include/opcode/ChangeLog

   1 include/opcode/ChangeLog
   2 2005-09-06  Chao-ying Fu  <fu@mips.com>
   3
   4         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
   5         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
   6         define.
   7         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
   8         (INSN_ASE_MASK): Update to include INSN_MT.
   9         (INSN_MT): New define for MT ASE.
  10
  11 2005-08-25  Chao-ying Fu  <fu@mips.com>
  12
  13         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
  14         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
  15         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
  16         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
  17         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
  18         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
  19         instructions.
  20         (INSN_DSP): New define for DSP ASE.
  21
  22 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
  23
  24         * a29k.h: Delete.
  25
  26 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
  27
  28         * ppc.h (PPC_OPCODE_E300): Define.
  29
  30 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
  31
  32         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
  33
  34 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  35
  36         PR gas/336
  37         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
  38         and pitlb.
  39
  40 2005-07-27  Jan Beulich  <jbeulich@novell.com>
  41
  42         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
  43         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
  44         Add movq-s as 64-bit variants of movd-s.
  45
  46 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  47
  48         * hppa.h: Fix punctuation in comment.
  49
  50         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
  51         implicit space-register addressing.  Set space-register bits on opcodes
  52         using implicit space-register addressing.  Add various missing pa20
  53         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
  54         space-register addressing.  Use "fE" instead of "fe" in various
  55         fstw opcodes.
  56
  57 2005-07-18  Jan Beulich  <jbeulich@novell.com>
  58
  59         * i386.h (i386_optab): Operands of aam and aad are unsigned.
  60
  61 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
  62
  63         * i386.h (i386_optab): Support Intel VMX Instructions.
  64
  65 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  66
  67         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
  68
  69 2005-07-05  Jan Beulich  <jbeulich@novell.com>
  70
  71         * i386.h (i386_optab): Add new insns.
  72
  73 2005-07-01  Nick Clifton  <nickc@redhat.com>
  74
  75         * sparc.h: Add typedefs to structure declarations.
  76
  77 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  78
  79         PR 1013
  80         * i386.h (i386_optab): Update comments for 64bit addressing on
  81         mov. Allow 64bit addressing for mov and movq.
  82
  83 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  84
  85         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  86         respectively, in various floating-point load and store patterns.
  87
  88 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  89
  90         * hppa.h (FLAG_STRICT): Correct comment.
  91         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  92         PA 2.0 mneumonics when equivalent.  Entries with cache control
  93         completers now require PA 1.1.  Adjust whitespace.
  94
  95 2005-05-19  Anton Blanchard  <anton@samba.org>
  96
  97         * ppc.h (PPC_OPCODE_POWER5): Define.
  98
  99 2005-05-10  Nick Clifton  <nickc@redhat.com>
 100
 101         * Update the address and phone number of the FSF organization in
 102         the GPL notices in the following files:
 103         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 104         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 105         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 106         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 107         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 108         tic54x.h, tic80.h, v850.h, vax.h
 109
 110 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 111
 112         * i386.h (i386_optab): Add ht and hnt.
 113
 114 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 115
 116         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 117         Add xcrypt-ctr.  Provide aliases without hyphens.
 118
 119 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 120
 121         Moved from ../ChangeLog
 122
 123         2005-04-12  Paul Brook  <paul@codesourcery.com>
 124         * m88k.h: Rename psr macros to avoid conflicts.
 125
 126         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 127         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 128         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 129         and ARM_ARCH_V6ZKT2.
 130
 131         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 132         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 133         Remove redundant instruction types.
 134         (struct argument): X_op - new field.
 135         (struct cst4_entry): Remove.
 136         (no_op_insn): Declare.
 137
 138         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 139         * crx.h (enum argtype): Rename types, remove unused types.
 140
 141         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 142         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 143         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 144         (enum operand_type): Rearrange operands, edit comments.
 145         replace us<N> with ui<N> for unsigned immediate.
 146         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 147         displacements (respectively).
 148         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 149         (instruction type): Add NO_TYPE_INS.
 150         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 151         (operand_entry): New field - 'flags'.
 152         (operand flags): New.
 153
 154         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 155         * crx.h (operand_type): Remove redundant types i3, i4,
 156         i5, i8, i12.
 157         Add new unsigned immediate types us3, us4, us5, us16.
 158
 159 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 160
 161         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 162         adjust them accordingly.
 163
 164 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 165
 166         * i386.h (i386_optab): Add rdtscp.
 167
 168 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 169
 170         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 171         between memory and segment register. Allow movq for moving between
 172         general-purpose register and segment register.
 173
 174 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 175
 176         PR gas/707
 177         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 178         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 179         fnstsw.
 180
 181 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 182
 183         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 184         * cgen.h (enum cgen_parse_operand_type): Add
 185         CGEN_PARSE_OPERAND_SYMBOLIC.
 186
 187 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 188
 189         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 190         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 191         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 192
 193 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 194
 195         * mips.h (struct mips_opcode): Add new pinfo2 member.
 196         (INSN_ALIAS): New define for opcode table entries that are
 197         specific instances of another entry, such as 'move' for an 'or'
 198         with a zero operand.
 199         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 200         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 201
 202 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 203
 204         * mips.h (CPU_RM9000): Define.
 205         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 206
 207 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 208
 209         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 210         to/from test registers are illegal in 64-bit mode. Add missing
 211         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 212         (previously one had to explicitly encode a rex64 prefix). Re-enable
 213         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 214         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 215
 216 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 217
 218         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 219         available only with SSE2. Change the MMX additions introduced by SSE
 220         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 221         instructions by their now designated identifier (since combining i686
 222         and 3DNow! does not really imply 3DNow!A).
 223
 224 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 225
 226         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 227         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 228
 229 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 230             Vineet Sharma      <vineets@noida.hcltech.com>
 231
 232         * maxq.h: New file: Disassembly information for the maxq port.
 233
 234 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 235
 236         * i386.h (i386_optab): Put back "movzb".
 237
 238 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 239
 240         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 241         comments.  Remove member cris_ver_sim.  Add members
 242         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 243         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 244         (struct cris_support_reg, struct cris_cond15): New types.
 245         (cris_conds15): Declare.
 246         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 247         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 248         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 249         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 250         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 251         SIZE_FIELD_UNSIGNED.
 252
 253 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 254
 255         * i386.h (sldx_Suf): Remove.
 256         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 257         (q_FP): Define, implying no REX64.
 258         (x_FP, sl_FP): Imply FloatMF.
 259         (i386_optab): Split reg and mem forms of moving from segment registers
 260         so that the memory forms can ignore the 16-/32-bit operand size
 261         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 262         all non-floating-point instructions. Unite 32- and 64-bit forms of
 263         movsx, movzx, and movd. Adjust floating point operations for the above
 264         changes to the *FP macros. Add DefaultSize to floating point control
 265         insns operating on larger memory ranges. Remove left over comments
 266         hinting at certain insns being Intel-syntax ones where the ones
 267         actually meant are already gone.
 268
 269 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 270
 271         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 272         instruction type.
 273
 274 2004-09-30  Paul Brook  <paul@codesourcery.com>
 275
 276         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 277         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 278
 279 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 280
 281         * avr.h: Add support for
 282         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 283
 284 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 285
 286         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 287
 288 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 289
 290         * msp430.h (msp430_opc): Add new instructions.
 291         (msp430_rcodes): Declare new instructions.
 292         (msp430_hcodes): Likewise..
 293
 294 2004-08-13  Nick Clifton  <nickc@redhat.com>
 295
 296         PR/301
 297         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 298         processors.
 299
 300 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 301
 302         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 303
 304 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 305
 306         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 307
 308 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 309
 310         * i386.h: Adjust instruction descriptions to better match the
 311         specification.
 312
 313 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 314
 315         * arm.h: Remove all old content.  Replace with architecture defines
 316         from gas/config/tc-arm.c.
 317
 318 2004-07-09  Andreas Schwab  <schwab@suse.de>
 319
 320         * m68k.h: Fix comment.
 321
 322 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 323
 324         * crx.h: New file.
 325
 326 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 327
 328         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 329
 330 2004-05-24  Peter Barada  <peter@the-baradas.com>
 331
 332         * m68k.h: Add 'size' to m68k_opcode.
 333
 334 2004-05-05  Peter Barada  <peter@the-baradas.com>
 335
 336         * m68k.h: Switch from ColdFire chip name to core variant.
 337
 338 2004-04-22  Peter Barada  <peter@the-baradas.com>
 339
 340         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 341         descriptions for new EMAC cases.
 342         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 343         handle Motorola MAC syntax.
 344         Allow disassembly of ColdFire V4e object files.
 345
 346 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 347
 348         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 349
 350 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 351
 352         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 353
 354 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 355
 356         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 357
 358 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 359
 360         * i386.h (i386_optab): Added xstore/xcrypt insns.
 361
 362 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 363
 364         * h8300.h (32bit ldc/stc): Add relaxing support.
 365
 366 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 367
 368         * h8300.h (BITOP): Pass MEMRELAX flag.
 369
 370 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 371
 372         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 373         except for the H8S.
 374
 375 For older changes see ChangeLog-9103
 376 \f
 377 Local Variables:
 378 mode: change-log
 379 left-margin: 8
 380 fill-column: 74
 381 version-control: never
 382 End: