include/opcode/ChangeLog

   1 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
   2
   3         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
   4         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
   5         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
   6         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
   7         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
   8
   9 2006-03-10  Paul Brook  <paul@codesourcery.com>
  10
  11         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
  12
  13 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  14
  15         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
  16         first.  Correct mask of bb "B" opcode.
  17
  18 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
  19
  20         * i386.h (i386_optab): Support Intel Merom New Instructions.
  21
  22 2006-02-24  Paul Brook  <paul@codesourcery.com>
  23
  24         * arm.h: Add V7 feature bits.
  25
  26 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
  27
  28         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
  29
  30 2006-01-31  Paul Brook  <paul@codesourcery.com>
  31         Richard Earnshaw <rearnsha@arm.com>
  32
  33         * arm.h: Use ARM_CPU_FEATURE.
  34         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
  35         (arm_feature_set): Change to a structure.
  36         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
  37         ARM_FEATURE): New macros.
  38
  39 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
  40
  41         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
  42         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
  43         (ADD_PC_INCR_OPCODE): Don't define.
  44
  45 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
  46
  47         PR gas/1874
  48         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
  49
  50 2005-11-14  David Ung  <davidu@mips.com>
  51
  52         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
  53         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
  54         save/restore encoding of the args field.
  55
  56 2005-10-28  Dave Brolley  <brolley@redhat.com>
  57
  58         Contribute the following changes:
  59         2005-02-16  Dave Brolley  <brolley@redhat.com>
  60
  61         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
  62         cgen_isa_mask_* to cgen_bitset_*.
  63         * cgen.h: Likewise.
  64
  65         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
  66
  67         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
  68         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
  69         (CGEN_CPU_TABLE): Make isas a ponter.
  70
  71         2003-09-29  Dave Brolley  <brolley@redhat.com>
  72
  73         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
  74         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
  75         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
  76
  77         2002-12-13  Dave Brolley  <brolley@redhat.com>
  78
  79         * cgen.h (symcat.h): #include it.
  80         (cgen-bitset.h): #include it.
  81         (CGEN_ATTR_VALUE_TYPE): Now a union.
  82         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
  83         (CGEN_ATTR_ENTRY): 'value' now unsigned.
  84         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
  85         * cgen-bitset.h: New file.
  86
  87 2005-09-30  Catherine Moore  <clm@cm00re.com>
  88
  89         * bfin.h: New file.
  90
  91 2005-10-24  Jan Beulich  <jbeulich@novell.com>
  92
  93         * ia64.h (enum ia64_opnd): Move memory operand out of set of
  94         indirect operands.
  95
  96 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  97
  98         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
  99         Add FLAG_STRICT to pa10 ftest opcode.
 100
 101 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 102
 103         * hppa.h (pa_opcodes): Remove lha entries.
 104
 105 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 106
 107         * hppa.h (FLAG_STRICT): Revise comment.
 108         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 109         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 110         entries for "fdc".
 111
 112 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 113
 114         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 115
 116 2005-09-06  Chao-ying Fu  <fu@mips.com>
 117
 118         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 119         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 120         define.
 121         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 122         (INSN_ASE_MASK): Update to include INSN_MT.
 123         (INSN_MT): New define for MT ASE.
 124
 125 2005-08-25  Chao-ying Fu  <fu@mips.com>
 126
 127         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 128         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 129         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 130         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 131         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 132         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 133         instructions.
 134         (INSN_DSP): New define for DSP ASE.
 135
 136 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 137
 138         * a29k.h: Delete.
 139
 140 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 141
 142         * ppc.h (PPC_OPCODE_E300): Define.
 143
 144 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 145
 146         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 147
 148 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 149
 150         PR gas/336
 151         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 152         and pitlb.
 153
 154 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 155
 156         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 157         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 158         Add movq-s as 64-bit variants of movd-s.
 159
 160 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 161
 162         * hppa.h: Fix punctuation in comment.
 163
 164         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 165         implicit space-register addressing.  Set space-register bits on opcodes
 166         using implicit space-register addressing.  Add various missing pa20
 167         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 168         space-register addressing.  Use "fE" instead of "fe" in various
 169         fstw opcodes.
 170
 171 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 172
 173         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 174
 175 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 176
 177         * i386.h (i386_optab): Support Intel VMX Instructions.
 178
 179 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 180
 181         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 182
 183 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 184
 185         * i386.h (i386_optab): Add new insns.
 186
 187 2005-07-01  Nick Clifton  <nickc@redhat.com>
 188
 189         * sparc.h: Add typedefs to structure declarations.
 190
 191 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         PR 1013
 194         * i386.h (i386_optab): Update comments for 64bit addressing on
 195         mov. Allow 64bit addressing for mov and movq.
 196
 197 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 198
 199         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 200         respectively, in various floating-point load and store patterns.
 201
 202 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 203
 204         * hppa.h (FLAG_STRICT): Correct comment.
 205         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 206         PA 2.0 mneumonics when equivalent.  Entries with cache control
 207         completers now require PA 1.1.  Adjust whitespace.
 208
 209 2005-05-19  Anton Blanchard  <anton@samba.org>
 210
 211         * ppc.h (PPC_OPCODE_POWER5): Define.
 212
 213 2005-05-10  Nick Clifton  <nickc@redhat.com>
 214
 215         * Update the address and phone number of the FSF organization in
 216         the GPL notices in the following files:
 217         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 218         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 219         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 220         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 221         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 222         tic54x.h, tic80.h, v850.h, vax.h
 223
 224 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 225
 226         * i386.h (i386_optab): Add ht and hnt.
 227
 228 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 229
 230         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 231         Add xcrypt-ctr.  Provide aliases without hyphens.
 232
 233 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 234
 235         Moved from ../ChangeLog
 236
 237         2005-04-12  Paul Brook  <paul@codesourcery.com>
 238         * m88k.h: Rename psr macros to avoid conflicts.
 239
 240         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 241         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 242         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 243         and ARM_ARCH_V6ZKT2.
 244
 245         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 246         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 247         Remove redundant instruction types.
 248         (struct argument): X_op - new field.
 249         (struct cst4_entry): Remove.
 250         (no_op_insn): Declare.
 251
 252         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 253         * crx.h (enum argtype): Rename types, remove unused types.
 254
 255         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 256         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 257         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 258         (enum operand_type): Rearrange operands, edit comments.
 259         replace us<N> with ui<N> for unsigned immediate.
 260         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 261         displacements (respectively).
 262         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 263         (instruction type): Add NO_TYPE_INS.
 264         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 265         (operand_entry): New field - 'flags'.
 266         (operand flags): New.
 267
 268         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 269         * crx.h (operand_type): Remove redundant types i3, i4,
 270         i5, i8, i12.
 271         Add new unsigned immediate types us3, us4, us5, us16.
 272
 273 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 274
 275         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 276         adjust them accordingly.
 277
 278 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 279
 280         * i386.h (i386_optab): Add rdtscp.
 281
 282 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 283
 284         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 285         between memory and segment register. Allow movq for moving between
 286         general-purpose register and segment register.
 287
 288 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 289
 290         PR gas/707
 291         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 292         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 293         fnstsw.
 294
 295 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 296
 297         * m68k.h (m68008, m68ec030, m68882): Remove.
 298         (m68k_mask): New.
 299         (cpu_m68k, cpu_cf): New.
 300         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 301         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 302
 303 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 304
 305         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 306         * cgen.h (enum cgen_parse_operand_type): Add
 307         CGEN_PARSE_OPERAND_SYMBOLIC.
 308
 309 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 310
 311         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 312         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 313         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 314
 315 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 316
 317         * mips.h (struct mips_opcode): Add new pinfo2 member.
 318         (INSN_ALIAS): New define for opcode table entries that are
 319         specific instances of another entry, such as 'move' for an 'or'
 320         with a zero operand.
 321         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 322         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 323
 324 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 325
 326         * mips.h (CPU_RM9000): Define.
 327         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 328
 329 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 330
 331         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 332         to/from test registers are illegal in 64-bit mode. Add missing
 333         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 334         (previously one had to explicitly encode a rex64 prefix). Re-enable
 335         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 336         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 337
 338 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 339
 340         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 341         available only with SSE2. Change the MMX additions introduced by SSE
 342         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 343         instructions by their now designated identifier (since combining i686
 344         and 3DNow! does not really imply 3DNow!A).
 345
 346 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 347
 348         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 349         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 350
 351 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 352             Vineet Sharma      <vineets@noida.hcltech.com>
 353
 354         * maxq.h: New file: Disassembly information for the maxq port.
 355
 356 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 357
 358         * i386.h (i386_optab): Put back "movzb".
 359
 360 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 361
 362         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 363         comments.  Remove member cris_ver_sim.  Add members
 364         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 365         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 366         (struct cris_support_reg, struct cris_cond15): New types.
 367         (cris_conds15): Declare.
 368         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 369         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 370         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 371         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 372         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 373         SIZE_FIELD_UNSIGNED.
 374
 375 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 376
 377         * i386.h (sldx_Suf): Remove.
 378         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 379         (q_FP): Define, implying no REX64.
 380         (x_FP, sl_FP): Imply FloatMF.
 381         (i386_optab): Split reg and mem forms of moving from segment registers
 382         so that the memory forms can ignore the 16-/32-bit operand size
 383         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 384         all non-floating-point instructions. Unite 32- and 64-bit forms of
 385         movsx, movzx, and movd. Adjust floating point operations for the above
 386         changes to the *FP macros. Add DefaultSize to floating point control
 387         insns operating on larger memory ranges. Remove left over comments
 388         hinting at certain insns being Intel-syntax ones where the ones
 389         actually meant are already gone.
 390
 391 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 392
 393         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 394         instruction type.
 395
 396 2004-09-30  Paul Brook  <paul@codesourcery.com>
 397
 398         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 399         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 400
 401 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 402
 403         * avr.h: Add support for
 404         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 405
 406 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 407
 408         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 409
 410 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 411
 412         * msp430.h (msp430_opc): Add new instructions.
 413         (msp430_rcodes): Declare new instructions.
 414         (msp430_hcodes): Likewise..
 415
 416 2004-08-13  Nick Clifton  <nickc@redhat.com>
 417
 418         PR/301
 419         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 420         processors.
 421
 422 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 423
 424         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 425
 426 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 427
 428         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 429
 430 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 431
 432         * i386.h: Adjust instruction descriptions to better match the
 433         specification.
 434
 435 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 436
 437         * arm.h: Remove all old content.  Replace with architecture defines
 438         from gas/config/tc-arm.c.
 439
 440 2004-07-09  Andreas Schwab  <schwab@suse.de>
 441
 442         * m68k.h: Fix comment.
 443
 444 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 445
 446         * crx.h: New file.
 447
 448 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 449
 450         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 451
 452 2004-05-24  Peter Barada  <peter@the-baradas.com>
 453
 454         * m68k.h: Add 'size' to m68k_opcode.
 455
 456 2004-05-05  Peter Barada  <peter@the-baradas.com>
 457
 458         * m68k.h: Switch from ColdFire chip name to core variant.
 459
 460 2004-04-22  Peter Barada  <peter@the-baradas.com>
 461
 462         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 463         descriptions for new EMAC cases.
 464         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 465         handle Motorola MAC syntax.
 466         Allow disassembly of ColdFire V4e object files.
 467
 468 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 469
 470         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 471
 472 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 473
 474         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 475
 476 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 477
 478         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 479
 480 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 481
 482         * i386.h (i386_optab): Added xstore/xcrypt insns.
 483
 484 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 485
 486         * h8300.h (32bit ldc/stc): Add relaxing support.
 487
 488 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 489
 490         * h8300.h (BITOP): Pass MEMRELAX flag.
 491
 492 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 493
 494         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 495         except for the H8S.
 496
 497 For older changes see ChangeLog-9103
 498 \f
 499 Local Variables:
 500 mode: change-log
 501 left-margin: 8
 502 fill-column: 74
 503 version-control: never
 504 End: