include/opcode/ChangeLog

   1 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
   4
   5 2009-09-29  DJ Delorie  <dj@redhat.com>
   6
   7         * rx.h: New file.
   8
   9 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
  10
  11         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
  12
  13 2009-09-21  Ben Elliston  <bje@au.ibm.com>
  14
  15         * ppc.h (PPC_OPCODE_PPCA2): New.
  16
  17 2009-09-05  Martin Thuresson  <martin@mtme.org>
  18
  19         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  20
  21 2009-08-29  Martin Thuresson  <martin@mtme.org>
  22
  23         * tic30.h (template): Rename type template to
  24         insn_template. Updated code to use new name.
  25         * tic54x.h (template): Rename type template to
  26         insn_template.
  27
  28 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  29
  30         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  31
  32 2009-06-11  Anthony Green  <green@moxielogic.com>
  33
  34         * moxie.h (MOXIE_F3_PCREL): Define.
  35         (moxie_form3_opc_info): Grow.
  36
  37 2009-06-06  Anthony Green  <green@moxielogic.com>
  38
  39         * moxie.h (MOXIE_F1_M): Define.
  40
  41 2009-04-15  Anthony Green  <green@moxielogic.com>
  42
  43         * moxie.h: Created.
  44
  45 2009-04-06  DJ Delorie  <dj@redhat.com>
  46
  47         * h8300.h: Add relaxation attributes to MOVA opcodes.
  48
  49 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  50
  51         * ppc.h (ppc_parse_cpu): Declare.
  52
  53 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  54
  55         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  56         and _IMM11 for mbitclr and mbitset.
  57         * score-datadep.h: Update dependency information.
  58
  59 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  60
  61         * ppc.h (PPC_OPCODE_POWER7): New.
  62
  63 2009-02-06  Doug Evans  <dje@google.com>
  64
  65         * i386.h: Add comment regarding sse* insns and prefixes.
  66
  67 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  68
  69         * mips.h (INSN_XLR): Define.
  70         (INSN_CHIP_MASK): Update.
  71         (CPU_XLR): Define.
  72         (OPCODE_IS_MEMBER): Update.
  73         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  74
  75 2009-01-28  Doug Evans  <dje@google.com>
  76
  77         * opcode/i386.h: Add multiple inclusion protection.
  78         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  79         (EDI_REG_NUM): New macros.
  80         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  81         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  82         (REX_PREFIX_P): New macro.
  83
  84 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  85
  86         * ppc.h (struct powerpc_opcode): New field "deprecated".
  87         (PPC_OPCODE_NOPOWER4): Delete.
  88
  89 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  90
  91         * mips.h: Define CPU_R14000, CPU_R16000.
  92         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  93
  94 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  95
  96         * arm.h (FPU_NEON_FP16): New.
  97         (FPU_ARCH_NEON_FP16): New.
  98
  99 2008-11-06  Chao-ying Fu  <fu@mips.com>
 100
 101         * mips.h: Doucument '1' for 5-bit sync type.
 102
 103 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 106         IA64_RS_CR.
 107
 108 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 109
 110         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 111
 112 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 113
 114         * ppc.h (PPC_OPCODE_405): Define.
 115         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 116
 117 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 118
 119         * ppc.h (ppc_cpu_t): New typedef.
 120         (struct powerpc_opcode <flags>): Use it.
 121         (struct powerpc_operand <insert, extract>): Likewise.
 122         (struct powerpc_macro <flags>): Likewise.
 123
 124 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 125
 126         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 127         Update comment before MIPS16 field descriptors to mention MIPS16.
 128         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 129         BBIT.
 130         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 131         New bit masks and shift counts for cins and exts.
 132
 133         * mips.h: Document new field descriptors +Q.
 134         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 135
 136 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 137
 138         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 139         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 140
 141 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 142
 143         * ppc.h: (PPC_OPCODE_E500MC): New.
 144
 145 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 146
 147         * i386.h (MAX_OPERANDS): Set to 5.
 148         (MAX_MNEM_SIZE): Changed to 20.
 149
 150 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 151
 152         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 153
 154 2008-03-09  Paul Brook  <paul@codesourcery.com>
 155
 156         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 157
 158 2008-03-04  Paul Brook  <paul@codesourcery.com>
 159
 160         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 161         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 162         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 163
 164 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 165             Nick Clifton  <nickc@redhat.com>
 166
 167         PR 3134
 168         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 169         with a 32-bit displacement but without the top bit of the 4th byte
 170         set.
 171
 172 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 173
 174         * cr16.h (cr16_num_optab): Declared.
 175
 176 2008-02-14  Hakan Ardo  <hakan@debian.org>
 177
 178         PR gas/2626
 179         * avr.h (AVR_ISA_2xxe): Define.
 180
 181 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 182
 183         * mips.h: Update copyright.
 184         (INSN_CHIP_MASK): New macro.
 185         (INSN_OCTEON): New macro.
 186         (CPU_OCTEON): New macro.
 187         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 188
 189 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 190
 191         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 192
 193 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 194
 195         * avr.h (AVR_ISA_USB162): Add new opcode set.
 196         (AVR_ISA_AVR3): Likewise.
 197
 198 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 199
 200         * mips.h (INSN_LOONGSON_2E): New.
 201         (INSN_LOONGSON_2F): New.
 202         (CPU_LOONGSON_2E): New.
 203         (CPU_LOONGSON_2F): New.
 204         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 205
 206 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 207
 208         * mips.h (INSN_ISA*): Redefine certain values as an
 209         enumeration.  Update comments.
 210         (mips_isa_table): New.
 211         (ISA_MIPS*): Redefine to match enumeration.
 212         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 213         values.
 214
 215 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 216
 217         * ppc.h (PPC_OPCODE_PPCPS): New.
 218
 219 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 220
 221         * m68k.h: Document j K & E.
 222
 223 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 224
 225         * cr16.h: New file for CR16 target.
 226
 227 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 228
 229         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 230
 231 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 232
 233         * m68k.h (mcfisa_c): New.
 234         (mcfusp, mcf_mask): Adjust.
 235
 236 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 237
 238         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 239         (num_powerpc_operands): Declare.
 240         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 241         (PPC_OPERAND_PLUS1): Define.
 242
 243 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 244
 245         * i386.h (REX_MODE64): Renamed to ...
 246         (REX_W): This.
 247         (REX_EXTX): Renamed to ...
 248         (REX_R): This.
 249         (REX_EXTY): Renamed to ...
 250         (REX_X): This.
 251         (REX_EXTZ): Renamed to ...
 252         (REX_B): This.
 253
 254 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 255
 256         * i386.h: Add entries from config/tc-i386.h and move tables
 257         to opcodes/i386-opc.h.
 258
 259 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 260
 261         * i386.h (FloatDR): Removed.
 262         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 263
 264 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 265
 266         * spu-insns.h: Add soma double-float insns.
 267
 268 2007-02-20  Thiemo Seufer  <ths@mips.com>
 269             Chao-Ying Fu  <fu@mips.com>
 270
 271         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 272         (INSN_DSPR2): Add flag for DSP R2 instructions.
 273         (M_BALIGN): New macro.
 274
 275 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 276
 277         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 278         and Seg3ShortFrom with Shortform.
 279
 280 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 281
 282         PR gas/4027
 283         * i386.h (i386_optab): Put the real "test" before the pseudo
 284         one.
 285
 286 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 287
 288         * m68k.h (m68010up): OR fido_a.
 289
 290 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 291
 292         * m68k.h (fido_a): New.
 293
 294 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 295
 296         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 297         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 298         values.
 299
 300 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 301
 302         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 303
 304 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 305
 306         * score-inst.h (enum score_insn_type): Add Insn_internal.
 307
 308 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 309             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 310             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 311             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 312             Alan Modra  <amodra@bigpond.net.au>
 313
 314         * spu-insns.h: New file.
 315         * spu.h: New file.
 316
 317 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 318
 319         * ppc.h (PPC_OPCODE_CELL): Define.
 320
 321 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 322
 323         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 324         in amdfam10 architecture.
 325
 326 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 327
 328         * i386.h: Replace CpuMNI with CpuSSSE3.
 329
 330 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 331             Joseph Myers  <joseph@codesourcery.com>
 332             Ian Lance Taylor  <ian@wasabisystems.com>
 333             Ben Elliston  <bje@wasabisystems.com>
 334
 335         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 336
 337 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 338
 339         * score-datadep.h: New file.
 340         * score-inst.h: New file.
 341
 342 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 343
 344         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 345         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 346         movdq2q and movq2dq.
 347
 348 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 349            Michael Meissner             <michael.meissner@amd.com>
 350
 351         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 352
 353 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 354
 355         * i386.h (i386_optab): Add "nop" with memory reference.
 356
 357 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 358
 359         * i386.h (i386_optab): Update comment for 64bit NOP.
 360
 361 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 362             Anton Blanchard  <anton@samba.org>
 363
 364         * ppc.h (PPC_OPCODE_POWER6): Define.
 365         Adjust whitespace.
 366
 367 2006-06-05  Thiemo Seufer  <ths@mips.com>
 368
 369         * mips.h: Improve description of MT flags.
 370
 371 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 372
 373         * m68k.h (mcf_mask): Define.
 374
 375 2006-05-05  Thiemo Seufer  <ths@mips.com>
 376             David Ung  <davidu@mips.com>
 377
 378         * mips.h (enum): Add macro M_CACHE_AB.
 379
 380 2006-05-04  Thiemo Seufer  <ths@mips.com>
 381             Nigel Stephens  <nigel@mips.com>
 382             David Ung  <davidu@mips.com>
 383
 384         * mips.h: Add INSN_SMARTMIPS define.
 385
 386 2006-04-30  Thiemo Seufer  <ths@mips.com>
 387             David Ung  <davidu@mips.com>
 388
 389         * mips.h: Defines udi bits and masks.  Add description of
 390         characters which may appear in the args field of udi
 391         instructions.
 392
 393 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 394
 395         * mips.h: Improve comments describing the bitfield instruction
 396         fields.
 397
 398 2006-04-26  Julian Brown  <julian@codesourcery.com>
 399
 400         * arm.h (FPU_VFP_EXT_V3): Define constant.
 401         (FPU_NEON_EXT_V1): Likewise.
 402         (FPU_VFP_HARD): Update.
 403         (FPU_VFP_V3): Define macro.
 404         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 405
 406 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 407
 408         * avr.h (AVR_ISA_PWMx): New.
 409
 410 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 411
 412         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 413         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 414         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 415         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 416         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 417
 418 2006-03-10  Paul Brook  <paul@codesourcery.com>
 419
 420         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 421
 422 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 425         first.  Correct mask of bb "B" opcode.
 426
 427 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 428
 429         * i386.h (i386_optab): Support Intel Merom New Instructions.
 430
 431 2006-02-24  Paul Brook  <paul@codesourcery.com>
 432
 433         * arm.h: Add V7 feature bits.
 434
 435 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 436
 437         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 438
 439 2006-01-31  Paul Brook  <paul@codesourcery.com>
 440         Richard Earnshaw <rearnsha@arm.com>
 441
 442         * arm.h: Use ARM_CPU_FEATURE.
 443         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 444         (arm_feature_set): Change to a structure.
 445         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 446         ARM_FEATURE): New macros.
 447
 448 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 449
 450         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 451         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 452         (ADD_PC_INCR_OPCODE): Don't define.
 453
 454 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 455
 456         PR gas/1874
 457         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 458
 459 2005-11-14  David Ung  <davidu@mips.com>
 460
 461         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 462         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 463         save/restore encoding of the args field.
 464
 465 2005-10-28  Dave Brolley  <brolley@redhat.com>
 466
 467         Contribute the following changes:
 468         2005-02-16  Dave Brolley  <brolley@redhat.com>
 469
 470         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 471         cgen_isa_mask_* to cgen_bitset_*.
 472         * cgen.h: Likewise.
 473
 474         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 475
 476         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 477         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 478         (CGEN_CPU_TABLE): Make isas a ponter.
 479
 480         2003-09-29  Dave Brolley  <brolley@redhat.com>
 481
 482         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 483         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 484         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 485
 486         2002-12-13  Dave Brolley  <brolley@redhat.com>
 487
 488         * cgen.h (symcat.h): #include it.
 489         (cgen-bitset.h): #include it.
 490         (CGEN_ATTR_VALUE_TYPE): Now a union.
 491         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 492         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 493         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 494         * cgen-bitset.h: New file.
 495
 496 2005-09-30  Catherine Moore  <clm@cm00re.com>
 497
 498         * bfin.h: New file.
 499
 500 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 501
 502         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 503         indirect operands.
 504
 505 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 506
 507         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 508         Add FLAG_STRICT to pa10 ftest opcode.
 509
 510 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 511
 512         * hppa.h (pa_opcodes): Remove lha entries.
 513
 514 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 515
 516         * hppa.h (FLAG_STRICT): Revise comment.
 517         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 518         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 519         entries for "fdc".
 520
 521 2005-09-30  Catherine Moore  <clm@cm00re.com>
 522
 523         * bfin.h: New file.
 524
 525 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 526
 527         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 528
 529 2005-09-06  Chao-ying Fu  <fu@mips.com>
 530
 531         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 532         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 533         define.
 534         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 535         (INSN_ASE_MASK): Update to include INSN_MT.
 536         (INSN_MT): New define for MT ASE.
 537
 538 2005-08-25  Chao-ying Fu  <fu@mips.com>
 539
 540         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 541         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 542         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 543         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 544         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 545         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 546         instructions.
 547         (INSN_DSP): New define for DSP ASE.
 548
 549 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 550
 551         * a29k.h: Delete.
 552
 553 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 554
 555         * ppc.h (PPC_OPCODE_E300): Define.
 556
 557 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 558
 559         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 560
 561 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 562
 563         PR gas/336
 564         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 565         and pitlb.
 566
 567 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 568
 569         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 570         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 571         Add movq-s as 64-bit variants of movd-s.
 572
 573 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 574
 575         * hppa.h: Fix punctuation in comment.
 576
 577         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 578         implicit space-register addressing.  Set space-register bits on opcodes
 579         using implicit space-register addressing.  Add various missing pa20
 580         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 581         space-register addressing.  Use "fE" instead of "fe" in various
 582         fstw opcodes.
 583
 584 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 585
 586         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 587
 588 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 589
 590         * i386.h (i386_optab): Support Intel VMX Instructions.
 591
 592 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 593
 594         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 595
 596 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 597
 598         * i386.h (i386_optab): Add new insns.
 599
 600 2005-07-01  Nick Clifton  <nickc@redhat.com>
 601
 602         * sparc.h: Add typedefs to structure declarations.
 603
 604 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 605
 606         PR 1013
 607         * i386.h (i386_optab): Update comments for 64bit addressing on
 608         mov. Allow 64bit addressing for mov and movq.
 609
 610 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 611
 612         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 613         respectively, in various floating-point load and store patterns.
 614
 615 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 616
 617         * hppa.h (FLAG_STRICT): Correct comment.
 618         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 619         PA 2.0 mneumonics when equivalent.  Entries with cache control
 620         completers now require PA 1.1.  Adjust whitespace.
 621
 622 2005-05-19  Anton Blanchard  <anton@samba.org>
 623
 624         * ppc.h (PPC_OPCODE_POWER5): Define.
 625
 626 2005-05-10  Nick Clifton  <nickc@redhat.com>
 627
 628         * Update the address and phone number of the FSF organization in
 629         the GPL notices in the following files:
 630         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 631         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 632         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 633         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 634         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 635         tic54x.h, tic80.h, v850.h, vax.h
 636
 637 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 638
 639         * i386.h (i386_optab): Add ht and hnt.
 640
 641 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 642
 643         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 644         Add xcrypt-ctr.  Provide aliases without hyphens.
 645
 646 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 647
 648         Moved from ../ChangeLog
 649
 650         2005-04-12  Paul Brook  <paul@codesourcery.com>
 651         * m88k.h: Rename psr macros to avoid conflicts.
 652
 653         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 654         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 655         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 656         and ARM_ARCH_V6ZKT2.
 657
 658         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 659         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 660         Remove redundant instruction types.
 661         (struct argument): X_op - new field.
 662         (struct cst4_entry): Remove.
 663         (no_op_insn): Declare.
 664
 665         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 666         * crx.h (enum argtype): Rename types, remove unused types.
 667
 668         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 669         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 670         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 671         (enum operand_type): Rearrange operands, edit comments.
 672         replace us<N> with ui<N> for unsigned immediate.
 673         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 674         displacements (respectively).
 675         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 676         (instruction type): Add NO_TYPE_INS.
 677         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 678         (operand_entry): New field - 'flags'.
 679         (operand flags): New.
 680
 681         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 682         * crx.h (operand_type): Remove redundant types i3, i4,
 683         i5, i8, i12.
 684         Add new unsigned immediate types us3, us4, us5, us16.
 685
 686 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 687
 688         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 689         adjust them accordingly.
 690
 691 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 692
 693         * i386.h (i386_optab): Add rdtscp.
 694
 695 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 696
 697         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 698         between memory and segment register. Allow movq for moving between
 699         general-purpose register and segment register.
 700
 701 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 702
 703         PR gas/707
 704         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 705         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 706         fnstsw.
 707
 708 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 709
 710         * m68k.h (m68008, m68ec030, m68882): Remove.
 711         (m68k_mask): New.
 712         (cpu_m68k, cpu_cf): New.
 713         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 714         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 715
 716 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 717
 718         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 719         * cgen.h (enum cgen_parse_operand_type): Add
 720         CGEN_PARSE_OPERAND_SYMBOLIC.
 721
 722 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 723
 724         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 725         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 726         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 727
 728 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 729
 730         * mips.h (struct mips_opcode): Add new pinfo2 member.
 731         (INSN_ALIAS): New define for opcode table entries that are
 732         specific instances of another entry, such as 'move' for an 'or'
 733         with a zero operand.
 734         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 735         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 736
 737 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 738
 739         * mips.h (CPU_RM9000): Define.
 740         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 741
 742 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 743
 744         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 745         to/from test registers are illegal in 64-bit mode. Add missing
 746         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 747         (previously one had to explicitly encode a rex64 prefix). Re-enable
 748         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 749         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 750
 751 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 752
 753         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 754         available only with SSE2. Change the MMX additions introduced by SSE
 755         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 756         instructions by their now designated identifier (since combining i686
 757         and 3DNow! does not really imply 3DNow!A).
 758
 759 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 760
 761         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 762         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 763
 764 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 765             Vineet Sharma      <vineets@noida.hcltech.com>
 766
 767         * maxq.h: New file: Disassembly information for the maxq port.
 768
 769 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 770
 771         * i386.h (i386_optab): Put back "movzb".
 772
 773 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 774
 775         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 776         comments.  Remove member cris_ver_sim.  Add members
 777         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 778         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 779         (struct cris_support_reg, struct cris_cond15): New types.
 780         (cris_conds15): Declare.
 781         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 782         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 783         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 784         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 785         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 786         SIZE_FIELD_UNSIGNED.
 787
 788 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 789
 790         * i386.h (sldx_Suf): Remove.
 791         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 792         (q_FP): Define, implying no REX64.
 793         (x_FP, sl_FP): Imply FloatMF.
 794         (i386_optab): Split reg and mem forms of moving from segment registers
 795         so that the memory forms can ignore the 16-/32-bit operand size
 796         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 797         all non-floating-point instructions. Unite 32- and 64-bit forms of
 798         movsx, movzx, and movd. Adjust floating point operations for the above
 799         changes to the *FP macros. Add DefaultSize to floating point control
 800         insns operating on larger memory ranges. Remove left over comments
 801         hinting at certain insns being Intel-syntax ones where the ones
 802         actually meant are already gone.
 803
 804 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 805
 806         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 807         instruction type.
 808
 809 2004-09-30  Paul Brook  <paul@codesourcery.com>
 810
 811         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 812         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 813
 814 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 815
 816         * avr.h: Add support for
 817         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 818
 819 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 820
 821         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 822
 823 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 824
 825         * msp430.h (msp430_opc): Add new instructions.
 826         (msp430_rcodes): Declare new instructions.
 827         (msp430_hcodes): Likewise..
 828
 829 2004-08-13  Nick Clifton  <nickc@redhat.com>
 830
 831         PR/301
 832         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 833         processors.
 834
 835 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 836
 837         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 838
 839 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 840
 841         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 842
 843 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 844
 845         * i386.h: Adjust instruction descriptions to better match the
 846         specification.
 847
 848 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 849
 850         * arm.h: Remove all old content.  Replace with architecture defines
 851         from gas/config/tc-arm.c.
 852
 853 2004-07-09  Andreas Schwab  <schwab@suse.de>
 854
 855         * m68k.h: Fix comment.
 856
 857 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 858
 859         * crx.h: New file.
 860
 861 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 862
 863         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 864
 865 2004-05-24  Peter Barada  <peter@the-baradas.com>
 866
 867         * m68k.h: Add 'size' to m68k_opcode.
 868
 869 2004-05-05  Peter Barada  <peter@the-baradas.com>
 870
 871         * m68k.h: Switch from ColdFire chip name to core variant.
 872
 873 2004-04-22  Peter Barada  <peter@the-baradas.com>
 874
 875         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 876         descriptions for new EMAC cases.
 877         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 878         handle Motorola MAC syntax.
 879         Allow disassembly of ColdFire V4e object files.
 880
 881 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 882
 883         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 884
 885 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 886
 887         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 888
 889 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 890
 891         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 892
 893 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 894
 895         * i386.h (i386_optab): Added xstore/xcrypt insns.
 896
 897 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 898
 899         * h8300.h (32bit ldc/stc): Add relaxing support.
 900
 901 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 902
 903         * h8300.h (BITOP): Pass MEMRELAX flag.
 904
 905 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 906
 907         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 908         except for the H8S.
 909
 910 For older changes see ChangeLog-9103
 911 \f
 912 Local Variables:
 913 mode: change-log
 914 left-margin: 8
 915 fill-column: 74
 916 version-control: never
 917 End: