include/opcode/ChangeLog

   1 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
   2
   3         * i386.h: Insert hyphens into selected VIA PadLock extensions.
   4         Add xcrypt-ctr.  Provide aliases without hyphens.
   5
   6 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
   7
   8         Moved from ../ChangeLog
   9
  10         2005-04-12  Paul Brook  <paul@codesourcery.com>
  11         * m88k.h: Rename psr macros to avoid conflicts.
  12
  13         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  14         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  15         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  16         and ARM_ARCH_V6ZKT2.
  17
  18         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  19         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  20         Remove redundant instruction types.
  21         (struct argument): X_op - new field.
  22         (struct cst4_entry): Remove.
  23         (no_op_insn): Declare.
  24
  25         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
  26         * crx.h (enum argtype): Rename types, remove unused types.
  27
  28         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
  29         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
  30         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
  31         (enum operand_type): Rearrange operands, edit comments.
  32         replace us<N> with ui<N> for unsigned immediate.
  33         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
  34         displacements (respectively).
  35         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
  36         (instruction type): Add NO_TYPE_INS.
  37         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
  38         (operand_entry): New field - 'flags'.
  39         (operand flags): New.
  40
  41         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
  42         * crx.h (operand_type): Remove redundant types i3, i4,
  43         i5, i8, i12.
  44         Add new unsigned immediate types us3, us4, us5, us16.
  45
  46 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
  47
  48         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
  49         adjust them accordingly.
  50
  51 2005-04-01  Jan Beulich  <jbeulich@novell.com>
  52
  53         * i386.h (i386_optab): Add rdtscp.
  54
  55 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
  56
  57         * i386.h (i386_optab): Don't allow the `l' suffix for moving
  58         between memory and segment register. Allow movq for moving between
  59         general-purpose register and segment register.
  60
  61 2005-02-09  Jan Beulich  <jbeulich@novell.com>
  62
  63         PR gas/707
  64         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
  65         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
  66         fnstsw.
  67
  68 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
  69
  70         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
  71         * cgen.h (enum cgen_parse_operand_type): Add
  72         CGEN_PARSE_OPERAND_SYMBOLIC.
  73
  74 2005-01-21  Fred Fish  <fnf@specifixinc.com>
  75
  76         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  77         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  78         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  79
  80 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  81
  82         * mips.h (struct mips_opcode): Add new pinfo2 member.
  83         (INSN_ALIAS): New define for opcode table entries that are
  84         specific instances of another entry, such as 'move' for an 'or'
  85         with a zero operand.
  86         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  87         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  88
  89 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  90
  91         * mips.h (CPU_RM9000): Define.
  92         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  93
  94 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  95
  96         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  97         to/from test registers are illegal in 64-bit mode. Add missing
  98         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  99         (previously one had to explicitly encode a rex64 prefix). Re-enable
 100         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 101         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 102
 103 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 104
 105         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 106         available only with SSE2. Change the MMX additions introduced by SSE
 107         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 108         instructions by their now designated identifier (since combining i686
 109         and 3DNow! does not really imply 3DNow!A).
 110
 111 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 112
 113         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 114         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 115
 116 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 117             Vineet Sharma      <vineets@noida.hcltech.com>
 118
 119         * maxq.h: New file: Disassembly information for the maxq port.
 120
 121 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 122
 123         * i386.h (i386_optab): Put back "movzb".
 124
 125 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 126
 127         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 128         comments.  Remove member cris_ver_sim.  Add members
 129         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 130         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 131         (struct cris_support_reg, struct cris_cond15): New types.
 132         (cris_conds15): Declare.
 133         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 134         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 135         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 136         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 137         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 138         SIZE_FIELD_UNSIGNED.
 139
 140 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 141
 142         * i386.h (sldx_Suf): Remove.
 143         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 144         (q_FP): Define, implying no REX64.
 145         (x_FP, sl_FP): Imply FloatMF.
 146         (i386_optab): Split reg and mem forms of moving from segment registers
 147         so that the memory forms can ignore the 16-/32-bit operand size
 148         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 149         all non-floating-point instructions. Unite 32- and 64-bit forms of
 150         movsx, movzx, and movd. Adjust floating point operations for the above
 151         changes to the *FP macros. Add DefaultSize to floating point control
 152         insns operating on larger memory ranges. Remove left over comments
 153         hinting at certain insns being Intel-syntax ones where the ones
 154         actually meant are already gone.
 155
 156 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 157
 158         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 159         instruction type.
 160
 161 2004-09-30  Paul Brook  <paul@codesourcery.com>
 162
 163         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 164         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 165
 166 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 167
 168         * avr.h: Add support for
 169         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 170
 171 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 172
 173         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 174
 175 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 176
 177         * msp430.h (msp430_opc): Add new instructions.
 178         (msp430_rcodes): Declare new instructions.
 179         (msp430_hcodes): Likewise..
 180
 181 2004-08-13  Nick Clifton  <nickc@redhat.com>
 182
 183         PR/301
 184         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 185         processors.
 186
 187 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 188
 189         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 190
 191 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 192
 193         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 194
 195 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 196
 197         * i386.h: Adjust instruction descriptions to better match the
 198         specification.
 199
 200 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 201
 202         * arm.h: Remove all old content.  Replace with architecture defines
 203         from gas/config/tc-arm.c.
 204
 205 2004-07-09  Andreas Schwab  <schwab@suse.de>
 206
 207         * m68k.h: Fix comment.
 208
 209 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 210
 211         * crx.h: New file.
 212
 213 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 214
 215         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 216
 217 2004-05-24  Peter Barada  <peter@the-baradas.com>
 218
 219         * m68k.h: Add 'size' to m68k_opcode.
 220
 221 2004-05-05  Peter Barada  <peter@the-baradas.com>
 222
 223         * m68k.h: Switch from ColdFire chip name to core variant.
 224
 225 2004-04-22  Peter Barada  <peter@the-baradas.com>
 226
 227         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 228         descriptions for new EMAC cases.
 229         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 230         handle Motorola MAC syntax.
 231         Allow disassembly of ColdFire V4e object files.
 232
 233 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 234
 235         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 236
 237 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 238
 239         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 240
 241 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 242
 243         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 244
 245 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 246
 247         * i386.h (i386_optab): Added xstore/xcrypt insns.
 248
 249 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 250
 251         * h8300.h (32bit ldc/stc): Add relaxing support.
 252
 253 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 254
 255         * h8300.h (BITOP): Pass MEMRELAX flag.
 256
 257 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 258
 259         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 260         except for the H8S.
 261
 262 For older changes see ChangeLog-9103
 263 \f
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