include/opcode/ChangeLog

   1 2005-07-27  Jan Beulich  <jbeulich@novell.com>
   2
   3         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
   4         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
   5         Add movq-s as 64-bit variants of movd-s.
   6
   7 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
   8
   9         * hppa.h: Fix punctuation in comment.
  10
  11         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
  12         implicit space-register addressing.  Set space-register bits on opcodes
  13         using implicit space-register addressing.  Add various missing pa20
  14         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
  15         space-register addressing.  Use "fE" instead of "fe" in various
  16         fstw opcodes.
  17
  18 2005-07-18  Jan Beulich  <jbeulich@novell.com>
  19
  20         * i386.h (i386_optab): Operands of aam and aad are unsigned.
  21
  22 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
  23
  24         * i386.h (i386_optab): Support Intel VMX Instructions.
  25
  26 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  27
  28         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
  29
  30 2005-07-05  Jan Beulich  <jbeulich@novell.com>
  31
  32         * i386.h (i386_optab): Add new insns.
  33
  34 2005-07-01  Nick Clifton  <nickc@redhat.com>
  35
  36         * sparc.h: Add typedefs to structure declarations.
  37
  38 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
  39
  40         PR 1013
  41         * i386.h (i386_optab): Update comments for 64bit addressing on
  42         mov. Allow 64bit addressing for mov and movq.
  43
  44 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  45
  46         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
  47         respectively, in various floating-point load and store patterns.
  48
  49 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  50
  51         * hppa.h (FLAG_STRICT): Correct comment.
  52         (pa_opcodes): Update load and store entries to allow both PA 1.X and
  53         PA 2.0 mneumonics when equivalent.  Entries with cache control
  54         completers now require PA 1.1.  Adjust whitespace.
  55
  56 2005-05-19  Anton Blanchard  <anton@samba.org>
  57
  58         * ppc.h (PPC_OPCODE_POWER5): Define.
  59
  60 2005-05-10  Nick Clifton  <nickc@redhat.com>
  61
  62         * Update the address and phone number of the FSF organization in
  63         the GPL notices in the following files:
  64         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
  65         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
  66         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
  67         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
  68         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
  69         tic54x.h, tic80.h, v850.h, vax.h
  70
  71 2005-05-09  Jan Beulich  <jbeulich@novell.com>
  72
  73         * i386.h (i386_optab): Add ht and hnt.
  74
  75 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
  76
  77         * i386.h: Insert hyphens into selected VIA PadLock extensions.
  78         Add xcrypt-ctr.  Provide aliases without hyphens.
  79
  80 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
  81
  82         Moved from ../ChangeLog
  83
  84         2005-04-12  Paul Brook  <paul@codesourcery.com>
  85         * m88k.h: Rename psr macros to avoid conflicts.
  86
  87         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
  88         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
  89         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
  90         and ARM_ARCH_V6ZKT2.
  91
  92         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
  93         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
  94         Remove redundant instruction types.
  95         (struct argument): X_op - new field.
  96         (struct cst4_entry): Remove.
  97         (no_op_insn): Declare.
  98
  99         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 100         * crx.h (enum argtype): Rename types, remove unused types.
 101
 102         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 103         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 104         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 105         (enum operand_type): Rearrange operands, edit comments.
 106         replace us<N> with ui<N> for unsigned immediate.
 107         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 108         displacements (respectively).
 109         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 110         (instruction type): Add NO_TYPE_INS.
 111         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 112         (operand_entry): New field - 'flags'.
 113         (operand flags): New.
 114
 115         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 116         * crx.h (operand_type): Remove redundant types i3, i4,
 117         i5, i8, i12.
 118         Add new unsigned immediate types us3, us4, us5, us16.
 119
 120 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 121
 122         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 123         adjust them accordingly.
 124
 125 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 126
 127         * i386.h (i386_optab): Add rdtscp.
 128
 129 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 130
 131         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 132         between memory and segment register. Allow movq for moving between
 133         general-purpose register and segment register.
 134
 135 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 136
 137         PR gas/707
 138         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 139         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 140         fnstsw.
 141
 142 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 143
 144         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 145         * cgen.h (enum cgen_parse_operand_type): Add
 146         CGEN_PARSE_OPERAND_SYMBOLIC.
 147
 148 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 149
 150         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 151         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 152         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 153
 154 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 155
 156         * mips.h (struct mips_opcode): Add new pinfo2 member.
 157         (INSN_ALIAS): New define for opcode table entries that are
 158         specific instances of another entry, such as 'move' for an 'or'
 159         with a zero operand.
 160         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 161         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 162
 163 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 164
 165         * mips.h (CPU_RM9000): Define.
 166         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 167
 168 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 169
 170         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 171         to/from test registers are illegal in 64-bit mode. Add missing
 172         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 173         (previously one had to explicitly encode a rex64 prefix). Re-enable
 174         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 175         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 176
 177 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 178
 179         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 180         available only with SSE2. Change the MMX additions introduced by SSE
 181         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 182         instructions by their now designated identifier (since combining i686
 183         and 3DNow! does not really imply 3DNow!A).
 184
 185 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 186
 187         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 188         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 189
 190 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 191             Vineet Sharma      <vineets@noida.hcltech.com>
 192
 193         * maxq.h: New file: Disassembly information for the maxq port.
 194
 195 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 196
 197         * i386.h (i386_optab): Put back "movzb".
 198
 199 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 200
 201         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 202         comments.  Remove member cris_ver_sim.  Add members
 203         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 204         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 205         (struct cris_support_reg, struct cris_cond15): New types.
 206         (cris_conds15): Declare.
 207         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 208         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 209         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 210         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 211         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 212         SIZE_FIELD_UNSIGNED.
 213
 214 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 215
 216         * i386.h (sldx_Suf): Remove.
 217         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 218         (q_FP): Define, implying no REX64.
 219         (x_FP, sl_FP): Imply FloatMF.
 220         (i386_optab): Split reg and mem forms of moving from segment registers
 221         so that the memory forms can ignore the 16-/32-bit operand size
 222         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 223         all non-floating-point instructions. Unite 32- and 64-bit forms of
 224         movsx, movzx, and movd. Adjust floating point operations for the above
 225         changes to the *FP macros. Add DefaultSize to floating point control
 226         insns operating on larger memory ranges. Remove left over comments
 227         hinting at certain insns being Intel-syntax ones where the ones
 228         actually meant are already gone.
 229
 230 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 231
 232         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 233         instruction type.
 234
 235 2004-09-30  Paul Brook  <paul@codesourcery.com>
 236
 237         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 238         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 239
 240 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 241
 242         * avr.h: Add support for
 243         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 244
 245 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 246
 247         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 248
 249 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 250
 251         * msp430.h (msp430_opc): Add new instructions.
 252         (msp430_rcodes): Declare new instructions.
 253         (msp430_hcodes): Likewise..
 254
 255 2004-08-13  Nick Clifton  <nickc@redhat.com>
 256
 257         PR/301
 258         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 259         processors.
 260
 261 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 262
 263         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 264
 265 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 266
 267         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 268
 269 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 270
 271         * i386.h: Adjust instruction descriptions to better match the
 272         specification.
 273
 274 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 275
 276         * arm.h: Remove all old content.  Replace with architecture defines
 277         from gas/config/tc-arm.c.
 278
 279 2004-07-09  Andreas Schwab  <schwab@suse.de>
 280
 281         * m68k.h: Fix comment.
 282
 283 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 284
 285         * crx.h: New file.
 286
 287 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 288
 289         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 290
 291 2004-05-24  Peter Barada  <peter@the-baradas.com>
 292
 293         * m68k.h: Add 'size' to m68k_opcode.
 294
 295 2004-05-05  Peter Barada  <peter@the-baradas.com>
 296
 297         * m68k.h: Switch from ColdFire chip name to core variant.
 298
 299 2004-04-22  Peter Barada  <peter@the-baradas.com>
 300
 301         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 302         descriptions for new EMAC cases.
 303         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 304         handle Motorola MAC syntax.
 305         Allow disassembly of ColdFire V4e object files.
 306
 307 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 308
 309         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 310
 311 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 312
 313         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 314
 315 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 316
 317         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 318
 319 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 320
 321         * i386.h (i386_optab): Added xstore/xcrypt insns.
 322
 323 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 324
 325         * h8300.h (32bit ldc/stc): Add relaxing support.
 326
 327 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 328
 329         * h8300.h (BITOP): Pass MEMRELAX flag.
 330
 331 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 332
 333         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 334         except for the H8S.
 335
 336 For older changes see ChangeLog-9103
 337 \f
 338 Local Variables:
 339 mode: change-log
 340 left-margin: 8
 341 fill-column: 74
 342 version-control: never
 343 End: