include/opcode/ChangeLog

   1 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
   2
   3         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
   4         * cgen.h (enum cgen_parse_operand_type): Add
   5         CGEN_PARSE_OPERAND_SYMBOLIC.
   6
   7 2005-01-21  Fred Fish  <fnf@specifixinc.com>
   8
   9         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
  10         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
  11         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
  12
  13 2005-01-19  Fred Fish  <fnf@specifixinc.com>
  14
  15         * mips.h (struct mips_opcode): Add new pinfo2 member.
  16         (INSN_ALIAS): New define for opcode table entries that are
  17         specific instances of another entry, such as 'move' for an 'or'
  18         with a zero operand.
  19         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
  20         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
  21
  22 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
  23
  24         * mips.h (CPU_RM9000): Define.
  25         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
  26
  27 2004-11-25 Jan Beulich  <jbeulich@novell.com>
  28
  29         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
  30         to/from test registers are illegal in 64-bit mode. Add missing
  31         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  32         (previously one had to explicitly encode a rex64 prefix). Re-enable
  33         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  34         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  35
  36 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  37
  38         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
  39         available only with SSE2. Change the MMX additions introduced by SSE
  40         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
  41         instructions by their now designated identifier (since combining i686
  42         and 3DNow! does not really imply 3DNow!A).
  43
  44 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  45
  46         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
  47         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
  48
  49 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  50             Vineet Sharma      <vineets@noida.hcltech.com>
  51
  52         * maxq.h: New file: Disassembly information for the maxq port.
  53
  54 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
  55
  56         * i386.h (i386_optab): Put back "movzb".
  57
  58 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  59
  60         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  61         comments.  Remove member cris_ver_sim.  Add members
  62         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  63         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  64         (struct cris_support_reg, struct cris_cond15): New types.
  65         (cris_conds15): Declare.
  66         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  67         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  68         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  69         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  70         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  71         SIZE_FIELD_UNSIGNED.
  72
  73 2004-11-04 Jan Beulich  <jbeulich@novell.com>
  74
  75         * i386.h (sldx_Suf): Remove.
  76         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  77         (q_FP): Define, implying no REX64.
  78         (x_FP, sl_FP): Imply FloatMF.
  79         (i386_optab): Split reg and mem forms of moving from segment registers
  80         so that the memory forms can ignore the 16-/32-bit operand size
  81         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  82         all non-floating-point instructions. Unite 32- and 64-bit forms of
  83         movsx, movzx, and movd. Adjust floating point operations for the above
  84         changes to the *FP macros. Add DefaultSize to floating point control
  85         insns operating on larger memory ranges. Remove left over comments
  86         hinting at certain insns being Intel-syntax ones where the ones
  87         actually meant are already gone.
  88
  89 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  90
  91         * crx.h: Add COPS_REG_INS - Coprocessor Special register
  92         instruction type.
  93
  94 2004-09-30  Paul Brook  <paul@codesourcery.com>
  95
  96         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
  97         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
  98
  99 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 100
 101         * avr.h: Add support for
 102         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 103
 104 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 105
 106         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 107
 108 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 109
 110         * msp430.h (msp430_opc): Add new instructions.
 111         (msp430_rcodes): Declare new instructions.
 112         (msp430_hcodes): Likewise..
 113
 114 2004-08-13  Nick Clifton  <nickc@redhat.com>
 115
 116         PR/301
 117         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 118         processors.
 119
 120 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 121
 122         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 123
 124 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 125
 126         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 127
 128 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 129
 130         * i386.h: Adjust instruction descriptions to better match the
 131         specification.
 132
 133 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 134
 135         * arm.h: Remove all old content.  Replace with architecture defines
 136         from gas/config/tc-arm.c.
 137
 138 2004-07-09  Andreas Schwab  <schwab@suse.de>
 139
 140         * m68k.h: Fix comment.
 141
 142 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 143
 144         * crx.h: New file.
 145
 146 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 147
 148         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 149
 150 2004-05-24  Peter Barada  <peter@the-baradas.com>
 151
 152         * m68k.h: Add 'size' to m68k_opcode.
 153
 154 2004-05-05  Peter Barada  <peter@the-baradas.com>
 155
 156         * m68k.h: Switch from ColdFire chip name to core variant.
 157
 158 2004-04-22  Peter Barada  <peter@the-baradas.com>
 159
 160         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 161         descriptions for new EMAC cases.
 162         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 163         handle Motorola MAC syntax.
 164         Allow disassembly of ColdFire V4e object files.
 165
 166 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 167
 168         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 169
 170 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 171
 172         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 173
 174 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 175
 176         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 177
 178 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 179
 180         * i386.h (i386_optab): Added xstore/xcrypt insns.
 181
 182 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 183
 184         * h8300.h (32bit ldc/stc): Add relaxing support.
 185
 186 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 187
 188         * h8300.h (BITOP): Pass MEMRELAX flag.
 189
 190 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 191
 192         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 193         except for the H8S.
 194
 195 For older changes see ChangeLog-9103
 196 \f
 197 Local Variables:
 198 mode: change-log
 199 left-margin: 8
 200 fill-column: 74
 201 version-control: never
 202 End: