1 2011-02-04 Bernd Schmidt <bernds@codesourcery.com>
3 * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
4 * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
6 2010-12-31 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
9 * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit
12 2010-12-26 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
15 * hppa.h: Clear "d" bit in "add" and "sub" patterns.
17 2010-12-18 Richard Sandiford <rdsandiford@googlemail.com>
19 * mips.h: Update commentary after last commit.
21 2010-12-18 Mingjie Xing <mingjie.xing@gmail.com>
23 * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
24 (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
25 (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
27 2010-11-23 Richard Sandiford <rdsandiford@googlemail.com>
29 * mips.h: Fix previous commit.
31 2010-11-23 Maciej W. Rozycki <macro@linux-mips.org>
33 * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
34 (INSN_LOONGSON_3A): Clear bit 31.
36 2010-11-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
39 * arm.h (ARM_AEXT_V6M_ONLY): New define.
40 (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
41 (ARM_ARCH_V6M_ONLY): New define.
43 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
45 * mips.h (INSN_LOONGSON_3A): Defined.
46 (CPU_LOONGSON_3A): Defined.
47 (OPCODE_IS_MEMBER): Add LOONGSON_3A.
49 2010-10-09 Matt Rice <ratmice@gmail.com>
51 * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
52 (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
54 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
56 * arm.h (ARM_EXT_VIRT): New define.
57 (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
58 (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
61 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
63 * arm.h (ARM_AEXT_ADIV): New define.
64 (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
66 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
68 * arm.h (ARM_EXT_OS): New define.
69 (ARM_AEXT_V6SM): Likewise.
70 (ARM_ARCH_V6SM): Likewise.
72 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
74 * arm.h (ARM_EXT_MP): Add.
75 (ARM_ARCH_V7A_MP): Likewise.
77 2010-09-22 Mike Frysinger <vapier@gentoo.org>
79 * bfin.h: Declare pseudoChr structs/defines.
81 2010-09-21 Mike Frysinger <vapier@gentoo.org>
83 * bfin.h: Strip trailing whitespace.
85 2010-07-29 DJ Delorie <dj@redhat.com>
87 * rx.h (RX_Operand_Type): Add TwoReg.
88 (RX_Opcode_ID): Remove ediv and ediv2.
90 2010-07-27 DJ Delorie <dj@redhat.com>
92 * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
94 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
95 Ina Pandit <ina.pandit@kpitcummins.com>
97 * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
98 PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
100 Remove PROCESSOR_V850EA support.
101 (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
102 V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
103 V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
104 V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
105 V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
106 V850_OPERAND_PERCENT.
107 Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
109 Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
112 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
114 * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
115 (MIPS16_INSN_BRANCH): Rename to...
116 (MIPS16_INSN_COND_BRANCH): ... this.
118 2010-07-03 Alan Modra <amodra@gmail.com>
120 * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
121 Renumber other PPC_OPCODE defines.
123 2010-07-03 Alan Modra <amodra@gmail.com>
125 * ppc.h (PPC_OPCODE_COMMON): Expand comment.
127 2010-06-29 Alan Modra <amodra@gmail.com>
129 * maxq.h: Delete file.
131 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
133 * ppc.h (PPC_OPCODE_E500): Define.
135 2010-05-26 Catherine Moore <clm@codesourcery.com>
137 * opcode/mips.h (INSN_MIPS16): Remove.
139 2010-04-21 Joseph Myers <joseph@codesourcery.com>
141 * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
143 2010-04-15 Nick Clifton <nickc@redhat.com>
145 * alpha.h: Update copyright notice to use GPLv3.
151 * convex.h: Likewise.
165 * m68hc11.h: Likewise.
171 * mn10200.h: Likewise.
172 * mn10300.h: Likewise.
173 * msp430.h: Likewise.
184 * score-datadep.h: Likewise.
185 * score-inst.h: Likewise.
187 * spu-insns.h: Likewise.
191 * tic54x.h: Likewise.
196 2010-03-25 Joseph Myers <joseph@codesourcery.com>
198 * tic6x-control-registers.h, tic6x-insn-formats.h,
199 tic6x-opcode-table.h, tic6x.h: New.
201 2010-02-25 Wu Zhangjin <wuzhangjin@gmail.com>
203 * mips.h: (LOONGSON2F_NOP_INSN): New macro.
205 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
207 * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
209 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
211 * ia64.h (ia64_find_opcode): Remove argument name.
212 (ia64_find_next_opcode): Likewise.
213 (ia64_dis_opcode): Likewise.
214 (ia64_free_opcode): Likewise.
215 (ia64_find_dependency): Likewise.
217 2009-11-22 Doug Evans <dje@sebabeach.org>
219 * cgen.h: Include bfd_stdint.h.
220 (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
222 2009-11-18 Paul Brook <paul@codesourcery.com>
224 * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
226 2009-11-17 Paul Brook <paul@codesourcery.com>
227 Daniel Jacobowitz <dan@codesourcery.com>
229 * arm.h (ARM_EXT_V6_DSP): Define.
230 (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
231 (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
233 2009-11-04 DJ Delorie <dj@redhat.com>
235 * rx.h (rx_decode_opcode) (mvtipl): Add.
236 (mvtcp, mvfcp, opecp): Remove.
238 2009-11-02 Paul Brook <paul@codesourcery.com>
240 * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
241 FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
242 (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
243 FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
244 FPU_ARCH_NEON_VFP_V4): Define.
246 2009-10-23 Doug Evans <dje@sebabeach.org>
248 * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
249 * cgen.h: Update. Improve multi-inclusion macro name.
251 2009-10-02 Peter Bergner <bergner@vnet.ibm.com>
253 * ppc.h (PPC_OPCODE_476): Define.
255 2009-10-01 Peter Bergner <bergner@vnet.ibm.com>
257 * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
259 2009-09-29 DJ Delorie <dj@redhat.com>
263 2009-09-22 Peter Bergner <bergner@vnet.ibm.com>
265 * ppc.h (ppc_cpu_t): Typedef to uint64_t.
267 2009-09-21 Ben Elliston <bje@au.ibm.com>
269 * ppc.h (PPC_OPCODE_PPCA2): New.
271 2009-09-05 Martin Thuresson <martin@mtme.org>
273 * ia64.h (struct ia64_operand): Renamed member class to op_class.
275 2009-08-29 Martin Thuresson <martin@mtme.org>
277 * tic30.h (template): Rename type template to
278 insn_template. Updated code to use new name.
279 * tic54x.h (template): Rename type template to
282 2009-08-20 Nick Hudson <nick.hudson@gmx.co.uk>
284 * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
286 2009-06-11 Anthony Green <green@moxielogic.com>
288 * moxie.h (MOXIE_F3_PCREL): Define.
289 (moxie_form3_opc_info): Grow.
291 2009-06-06 Anthony Green <green@moxielogic.com>
293 * moxie.h (MOXIE_F1_M): Define.
295 2009-04-15 Anthony Green <green@moxielogic.com>
299 2009-04-06 DJ Delorie <dj@redhat.com>
301 * h8300.h: Add relaxation attributes to MOVA opcodes.
303 2009-03-10 Alan Modra <amodra@bigpond.net.au>
305 * ppc.h (ppc_parse_cpu): Declare.
307 2009-03-02 Qinwei <qinwei@sunnorth.com.cn>
309 * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
310 and _IMM11 for mbitclr and mbitset.
311 * score-datadep.h: Update dependency information.
313 2009-02-26 Peter Bergner <bergner@vnet.ibm.com>
315 * ppc.h (PPC_OPCODE_POWER7): New.
317 2009-02-06 Doug Evans <dje@google.com>
319 * i386.h: Add comment regarding sse* insns and prefixes.
321 2009-02-03 Sandip Matte <sandip@rmicorp.com>
323 * mips.h (INSN_XLR): Define.
324 (INSN_CHIP_MASK): Update.
326 (OPCODE_IS_MEMBER): Update.
327 (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
329 2009-01-28 Doug Evans <dje@google.com>
331 * opcode/i386.h: Add multiple inclusion protection.
332 (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
333 (EDI_REG_NUM): New macros.
334 (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
335 (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
336 (REX_PREFIX_P): New macro.
338 2009-01-09 Peter Bergner <bergner@vnet.ibm.com>
340 * ppc.h (struct powerpc_opcode): New field "deprecated".
341 (PPC_OPCODE_NOPOWER4): Delete.
343 2008-11-28 Joshua Kinard <kumba@gentoo.org>
345 * mips.h: Define CPU_R14000, CPU_R16000.
346 (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
348 2008-11-18 Catherine Moore <clm@codesourcery.com>
350 * arm.h (FPU_NEON_FP16): New.
351 (FPU_ARCH_NEON_FP16): New.
353 2008-11-06 Chao-ying Fu <fu@mips.com>
355 * mips.h: Doucument '1' for 5-bit sync type.
357 2008-08-28 H.J. Lu <hongjiu.lu@intel.com>
359 * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update
362 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
364 * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
366 2008-07-30 Michael J. Eager <eager@eagercon.com>
368 * ppc.h (PPC_OPCODE_405): Define.
369 (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
371 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
373 * ppc.h (ppc_cpu_t): New typedef.
374 (struct powerpc_opcode <flags>): Use it.
375 (struct powerpc_operand <insert, extract>): Likewise.
376 (struct powerpc_macro <flags>): Likewise.
378 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
380 * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
381 Update comment before MIPS16 field descriptors to mention MIPS16.
382 (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
384 (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
385 New bit masks and shift counts for cins and exts.
387 * mips.h: Document new field descriptors +Q.
388 (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
390 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
392 * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
393 (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
395 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
397 * ppc.h: (PPC_OPCODE_E500MC): New.
399 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
401 * i386.h (MAX_OPERANDS): Set to 5.
402 (MAX_MNEM_SIZE): Changed to 20.
404 2008-03-28 Eric B. Weddington <eric.weddington@atmel.com>
406 * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
408 2008-03-09 Paul Brook <paul@codesourcery.com>
410 * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
412 2008-03-04 Paul Brook <paul@codesourcery.com>
414 * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
415 (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
416 (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
418 2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
419 Nick Clifton <nickc@redhat.com>
422 * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
423 with a 32-bit displacement but without the top bit of the 4th byte
426 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
428 * cr16.h (cr16_num_optab): Declared.
430 2008-02-14 Hakan Ardo <hakan@debian.org>
433 * avr.h (AVR_ISA_2xxe): Define.
435 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
437 * mips.h: Update copyright.
438 (INSN_CHIP_MASK): New macro.
439 (INSN_OCTEON): New macro.
440 (CPU_OCTEON): New macro.
441 (OPCODE_IS_MEMBER): Handle Octeon instructions.
443 2008-01-23 Eric B. Weddington <eric.weddington@atmel.com>
445 * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
447 2008-01-03 Eric B. Weddington <eric.weddington@atmel.com>
449 * avr.h (AVR_ISA_USB162): Add new opcode set.
450 (AVR_ISA_AVR3): Likewise.
452 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
454 * mips.h (INSN_LOONGSON_2E): New.
455 (INSN_LOONGSON_2F): New.
456 (CPU_LOONGSON_2E): New.
457 (CPU_LOONGSON_2F): New.
458 (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
460 2007-11-29 Mark Shinwell <shinwell@codesourcery.com>
462 * mips.h (INSN_ISA*): Redefine certain values as an
463 enumeration. Update comments.
464 (mips_isa_table): New.
465 (ISA_MIPS*): Redefine to match enumeration.
466 (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
469 2007-08-08 Ben Elliston <bje@au.ibm.com>
471 * ppc.h (PPC_OPCODE_PPCPS): New.
473 2007-07-03 Nathan Sidwell <nathan@codesourcery.com>
475 * m68k.h: Document j K & E.
477 2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
479 * cr16.h: New file for CR16 target.
481 2007-05-02 Alan Modra <amodra@bigpond.net.au>
483 * ppc.h (PPC_OPERAND_PLUS1): Update comment.
485 2007-04-23 Nathan Sidwell <nathan@codesourcery.com>
487 * m68k.h (mcfisa_c): New.
488 (mcfusp, mcf_mask): Adjust.
490 2007-04-20 Alan Modra <amodra@bigpond.net.au>
492 * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
493 (num_powerpc_operands): Declare.
494 (PPC_OPERAND_SIGNED et al): Redefine as hex.
495 (PPC_OPERAND_PLUS1): Define.
497 2007-03-21 H.J. Lu <hongjiu.lu@intel.com>
499 * i386.h (REX_MODE64): Renamed to ...
501 (REX_EXTX): Renamed to ...
503 (REX_EXTY): Renamed to ...
505 (REX_EXTZ): Renamed to ...
508 2007-03-15 H.J. Lu <hongjiu.lu@intel.com>
510 * i386.h: Add entries from config/tc-i386.h and move tables
511 to opcodes/i386-opc.h.
513 2007-03-13 H.J. Lu <hongjiu.lu@intel.com>
515 * i386.h (FloatDR): Removed.
516 (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
518 2007-03-01 Alan Modra <amodra@bigpond.net.au>
520 * spu-insns.h: Add soma double-float insns.
522 2007-02-20 Thiemo Seufer <ths@mips.com>
523 Chao-Ying Fu <fu@mips.com>
525 * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
526 (INSN_DSPR2): Add flag for DSP R2 instructions.
527 (M_BALIGN): New macro.
529 2007-02-14 Alan Modra <amodra@bigpond.net.au>
531 * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
532 and Seg3ShortFrom with Shortform.
534 2007-02-11 H.J. Lu <hongjiu.lu@intel.com>
537 * i386.h (i386_optab): Put the real "test" before the pseudo
540 2007-01-08 Kazu Hirata <kazu@codesourcery.com>
542 * m68k.h (m68010up): OR fido_a.
544 2006-12-25 Kazu Hirata <kazu@codesourcery.com>
546 * m68k.h (fido_a): New.
548 2006-12-24 Kazu Hirata <kazu@codesourcery.com>
550 * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
551 mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
554 2006-11-08 H.J. Lu <hongjiu.lu@intel.com>
556 * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
558 2006-10-31 Mei Ligang <ligang@sunnorth.com.cn>
560 * score-inst.h (enum score_insn_type): Add Insn_internal.
562 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
563 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
564 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
565 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
566 Alan Modra <amodra@bigpond.net.au>
568 * spu-insns.h: New file.
571 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
573 * ppc.h (PPC_OPCODE_CELL): Define.
575 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
577 * i386.h : Modify opcode to support for the change in POPCNT opcode
578 in amdfam10 architecture.
580 2006-09-28 H.J. Lu <hongjiu.lu@intel.com>
582 * i386.h: Replace CpuMNI with CpuSSSE3.
584 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
585 Joseph Myers <joseph@codesourcery.com>
586 Ian Lance Taylor <ian@wasabisystems.com>
587 Ben Elliston <bje@wasabisystems.com>
589 * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
591 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
593 * score-datadep.h: New file.
594 * score-inst.h: New file.
596 2006-07-14 H.J. Lu <hongjiu.lu@intel.com>
598 * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
599 movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
602 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
603 Michael Meissner <michael.meissner@amd.com>
605 * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
607 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
609 * i386.h (i386_optab): Add "nop" with memory reference.
611 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
613 * i386.h (i386_optab): Update comment for 64bit NOP.
615 2006-06-06 Ben Elliston <bje@au.ibm.com>
616 Anton Blanchard <anton@samba.org>
618 * ppc.h (PPC_OPCODE_POWER6): Define.
621 2006-06-05 Thiemo Seufer <ths@mips.com>
623 * mips.h: Improve description of MT flags.
625 2006-05-25 Richard Sandiford <richard@codesourcery.com>
627 * m68k.h (mcf_mask): Define.
629 2006-05-05 Thiemo Seufer <ths@mips.com>
630 David Ung <davidu@mips.com>
632 * mips.h (enum): Add macro M_CACHE_AB.
634 2006-05-04 Thiemo Seufer <ths@mips.com>
635 Nigel Stephens <nigel@mips.com>
636 David Ung <davidu@mips.com>
638 * mips.h: Add INSN_SMARTMIPS define.
640 2006-04-30 Thiemo Seufer <ths@mips.com>
641 David Ung <davidu@mips.com>
643 * mips.h: Defines udi bits and masks. Add description of
644 characters which may appear in the args field of udi
647 2006-04-26 Thiemo Seufer <ths@networkno.de>
649 * mips.h: Improve comments describing the bitfield instruction
652 2006-04-26 Julian Brown <julian@codesourcery.com>
654 * arm.h (FPU_VFP_EXT_V3): Define constant.
655 (FPU_NEON_EXT_V1): Likewise.
656 (FPU_VFP_HARD): Update.
657 (FPU_VFP_V3): Define macro.
658 (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
660 2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de>
662 * avr.h (AVR_ISA_PWMx): New.
664 2006-03-28 Nathan Sidwell <nathan@codesourcery.com>
666 * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
667 cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
668 cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
669 cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
670 cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
672 2006-03-10 Paul Brook <paul@codesourcery.com>
674 * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
676 2006-03-04 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
678 * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
679 first. Correct mask of bb "B" opcode.
681 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
683 * i386.h (i386_optab): Support Intel Merom New Instructions.
685 2006-02-24 Paul Brook <paul@codesourcery.com>
687 * arm.h: Add V7 feature bits.
689 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
691 * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
693 2006-01-31 Paul Brook <paul@codesourcery.com>
694 Richard Earnshaw <rearnsha@arm.com>
696 * arm.h: Use ARM_CPU_FEATURE.
697 (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
698 (arm_feature_set): Change to a structure.
699 (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
700 ARM_FEATURE): New macros.
702 2005-12-07 Hans-Peter Nilsson <hp@axis.com>
704 * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
705 (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
706 (ADD_PC_INCR_OPCODE): Don't define.
708 2005-12-06 H.J. Lu <hongjiu.lu@intel.com>
711 * i386.h (i386_optab): Add 64bit support for monitor and mwait.
713 2005-11-14 David Ung <davidu@mips.com>
715 * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
716 instructions. Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
717 save/restore encoding of the args field.
719 2005-10-28 Dave Brolley <brolley@redhat.com>
721 Contribute the following changes:
722 2005-02-16 Dave Brolley <brolley@redhat.com>
724 * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
725 cgen_isa_mask_* to cgen_bitset_*.
728 2003-10-21 Richard Sandiford <rsandifo@redhat.com>
730 * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
731 (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
732 (CGEN_CPU_TABLE): Make isas a ponter.
734 2003-09-29 Dave Brolley <brolley@redhat.com>
736 * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
737 (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
738 (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
740 2002-12-13 Dave Brolley <brolley@redhat.com>
742 * cgen.h (symcat.h): #include it.
743 (cgen-bitset.h): #include it.
744 (CGEN_ATTR_VALUE_TYPE): Now a union.
745 (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
746 (CGEN_ATTR_ENTRY): 'value' now unsigned.
747 (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
748 * cgen-bitset.h: New file.
750 2005-09-30 Catherine Moore <clm@cm00re.com>
754 2005-10-24 Jan Beulich <jbeulich@novell.com>
756 * ia64.h (enum ia64_opnd): Move memory operand out of set of
759 2005-10-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
761 * hppa.h (pa_opcodes): Add two fcmp opcodes. Reorder ftest opcodes.
762 Add FLAG_STRICT to pa10 ftest opcode.
764 2005-10-12 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
766 * hppa.h (pa_opcodes): Remove lha entries.
768 2005-10-08 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
770 * hppa.h (FLAG_STRICT): Revise comment.
771 (pa_opcode): Revise ordering rules. Add/move strict pa10 variants
772 before corresponding pa11 opcodes. Add strict pa10 register-immediate
775 2005-09-30 Catherine Moore <clm@cm00re.com>
779 2005-09-24 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
781 * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
783 2005-09-06 Chao-ying Fu <fu@mips.com>
785 * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
786 OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
788 Document !, $, *, &, g, +t, +T operand formats for MT instructions.
789 (INSN_ASE_MASK): Update to include INSN_MT.
790 (INSN_MT): New define for MT ASE.
792 2005-08-25 Chao-ying Fu <fu@mips.com>
794 * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
795 OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
796 OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
797 OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
798 OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
799 Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
801 (INSN_DSP): New define for DSP ASE.
803 2005-08-18 Alan Modra <amodra@bigpond.net.au>
807 2005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
809 * ppc.h (PPC_OPCODE_E300): Define.
811 2005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
813 * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
815 2005-07-28 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
818 * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
821 2005-07-27 Jan Beulich <jbeulich@novell.com>
823 * i386.h (i386_optab): Add comment to movd. Use LongMem for all
824 movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
825 Add movq-s as 64-bit variants of movd-s.
827 2005-07-18 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
829 * hppa.h: Fix punctuation in comment.
831 * hppa.h (pa_opcode): Add rules for opcode ordering. Check first for
832 implicit space-register addressing. Set space-register bits on opcodes
833 using implicit space-register addressing. Add various missing pa20
834 long-immediate opcodes. Remove various opcodes using implicit 3-bit
835 space-register addressing. Use "fE" instead of "fe" in various
838 2005-07-18 Jan Beulich <jbeulich@novell.com>
840 * i386.h (i386_optab): Operands of aam and aad are unsigned.
842 2007-07-15 H.J. Lu <hongjiu.lu@intel.com>
844 * i386.h (i386_optab): Support Intel VMX Instructions.
846 2005-07-10 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
848 * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
850 2005-07-05 Jan Beulich <jbeulich@novell.com>
852 * i386.h (i386_optab): Add new insns.
854 2005-07-01 Nick Clifton <nickc@redhat.com>
856 * sparc.h: Add typedefs to structure declarations.
858 2005-06-20 H.J. Lu <hongjiu.lu@intel.com>
861 * i386.h (i386_optab): Update comments for 64bit addressing on
862 mov. Allow 64bit addressing for mov and movq.
864 2005-06-11 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
866 * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
867 respectively, in various floating-point load and store patterns.
869 2005-05-23 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
871 * hppa.h (FLAG_STRICT): Correct comment.
872 (pa_opcodes): Update load and store entries to allow both PA 1.X and
873 PA 2.0 mneumonics when equivalent. Entries with cache control
874 completers now require PA 1.1. Adjust whitespace.
876 2005-05-19 Anton Blanchard <anton@samba.org>
878 * ppc.h (PPC_OPCODE_POWER5): Define.
880 2005-05-10 Nick Clifton <nickc@redhat.com>
882 * Update the address and phone number of the FSF organization in
883 the GPL notices in the following files:
884 a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
885 crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
886 i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
887 mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
888 pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
889 tic54x.h, tic80.h, v850.h, vax.h
891 2005-05-09 Jan Beulich <jbeulich@novell.com>
893 * i386.h (i386_optab): Add ht and hnt.
895 2005-04-18 Mark Kettenis <kettenis@gnu.org>
897 * i386.h: Insert hyphens into selected VIA PadLock extensions.
898 Add xcrypt-ctr. Provide aliases without hyphens.
900 2005-04-13 H.J. Lu <hongjiu.lu@intel.com>
902 Moved from ../ChangeLog
904 2005-04-12 Paul Brook <paul@codesourcery.com>
905 * m88k.h: Rename psr macros to avoid conflicts.
907 2005-03-12 Zack Weinberg <zack@codesourcery.com>
908 * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
909 Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
912 2004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
913 * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
914 Remove redundant instruction types.
915 (struct argument): X_op - new field.
916 (struct cst4_entry): Remove.
917 (no_op_insn): Declare.
919 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
920 * crx.h (enum argtype): Rename types, remove unused types.
922 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
923 * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
924 (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
925 (enum operand_type): Rearrange operands, edit comments.
926 replace us<N> with ui<N> for unsigned immediate.
927 replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
928 displacements (respectively).
929 replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
930 (instruction type): Add NO_TYPE_INS.
931 (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
932 (operand_entry): New field - 'flags'.
933 (operand flags): New.
935 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
936 * crx.h (operand_type): Remove redundant types i3, i4,
938 Add new unsigned immediate types us3, us4, us5, us16.
940 2005-04-12 Mark Kettenis <kettenis@gnu.org>
942 * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
943 adjust them accordingly.
945 2005-04-01 Jan Beulich <jbeulich@novell.com>
947 * i386.h (i386_optab): Add rdtscp.
949 2005-03-29 H.J. Lu <hongjiu.lu@intel.com>
951 * i386.h (i386_optab): Don't allow the `l' suffix for moving
952 between memory and segment register. Allow movq for moving between
953 general-purpose register and segment register.
955 2005-02-09 Jan Beulich <jbeulich@novell.com>
958 * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
959 FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
962 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
964 * m68k.h (m68008, m68ec030, m68882): Remove.
966 (cpu_m68k, cpu_cf): New.
967 (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
968 mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
970 2005-01-25 Alexandre Oliva <aoliva@redhat.com>
972 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
973 * cgen.h (enum cgen_parse_operand_type): Add
974 CGEN_PARSE_OPERAND_SYMBOLIC.
976 2005-01-21 Fred Fish <fnf@specifixinc.com>
978 * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
979 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
980 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
982 2005-01-19 Fred Fish <fnf@specifixinc.com>
984 * mips.h (struct mips_opcode): Add new pinfo2 member.
985 (INSN_ALIAS): New define for opcode table entries that are
986 specific instances of another entry, such as 'move' for an 'or'
988 (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
989 (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
991 2004-12-09 Ian Lance Taylor <ian@wasabisystems.com>
993 * mips.h (CPU_RM9000): Define.
994 (OPCODE_IS_MEMBER): Handle CPU_RM9000.
996 2004-11-25 Jan Beulich <jbeulich@novell.com>
998 * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
999 to/from test registers are illegal in 64-bit mode. Add missing
1000 NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1001 (previously one had to explicitly encode a rex64 prefix). Re-enable
1002 lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1003 support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1005 2004-11-23 Jan Beulich <jbeulich@novell.com>
1007 * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1008 available only with SSE2. Change the MMX additions introduced by SSE
1009 and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1010 instructions by their now designated identifier (since combining i686
1011 and 3DNow! does not really imply 3DNow!A).
1013 2004-11-19 Alan Modra <amodra@bigpond.net.au>
1015 * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1016 struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1018 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
1019 Vineet Sharma <vineets@noida.hcltech.com>
1021 * maxq.h: New file: Disassembly information for the maxq port.
1023 2004-11-05 H.J. Lu <hongjiu.lu@intel.com>
1025 * i386.h (i386_optab): Put back "movzb".
1027 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
1029 * cris.h (enum cris_insn_version_usage): Tweak formatting and
1030 comments. Remove member cris_ver_sim. Add members
1031 cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1032 cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1033 (struct cris_support_reg, struct cris_cond15): New types.
1034 (cris_conds15): Declare.
1035 (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1036 (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1037 (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1038 (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1039 (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1040 SIZE_FIELD_UNSIGNED.
1042 2004-11-04 Jan Beulich <jbeulich@novell.com>
1044 * i386.h (sldx_Suf): Remove.
1045 (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1046 (q_FP): Define, implying no REX64.
1047 (x_FP, sl_FP): Imply FloatMF.
1048 (i386_optab): Split reg and mem forms of moving from segment registers
1049 so that the memory forms can ignore the 16-/32-bit operand size
1050 distinction. Adjust a few others for Intel mode. Remove *FP uses from
1051 all non-floating-point instructions. Unite 32- and 64-bit forms of
1052 movsx, movzx, and movd. Adjust floating point operations for the above
1053 changes to the *FP macros. Add DefaultSize to floating point control
1054 insns operating on larger memory ranges. Remove left over comments
1055 hinting at certain insns being Intel-syntax ones where the ones
1056 actually meant are already gone.
1058 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1060 * crx.h: Add COPS_REG_INS - Coprocessor Special register
1063 2004-09-30 Paul Brook <paul@codesourcery.com>
1065 * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1066 (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1068 2004-09-11 Theodore A. Roth <troth@openavr.org>
1070 * avr.h: Add support for
1071 atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1073 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1075 * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1077 2004-08-24 Dmitry Diky <diwil@spec.ru>
1079 * msp430.h (msp430_opc): Add new instructions.
1080 (msp430_rcodes): Declare new instructions.
1081 (msp430_hcodes): Likewise..
1083 2004-08-13 Nick Clifton <nickc@redhat.com>
1086 * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1089 2004-08-30 Michal Ludvig <mludvig@suse.cz>
1091 * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1093 2004-07-22 H.J. Lu <hongjiu.lu@intel.com>
1095 * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1097 2004-07-21 Jan Beulich <jbeulich@novell.com>
1099 * i386.h: Adjust instruction descriptions to better match the
1102 2004-07-16 Richard Earnshaw <rearnsha@arm.com>
1104 * arm.h: Remove all old content. Replace with architecture defines
1105 from gas/config/tc-arm.c.
1107 2004-07-09 Andreas Schwab <schwab@suse.de>
1109 * m68k.h: Fix comment.
1111 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1115 2004-06-24 Alan Modra <amodra@bigpond.net.au>
1117 * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1119 2004-05-24 Peter Barada <peter@the-baradas.com>
1121 * m68k.h: Add 'size' to m68k_opcode.
1123 2004-05-05 Peter Barada <peter@the-baradas.com>
1125 * m68k.h: Switch from ColdFire chip name to core variant.
1127 2004-04-22 Peter Barada <peter@the-baradas.com>
1129 * m68k.h: Add mcfmac/mcfemac definitions. Update operand
1130 descriptions for new EMAC cases.
1131 Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1132 handle Motorola MAC syntax.
1133 Allow disassembly of ColdFire V4e object files.
1135 2004-03-16 Alan Modra <amodra@bigpond.net.au>
1137 * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines.
1139 2004-03-12 Jakub Jelinek <jakub@redhat.com>
1141 * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1143 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1145 * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1147 2004-03-12 Michal Ludvig <mludvig@suse.cz>
1149 * i386.h (i386_optab): Added xstore/xcrypt insns.
1151 2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
1153 * h8300.h (32bit ldc/stc): Add relaxing support.
1155 2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
1157 * h8300.h (BITOP): Pass MEMRELAX flag.
1159 2004-01-09 Anil Paranjpe <anilp1@KPITCummins.com>
1161 * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1164 For older changes see ChangeLog-9103
1170 version-control: never