include/opcode/ChangeLog

   1 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
   2
   3         * mips.h (CPU_RM9000): Define.
   4         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
   5
   6 2004-11-25 Jan Beulich  <jbeulich@novell.com>
   7
   8         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
   9         to/from test registers are illegal in 64-bit mode. Add missing
  10         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
  11         (previously one had to explicitly encode a rex64 prefix). Re-enable
  12         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
  13         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
  14
  15 2004-11-23 Jan Beulich  <jbeulich@novell.com>
  16
  17         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
  18         available only with SSE2. Change the MMX additions introduced by SSE
  19         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
  20         instructions by their now designated identifier (since combining i686
  21         and 3DNow! does not really imply 3DNow!A).
  22
  23 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
  24
  25         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
  26         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
  27
  28 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
  29             Vineet Sharma      <vineets@noida.hcltech.com>
  30
  31         * maxq.h: New file: Disassembly information for the maxq port.
  32
  33 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
  34
  35         * i386.h (i386_optab): Put back "movzb".
  36
  37 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
  38
  39         * cris.h (enum cris_insn_version_usage): Tweak formatting and
  40         comments.  Remove member cris_ver_sim.  Add members
  41         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
  42         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
  43         (struct cris_support_reg, struct cris_cond15): New types.
  44         (cris_conds15): Declare.
  45         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
  46         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
  47         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
  48         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
  49         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
  50         SIZE_FIELD_UNSIGNED.
  51
  52 2004-11-04 Jan Beulich  <jbeulich@novell.com>
  53
  54         * i386.h (sldx_Suf): Remove.
  55         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
  56         (q_FP): Define, implying no REX64.
  57         (x_FP, sl_FP): Imply FloatMF.
  58         (i386_optab): Split reg and mem forms of moving from segment registers
  59         so that the memory forms can ignore the 16-/32-bit operand size
  60         distinction. Adjust a few others for Intel mode. Remove *FP uses from
  61         all non-floating-point instructions. Unite 32- and 64-bit forms of
  62         movsx, movzx, and movd. Adjust floating point operations for the above
  63         changes to the *FP macros. Add DefaultSize to floating point control
  64         insns operating on larger memory ranges. Remove left over comments
  65         hinting at certain insns being Intel-syntax ones where the ones
  66         actually meant are already gone.
  67
  68 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
  69
  70         * crx.h: Add COPS_REG_INS - Coprocessor Special register
  71         instruction type.
  72
  73 2004-09-30  Paul Brook  <paul@codesourcery.com>
  74
  75         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
  76         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
  77
  78 2004-09-11  Theodore A. Roth  <troth@openavr.org>
  79
  80         * avr.h: Add support for
  81         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
  82
  83 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
  84
  85         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
  86
  87 2004-08-24  Dmitry Diky  <diwil@spec.ru>
  88
  89         * msp430.h (msp430_opc): Add new instructions.
  90         (msp430_rcodes): Declare new instructions.
  91         (msp430_hcodes): Likewise..
  92
  93 2004-08-13  Nick Clifton  <nickc@redhat.com>
  94
  95         PR/301
  96         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
  97         processors.
  98
  99 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 100
 101         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 102
 103 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 104
 105         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 106
 107 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 108
 109         * i386.h: Adjust instruction descriptions to better match the
 110         specification.
 111
 112 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 113
 114         * arm.h: Remove all old content.  Replace with architecture defines
 115         from gas/config/tc-arm.c.
 116
 117 2004-07-09  Andreas Schwab  <schwab@suse.de>
 118
 119         * m68k.h: Fix comment.
 120
 121 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 122
 123         * crx.h: New file.
 124
 125 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 126
 127         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 128
 129 2004-05-24  Peter Barada  <peter@the-baradas.com>
 130
 131         * m68k.h: Add 'size' to m68k_opcode.
 132
 133 2004-05-05  Peter Barada  <peter@the-baradas.com>
 134
 135         * m68k.h: Switch from ColdFire chip name to core variant.
 136
 137 2004-04-22  Peter Barada  <peter@the-baradas.com>
 138
 139         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 140         descriptions for new EMAC cases.
 141         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 142         handle Motorola MAC syntax.
 143         Allow disassembly of ColdFire V4e object files.
 144
 145 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 146
 147         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 148
 149 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 150
 151         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 152
 153 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 154
 155         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 156
 157 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 158
 159         * i386.h (i386_optab): Added xstore/xcrypt insns.
 160
 161 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 162
 163         * h8300.h (32bit ldc/stc): Add relaxing support.
 164
 165 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 166
 167         * h8300.h (BITOP): Pass MEMRELAX flag.
 168
 169 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 170
 171         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 172         except for the H8S.
 173
 174 For older changes see ChangeLog-9103
 175 \f
 176 Local Variables:
 177 mode: change-log
 178 left-margin: 8
 179 fill-column: 74
 180 version-control: never
 181 End: