include/opcode/ChangeLog

   1 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
   2
   3         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
   4
   5 2009-09-21  Ben Elliston  <bje@au.ibm.com>
   6
   7         * ppc.h (PPC_OPCODE_PPCA2): New.
   8
   9 2009-09-05  Martin Thuresson  <martin@mtme.org>
  10
  11         * ia64.h (struct ia64_operand): Renamed member class to op_class.
  12
  13 2009-08-29  Martin Thuresson  <martin@mtme.org>
  14
  15         * tic30.h (template): Rename type template to
  16         insn_template. Updated code to use new name.
  17         * tic54x.h (template): Rename type template to
  18         insn_template.
  19
  20 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
  21
  22         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
  23
  24 2009-06-11  Anthony Green  <green@moxielogic.com>
  25
  26         * moxie.h (MOXIE_F3_PCREL): Define.
  27         (moxie_form3_opc_info): Grow.
  28
  29 2009-06-06  Anthony Green  <green@moxielogic.com>
  30
  31         * moxie.h (MOXIE_F1_M): Define.
  32
  33 2009-04-15  Anthony Green  <green@moxielogic.com>
  34
  35         * moxie.h: Created.
  36
  37 2009-04-06  DJ Delorie  <dj@redhat.com>
  38
  39         * h8300.h: Add relaxation attributes to MOVA opcodes.
  40
  41 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
  42
  43         * ppc.h (ppc_parse_cpu): Declare.
  44
  45 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
  46
  47         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
  48         and _IMM11 for mbitclr and mbitset.
  49         * score-datadep.h: Update dependency information.
  50
  51 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
  52
  53         * ppc.h (PPC_OPCODE_POWER7): New.
  54
  55 2009-02-06  Doug Evans  <dje@google.com>
  56
  57         * i386.h: Add comment regarding sse* insns and prefixes.
  58
  59 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
  60
  61         * mips.h (INSN_XLR): Define.
  62         (INSN_CHIP_MASK): Update.
  63         (CPU_XLR): Define.
  64         (OPCODE_IS_MEMBER): Update.
  65         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
  66
  67 2009-01-28  Doug Evans  <dje@google.com>
  68
  69         * opcode/i386.h: Add multiple inclusion protection.
  70         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
  71         (EDI_REG_NUM): New macros.
  72         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
  73         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
  74         (REX_PREFIX_P): New macro.
  75
  76 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
  77
  78         * ppc.h (struct powerpc_opcode): New field "deprecated".
  79         (PPC_OPCODE_NOPOWER4): Delete.
  80
  81 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
  82
  83         * mips.h: Define CPU_R14000, CPU_R16000.
  84         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
  85
  86 2008-11-18  Catherine Moore  <clm@codesourcery.com>
  87
  88         * arm.h (FPU_NEON_FP16): New.
  89         (FPU_ARCH_NEON_FP16): New.
  90
  91 2008-11-06  Chao-ying Fu  <fu@mips.com>
  92
  93         * mips.h: Doucument '1' for 5-bit sync type.
  94
  95 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
  96
  97         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
  98         IA64_RS_CR.
  99
 100 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 101
 102         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 103
 104 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 105
 106         * ppc.h (PPC_OPCODE_405): Define.
 107         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 108
 109 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 110
 111         * ppc.h (ppc_cpu_t): New typedef.
 112         (struct powerpc_opcode <flags>): Use it.
 113         (struct powerpc_operand <insert, extract>): Likewise.
 114         (struct powerpc_macro <flags>): Likewise.
 115
 116 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 117
 118         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 119         Update comment before MIPS16 field descriptors to mention MIPS16.
 120         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 121         BBIT.
 122         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 123         New bit masks and shift counts for cins and exts.
 124
 125         * mips.h: Document new field descriptors +Q.
 126         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 127
 128 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 129
 130         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 131         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 132
 133 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 134
 135         * ppc.h: (PPC_OPCODE_E500MC): New.
 136
 137 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 138
 139         * i386.h (MAX_OPERANDS): Set to 5.
 140         (MAX_MNEM_SIZE): Changed to 20.
 141
 142 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 143
 144         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 145
 146 2008-03-09  Paul Brook  <paul@codesourcery.com>
 147
 148         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 149
 150 2008-03-04  Paul Brook  <paul@codesourcery.com>
 151
 152         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 153         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 154         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 155
 156 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 157             Nick Clifton  <nickc@redhat.com>
 158
 159         PR 3134
 160         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 161         with a 32-bit displacement but without the top bit of the 4th byte
 162         set.
 163
 164 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 165
 166         * cr16.h (cr16_num_optab): Declared.
 167
 168 2008-02-14  Hakan Ardo  <hakan@debian.org>
 169
 170         PR gas/2626
 171         * avr.h (AVR_ISA_2xxe): Define.
 172
 173 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 174
 175         * mips.h: Update copyright.
 176         (INSN_CHIP_MASK): New macro.
 177         (INSN_OCTEON): New macro.
 178         (CPU_OCTEON): New macro.
 179         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 180
 181 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 182
 183         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 184
 185 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 186
 187         * avr.h (AVR_ISA_USB162): Add new opcode set.
 188         (AVR_ISA_AVR3): Likewise.
 189
 190 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 191
 192         * mips.h (INSN_LOONGSON_2E): New.
 193         (INSN_LOONGSON_2F): New.
 194         (CPU_LOONGSON_2E): New.
 195         (CPU_LOONGSON_2F): New.
 196         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 197
 198 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 199
 200         * mips.h (INSN_ISA*): Redefine certain values as an
 201         enumeration.  Update comments.
 202         (mips_isa_table): New.
 203         (ISA_MIPS*): Redefine to match enumeration.
 204         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 205         values.
 206
 207 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 208
 209         * ppc.h (PPC_OPCODE_PPCPS): New.
 210
 211 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 212
 213         * m68k.h: Document j K & E.
 214
 215 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 216
 217         * cr16.h: New file for CR16 target.
 218
 219 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 220
 221         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 222
 223 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 224
 225         * m68k.h (mcfisa_c): New.
 226         (mcfusp, mcf_mask): Adjust.
 227
 228 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 229
 230         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 231         (num_powerpc_operands): Declare.
 232         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 233         (PPC_OPERAND_PLUS1): Define.
 234
 235 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 236
 237         * i386.h (REX_MODE64): Renamed to ...
 238         (REX_W): This.
 239         (REX_EXTX): Renamed to ...
 240         (REX_R): This.
 241         (REX_EXTY): Renamed to ...
 242         (REX_X): This.
 243         (REX_EXTZ): Renamed to ...
 244         (REX_B): This.
 245
 246 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 247
 248         * i386.h: Add entries from config/tc-i386.h and move tables
 249         to opcodes/i386-opc.h.
 250
 251 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 252
 253         * i386.h (FloatDR): Removed.
 254         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 255
 256 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 257
 258         * spu-insns.h: Add soma double-float insns.
 259
 260 2007-02-20  Thiemo Seufer  <ths@mips.com>
 261             Chao-Ying Fu  <fu@mips.com>
 262
 263         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 264         (INSN_DSPR2): Add flag for DSP R2 instructions.
 265         (M_BALIGN): New macro.
 266
 267 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 268
 269         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 270         and Seg3ShortFrom with Shortform.
 271
 272 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 273
 274         PR gas/4027
 275         * i386.h (i386_optab): Put the real "test" before the pseudo
 276         one.
 277
 278 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 279
 280         * m68k.h (m68010up): OR fido_a.
 281
 282 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 283
 284         * m68k.h (fido_a): New.
 285
 286 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 287
 288         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 289         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 290         values.
 291
 292 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 293
 294         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 295
 296 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 297
 298         * score-inst.h (enum score_insn_type): Add Insn_internal.
 299
 300 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 301             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 302             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 303             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 304             Alan Modra  <amodra@bigpond.net.au>
 305
 306         * spu-insns.h: New file.
 307         * spu.h: New file.
 308
 309 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 310
 311         * ppc.h (PPC_OPCODE_CELL): Define.
 312
 313 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 314
 315         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 316         in amdfam10 architecture.
 317
 318 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 319
 320         * i386.h: Replace CpuMNI with CpuSSSE3.
 321
 322 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 323             Joseph Myers  <joseph@codesourcery.com>
 324             Ian Lance Taylor  <ian@wasabisystems.com>
 325             Ben Elliston  <bje@wasabisystems.com>
 326
 327         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 328
 329 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 330
 331         * score-datadep.h: New file.
 332         * score-inst.h: New file.
 333
 334 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 335
 336         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 337         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 338         movdq2q and movq2dq.
 339
 340 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 341            Michael Meissner             <michael.meissner@amd.com>
 342
 343         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 344
 345 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 346
 347         * i386.h (i386_optab): Add "nop" with memory reference.
 348
 349 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 350
 351         * i386.h (i386_optab): Update comment for 64bit NOP.
 352
 353 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 354             Anton Blanchard  <anton@samba.org>
 355
 356         * ppc.h (PPC_OPCODE_POWER6): Define.
 357         Adjust whitespace.
 358
 359 2006-06-05  Thiemo Seufer  <ths@mips.com>
 360
 361         * mips.h: Improve description of MT flags.
 362
 363 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 364
 365         * m68k.h (mcf_mask): Define.
 366
 367 2006-05-05  Thiemo Seufer  <ths@mips.com>
 368             David Ung  <davidu@mips.com>
 369
 370         * mips.h (enum): Add macro M_CACHE_AB.
 371
 372 2006-05-04  Thiemo Seufer  <ths@mips.com>
 373             Nigel Stephens  <nigel@mips.com>
 374             David Ung  <davidu@mips.com>
 375
 376         * mips.h: Add INSN_SMARTMIPS define.
 377
 378 2006-04-30  Thiemo Seufer  <ths@mips.com>
 379             David Ung  <davidu@mips.com>
 380
 381         * mips.h: Defines udi bits and masks.  Add description of
 382         characters which may appear in the args field of udi
 383         instructions.
 384
 385 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 386
 387         * mips.h: Improve comments describing the bitfield instruction
 388         fields.
 389
 390 2006-04-26  Julian Brown  <julian@codesourcery.com>
 391
 392         * arm.h (FPU_VFP_EXT_V3): Define constant.
 393         (FPU_NEON_EXT_V1): Likewise.
 394         (FPU_VFP_HARD): Update.
 395         (FPU_VFP_V3): Define macro.
 396         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 397
 398 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 399
 400         * avr.h (AVR_ISA_PWMx): New.
 401
 402 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 403
 404         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 405         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 406         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 407         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 408         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 409
 410 2006-03-10  Paul Brook  <paul@codesourcery.com>
 411
 412         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 413
 414 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 415
 416         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 417         first.  Correct mask of bb "B" opcode.
 418
 419 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 420
 421         * i386.h (i386_optab): Support Intel Merom New Instructions.
 422
 423 2006-02-24  Paul Brook  <paul@codesourcery.com>
 424
 425         * arm.h: Add V7 feature bits.
 426
 427 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 428
 429         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 430
 431 2006-01-31  Paul Brook  <paul@codesourcery.com>
 432         Richard Earnshaw <rearnsha@arm.com>
 433
 434         * arm.h: Use ARM_CPU_FEATURE.
 435         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 436         (arm_feature_set): Change to a structure.
 437         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 438         ARM_FEATURE): New macros.
 439
 440 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 441
 442         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 443         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 444         (ADD_PC_INCR_OPCODE): Don't define.
 445
 446 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 447
 448         PR gas/1874
 449         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 450
 451 2005-11-14  David Ung  <davidu@mips.com>
 452
 453         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 454         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 455         save/restore encoding of the args field.
 456
 457 2005-10-28  Dave Brolley  <brolley@redhat.com>
 458
 459         Contribute the following changes:
 460         2005-02-16  Dave Brolley  <brolley@redhat.com>
 461
 462         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 463         cgen_isa_mask_* to cgen_bitset_*.
 464         * cgen.h: Likewise.
 465
 466         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 467
 468         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 469         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 470         (CGEN_CPU_TABLE): Make isas a ponter.
 471
 472         2003-09-29  Dave Brolley  <brolley@redhat.com>
 473
 474         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 475         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 476         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 477
 478         2002-12-13  Dave Brolley  <brolley@redhat.com>
 479
 480         * cgen.h (symcat.h): #include it.
 481         (cgen-bitset.h): #include it.
 482         (CGEN_ATTR_VALUE_TYPE): Now a union.
 483         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 484         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 485         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 486         * cgen-bitset.h: New file.
 487
 488 2005-09-30  Catherine Moore  <clm@cm00re.com>
 489
 490         * bfin.h: New file.
 491
 492 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 493
 494         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 495         indirect operands.
 496
 497 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 498
 499         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 500         Add FLAG_STRICT to pa10 ftest opcode.
 501
 502 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 503
 504         * hppa.h (pa_opcodes): Remove lha entries.
 505
 506 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 507
 508         * hppa.h (FLAG_STRICT): Revise comment.
 509         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 510         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 511         entries for "fdc".
 512
 513 2005-09-30  Catherine Moore  <clm@cm00re.com>
 514
 515         * bfin.h: New file.
 516
 517 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 518
 519         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 520
 521 2005-09-06  Chao-ying Fu  <fu@mips.com>
 522
 523         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 524         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 525         define.
 526         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 527         (INSN_ASE_MASK): Update to include INSN_MT.
 528         (INSN_MT): New define for MT ASE.
 529
 530 2005-08-25  Chao-ying Fu  <fu@mips.com>
 531
 532         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 533         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 534         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 535         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 536         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 537         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 538         instructions.
 539         (INSN_DSP): New define for DSP ASE.
 540
 541 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * a29k.h: Delete.
 544
 545 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 546
 547         * ppc.h (PPC_OPCODE_E300): Define.
 548
 549 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 550
 551         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 552
 553 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 554
 555         PR gas/336
 556         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 557         and pitlb.
 558
 559 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 560
 561         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 562         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 563         Add movq-s as 64-bit variants of movd-s.
 564
 565 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 566
 567         * hppa.h: Fix punctuation in comment.
 568
 569         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 570         implicit space-register addressing.  Set space-register bits on opcodes
 571         using implicit space-register addressing.  Add various missing pa20
 572         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 573         space-register addressing.  Use "fE" instead of "fe" in various
 574         fstw opcodes.
 575
 576 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 577
 578         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 579
 580 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 581
 582         * i386.h (i386_optab): Support Intel VMX Instructions.
 583
 584 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 585
 586         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 587
 588 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 589
 590         * i386.h (i386_optab): Add new insns.
 591
 592 2005-07-01  Nick Clifton  <nickc@redhat.com>
 593
 594         * sparc.h: Add typedefs to structure declarations.
 595
 596 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 597
 598         PR 1013
 599         * i386.h (i386_optab): Update comments for 64bit addressing on
 600         mov. Allow 64bit addressing for mov and movq.
 601
 602 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 603
 604         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 605         respectively, in various floating-point load and store patterns.
 606
 607 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 608
 609         * hppa.h (FLAG_STRICT): Correct comment.
 610         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 611         PA 2.0 mneumonics when equivalent.  Entries with cache control
 612         completers now require PA 1.1.  Adjust whitespace.
 613
 614 2005-05-19  Anton Blanchard  <anton@samba.org>
 615
 616         * ppc.h (PPC_OPCODE_POWER5): Define.
 617
 618 2005-05-10  Nick Clifton  <nickc@redhat.com>
 619
 620         * Update the address and phone number of the FSF organization in
 621         the GPL notices in the following files:
 622         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 623         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 624         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 625         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 626         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 627         tic54x.h, tic80.h, v850.h, vax.h
 628
 629 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 630
 631         * i386.h (i386_optab): Add ht and hnt.
 632
 633 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 634
 635         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 636         Add xcrypt-ctr.  Provide aliases without hyphens.
 637
 638 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 639
 640         Moved from ../ChangeLog
 641
 642         2005-04-12  Paul Brook  <paul@codesourcery.com>
 643         * m88k.h: Rename psr macros to avoid conflicts.
 644
 645         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 646         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 647         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 648         and ARM_ARCH_V6ZKT2.
 649
 650         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 651         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 652         Remove redundant instruction types.
 653         (struct argument): X_op - new field.
 654         (struct cst4_entry): Remove.
 655         (no_op_insn): Declare.
 656
 657         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 658         * crx.h (enum argtype): Rename types, remove unused types.
 659
 660         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 661         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 662         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 663         (enum operand_type): Rearrange operands, edit comments.
 664         replace us<N> with ui<N> for unsigned immediate.
 665         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 666         displacements (respectively).
 667         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 668         (instruction type): Add NO_TYPE_INS.
 669         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 670         (operand_entry): New field - 'flags'.
 671         (operand flags): New.
 672
 673         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 674         * crx.h (operand_type): Remove redundant types i3, i4,
 675         i5, i8, i12.
 676         Add new unsigned immediate types us3, us4, us5, us16.
 677
 678 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 679
 680         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 681         adjust them accordingly.
 682
 683 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 684
 685         * i386.h (i386_optab): Add rdtscp.
 686
 687 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 688
 689         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 690         between memory and segment register. Allow movq for moving between
 691         general-purpose register and segment register.
 692
 693 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 694
 695         PR gas/707
 696         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 697         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 698         fnstsw.
 699
 700 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 701
 702         * m68k.h (m68008, m68ec030, m68882): Remove.
 703         (m68k_mask): New.
 704         (cpu_m68k, cpu_cf): New.
 705         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 706         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 707
 708 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 709
 710         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 711         * cgen.h (enum cgen_parse_operand_type): Add
 712         CGEN_PARSE_OPERAND_SYMBOLIC.
 713
 714 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 715
 716         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 717         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 718         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 719
 720 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 721
 722         * mips.h (struct mips_opcode): Add new pinfo2 member.
 723         (INSN_ALIAS): New define for opcode table entries that are
 724         specific instances of another entry, such as 'move' for an 'or'
 725         with a zero operand.
 726         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 727         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 728
 729 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 730
 731         * mips.h (CPU_RM9000): Define.
 732         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 733
 734 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 735
 736         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 737         to/from test registers are illegal in 64-bit mode. Add missing
 738         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 739         (previously one had to explicitly encode a rex64 prefix). Re-enable
 740         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 741         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 742
 743 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 744
 745         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 746         available only with SSE2. Change the MMX additions introduced by SSE
 747         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 748         instructions by their now designated identifier (since combining i686
 749         and 3DNow! does not really imply 3DNow!A).
 750
 751 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 752
 753         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 754         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 755
 756 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 757             Vineet Sharma      <vineets@noida.hcltech.com>
 758
 759         * maxq.h: New file: Disassembly information for the maxq port.
 760
 761 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 762
 763         * i386.h (i386_optab): Put back "movzb".
 764
 765 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 766
 767         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 768         comments.  Remove member cris_ver_sim.  Add members
 769         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 770         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 771         (struct cris_support_reg, struct cris_cond15): New types.
 772         (cris_conds15): Declare.
 773         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 774         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 775         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 776         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 777         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 778         SIZE_FIELD_UNSIGNED.
 779
 780 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 781
 782         * i386.h (sldx_Suf): Remove.
 783         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 784         (q_FP): Define, implying no REX64.
 785         (x_FP, sl_FP): Imply FloatMF.
 786         (i386_optab): Split reg and mem forms of moving from segment registers
 787         so that the memory forms can ignore the 16-/32-bit operand size
 788         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 789         all non-floating-point instructions. Unite 32- and 64-bit forms of
 790         movsx, movzx, and movd. Adjust floating point operations for the above
 791         changes to the *FP macros. Add DefaultSize to floating point control
 792         insns operating on larger memory ranges. Remove left over comments
 793         hinting at certain insns being Intel-syntax ones where the ones
 794         actually meant are already gone.
 795
 796 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 797
 798         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 799         instruction type.
 800
 801 2004-09-30  Paul Brook  <paul@codesourcery.com>
 802
 803         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 804         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 805
 806 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 807
 808         * avr.h: Add support for
 809         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 810
 811 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 812
 813         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 814
 815 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 816
 817         * msp430.h (msp430_opc): Add new instructions.
 818         (msp430_rcodes): Declare new instructions.
 819         (msp430_hcodes): Likewise..
 820
 821 2004-08-13  Nick Clifton  <nickc@redhat.com>
 822
 823         PR/301
 824         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 825         processors.
 826
 827 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 828
 829         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 830
 831 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 832
 833         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 834
 835 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 836
 837         * i386.h: Adjust instruction descriptions to better match the
 838         specification.
 839
 840 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 841
 842         * arm.h: Remove all old content.  Replace with architecture defines
 843         from gas/config/tc-arm.c.
 844
 845 2004-07-09  Andreas Schwab  <schwab@suse.de>
 846
 847         * m68k.h: Fix comment.
 848
 849 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 850
 851         * crx.h: New file.
 852
 853 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 854
 855         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 856
 857 2004-05-24  Peter Barada  <peter@the-baradas.com>
 858
 859         * m68k.h: Add 'size' to m68k_opcode.
 860
 861 2004-05-05  Peter Barada  <peter@the-baradas.com>
 862
 863         * m68k.h: Switch from ColdFire chip name to core variant.
 864
 865 2004-04-22  Peter Barada  <peter@the-baradas.com>
 866
 867         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 868         descriptions for new EMAC cases.
 869         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 870         handle Motorola MAC syntax.
 871         Allow disassembly of ColdFire V4e object files.
 872
 873 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 874
 875         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 876
 877 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 878
 879         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 880
 881 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 882
 883         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 884
 885 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 886
 887         * i386.h (i386_optab): Added xstore/xcrypt insns.
 888
 889 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 890
 891         * h8300.h (32bit ldc/stc): Add relaxing support.
 892
 893 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 894
 895         * h8300.h (BITOP): Pass MEMRELAX flag.
 896
 897 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 898
 899         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 900         except for the H8S.
 901
 902 For older changes see ChangeLog-9103
 903 \f
 904 Local Variables:
 905 mode: change-log
 906 left-margin: 8
 907 fill-column: 74
 908 version-control: never
 909 End: