include/opcode/ChangeLog

   1 2008-02-14  Hakan Ardo  <hakan@debian.org>
   2
   3         PR gas/2626
   4         * avr.h (AVR_ISA_2xxe): Define.
   5
   6 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
   7
   8         * mips.h: Update copyright.
   9         (INSN_CHIP_MASK): New macro.
  10         (INSN_OCTEON): New macro.
  11         (CPU_OCTEON): New macro.
  12         (OPCODE_IS_MEMBER): Handle Octeon instructions.
  13
  14 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  15
  16         * mips.h (INSN_LOONGSON_2E): New.
  17         (INSN_LOONGSON_2F): New.
  18         (CPU_LOONGSON_2E): New.
  19         (CPU_LOONGSON_2F): New.
  20         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
  21
  22 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
  23
  24         * mips.h (INSN_ISA*): Redefine certain values as an
  25         enumeration.  Update comments.
  26         (mips_isa_table): New.
  27         (ISA_MIPS*): Redefine to match enumeration.
  28         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
  29         values.
  30
  31 2007-08-08  Ben Elliston  <bje@au.ibm.com>
  32
  33         * ppc.h (PPC_OPCODE_PPCPS): New.
  34
  35 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
  36
  37         * m68k.h: Document j K & E.
  38
  39 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
  40
  41         * cr16.h: New file for CR16 target.
  42
  43 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
  44
  45         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
  46
  47 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
  48
  49         * m68k.h (mcfisa_c): New.
  50         (mcfusp, mcf_mask): Adjust.
  51
  52 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
  53
  54         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
  55         (num_powerpc_operands): Declare.
  56         (PPC_OPERAND_SIGNED et al): Redefine as hex.
  57         (PPC_OPERAND_PLUS1): Define.
  58
  59 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
  60
  61         * i386.h (REX_MODE64): Renamed to ...
  62         (REX_W): This.
  63         (REX_EXTX): Renamed to ...
  64         (REX_R): This.
  65         (REX_EXTY): Renamed to ...
  66         (REX_X): This.
  67         (REX_EXTZ): Renamed to ...
  68         (REX_B): This.
  69
  70 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
  71
  72         * i386.h: Add entries from config/tc-i386.h and move tables
  73         to opcodes/i386-opc.h.
  74
  75 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
  76
  77         * i386.h (FloatDR): Removed.
  78         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
  79
  80 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
  81
  82         * spu-insns.h: Add soma double-float insns.
  83
  84 2007-02-20  Thiemo Seufer  <ths@mips.com>
  85             Chao-Ying Fu  <fu@mips.com>
  86
  87         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
  88         (INSN_DSPR2): Add flag for DSP R2 instructions.
  89         (M_BALIGN): New macro.
  90
  91 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
  92
  93         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
  94         and Seg3ShortFrom with Shortform.
  95
  96 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
  97
  98         PR gas/4027
  99         * i386.h (i386_optab): Put the real "test" before the pseudo
 100         one.
 101
 102 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 103
 104         * m68k.h (m68010up): OR fido_a.
 105
 106 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 107
 108         * m68k.h (fido_a): New.
 109
 110 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 111
 112         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 113         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 114         values.
 115
 116 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 117
 118         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 119
 120 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 121
 122         * score-inst.h (enum score_insn_type): Add Insn_internal.
 123
 124 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 125             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 126             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 127             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 128             Alan Modra  <amodra@bigpond.net.au>
 129
 130         * spu-insns.h: New file.
 131         * spu.h: New file.
 132
 133 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 134
 135         * ppc.h (PPC_OPCODE_CELL): Define.
 136
 137 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 138
 139         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 140         in amdfam10 architecture.
 141
 142 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 143
 144         * i386.h: Replace CpuMNI with CpuSSSE3.
 145
 146 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 147             Joseph Myers  <joseph@codesourcery.com>
 148             Ian Lance Taylor  <ian@wasabisystems.com>
 149             Ben Elliston  <bje@wasabisystems.com>
 150
 151         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 152
 153 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 154
 155         * score-datadep.h: New file.
 156         * score-inst.h: New file.
 157
 158 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 159
 160         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 161         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 162         movdq2q and movq2dq.
 163
 164 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 165            Michael Meissner             <michael.meissner@amd.com>
 166
 167         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 168
 169 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 170
 171         * i386.h (i386_optab): Add "nop" with memory reference.
 172
 173 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 174
 175         * i386.h (i386_optab): Update comment for 64bit NOP.
 176
 177 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 178             Anton Blanchard  <anton@samba.org>
 179
 180         * ppc.h (PPC_OPCODE_POWER6): Define.
 181         Adjust whitespace.
 182
 183 2006-06-05  Thiemo Seufer  <ths@mips.com>
 184
 185         * mips.h: Improve description of MT flags.
 186
 187 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 188
 189         * m68k.h (mcf_mask): Define.
 190
 191 2006-05-05  Thiemo Seufer  <ths@mips.com>
 192             David Ung  <davidu@mips.com>
 193
 194         * mips.h (enum): Add macro M_CACHE_AB.
 195
 196 2006-05-04  Thiemo Seufer  <ths@mips.com>
 197             Nigel Stephens  <nigel@mips.com>
 198             David Ung  <davidu@mips.com>
 199
 200         * mips.h: Add INSN_SMARTMIPS define.
 201
 202 2006-04-30  Thiemo Seufer  <ths@mips.com>
 203             David Ung  <davidu@mips.com>
 204
 205         * mips.h: Defines udi bits and masks.  Add description of
 206         characters which may appear in the args field of udi
 207         instructions.
 208
 209 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 210
 211         * mips.h: Improve comments describing the bitfield instruction
 212         fields.
 213
 214 2006-04-26  Julian Brown  <julian@codesourcery.com>
 215
 216         * arm.h (FPU_VFP_EXT_V3): Define constant.
 217         (FPU_NEON_EXT_V1): Likewise.
 218         (FPU_VFP_HARD): Update.
 219         (FPU_VFP_V3): Define macro.
 220         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 221
 222 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 223
 224         * avr.h (AVR_ISA_PWMx): New.
 225
 226 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 227
 228         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 229         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 230         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 231         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 232         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 233
 234 2006-03-10  Paul Brook  <paul@codesourcery.com>
 235
 236         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 237
 238 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 239
 240         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 241         first.  Correct mask of bb "B" opcode.
 242
 243 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 244
 245         * i386.h (i386_optab): Support Intel Merom New Instructions.
 246
 247 2006-02-24  Paul Brook  <paul@codesourcery.com>
 248
 249         * arm.h: Add V7 feature bits.
 250
 251 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 252
 253         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 254
 255 2006-01-31  Paul Brook  <paul@codesourcery.com>
 256         Richard Earnshaw <rearnsha@arm.com>
 257
 258         * arm.h: Use ARM_CPU_FEATURE.
 259         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 260         (arm_feature_set): Change to a structure.
 261         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 262         ARM_FEATURE): New macros.
 263
 264 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 265
 266         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 267         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 268         (ADD_PC_INCR_OPCODE): Don't define.
 269
 270 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 271
 272         PR gas/1874
 273         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 274
 275 2005-11-14  David Ung  <davidu@mips.com>
 276
 277         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 278         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 279         save/restore encoding of the args field.
 280
 281 2005-10-28  Dave Brolley  <brolley@redhat.com>
 282
 283         Contribute the following changes:
 284         2005-02-16  Dave Brolley  <brolley@redhat.com>
 285
 286         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 287         cgen_isa_mask_* to cgen_bitset_*.
 288         * cgen.h: Likewise.
 289
 290         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 291
 292         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 293         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 294         (CGEN_CPU_TABLE): Make isas a ponter.
 295
 296         2003-09-29  Dave Brolley  <brolley@redhat.com>
 297
 298         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 299         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 300         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 301
 302         2002-12-13  Dave Brolley  <brolley@redhat.com>
 303
 304         * cgen.h (symcat.h): #include it.
 305         (cgen-bitset.h): #include it.
 306         (CGEN_ATTR_VALUE_TYPE): Now a union.
 307         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 308         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 309         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 310         * cgen-bitset.h: New file.
 311
 312 2005-09-30  Catherine Moore  <clm@cm00re.com>
 313
 314         * bfin.h: New file.
 315
 316 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 317
 318         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 319         indirect operands.
 320
 321 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 322
 323         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 324         Add FLAG_STRICT to pa10 ftest opcode.
 325
 326 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 327
 328         * hppa.h (pa_opcodes): Remove lha entries.
 329
 330 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 331
 332         * hppa.h (FLAG_STRICT): Revise comment.
 333         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 334         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 335         entries for "fdc".
 336
 337 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 338
 339         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 340
 341 2005-09-06  Chao-ying Fu  <fu@mips.com>
 342
 343         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 344         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 345         define.
 346         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 347         (INSN_ASE_MASK): Update to include INSN_MT.
 348         (INSN_MT): New define for MT ASE.
 349
 350 2005-08-25  Chao-ying Fu  <fu@mips.com>
 351
 352         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 353         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 354         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 355         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 356         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 357         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 358         instructions.
 359         (INSN_DSP): New define for DSP ASE.
 360
 361 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 362
 363         * a29k.h: Delete.
 364
 365 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 366
 367         * ppc.h (PPC_OPCODE_E300): Define.
 368
 369 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 370
 371         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 372
 373 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 374
 375         PR gas/336
 376         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 377         and pitlb.
 378
 379 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 380
 381         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 382         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 383         Add movq-s as 64-bit variants of movd-s.
 384
 385 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 386
 387         * hppa.h: Fix punctuation in comment.
 388
 389         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 390         implicit space-register addressing.  Set space-register bits on opcodes
 391         using implicit space-register addressing.  Add various missing pa20
 392         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 393         space-register addressing.  Use "fE" instead of "fe" in various
 394         fstw opcodes.
 395
 396 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 397
 398         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 399
 400 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 401
 402         * i386.h (i386_optab): Support Intel VMX Instructions.
 403
 404 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 405
 406         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 407
 408 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 409
 410         * i386.h (i386_optab): Add new insns.
 411
 412 2005-07-01  Nick Clifton  <nickc@redhat.com>
 413
 414         * sparc.h: Add typedefs to structure declarations.
 415
 416 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 417
 418         PR 1013
 419         * i386.h (i386_optab): Update comments for 64bit addressing on
 420         mov. Allow 64bit addressing for mov and movq.
 421
 422 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 423
 424         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 425         respectively, in various floating-point load and store patterns.
 426
 427 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 428
 429         * hppa.h (FLAG_STRICT): Correct comment.
 430         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 431         PA 2.0 mneumonics when equivalent.  Entries with cache control
 432         completers now require PA 1.1.  Adjust whitespace.
 433
 434 2005-05-19  Anton Blanchard  <anton@samba.org>
 435
 436         * ppc.h (PPC_OPCODE_POWER5): Define.
 437
 438 2005-05-10  Nick Clifton  <nickc@redhat.com>
 439
 440         * Update the address and phone number of the FSF organization in
 441         the GPL notices in the following files:
 442         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 443         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 444         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 445         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 446         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 447         tic54x.h, tic80.h, v850.h, vax.h
 448
 449 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 450
 451         * i386.h (i386_optab): Add ht and hnt.
 452
 453 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 454
 455         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 456         Add xcrypt-ctr.  Provide aliases without hyphens.
 457
 458 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 459
 460         Moved from ../ChangeLog
 461
 462         2005-04-12  Paul Brook  <paul@codesourcery.com>
 463         * m88k.h: Rename psr macros to avoid conflicts.
 464
 465         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 466         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 467         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 468         and ARM_ARCH_V6ZKT2.
 469
 470         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 471         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 472         Remove redundant instruction types.
 473         (struct argument): X_op - new field.
 474         (struct cst4_entry): Remove.
 475         (no_op_insn): Declare.
 476
 477         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 478         * crx.h (enum argtype): Rename types, remove unused types.
 479
 480         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 481         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 482         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 483         (enum operand_type): Rearrange operands, edit comments.
 484         replace us<N> with ui<N> for unsigned immediate.
 485         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 486         displacements (respectively).
 487         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 488         (instruction type): Add NO_TYPE_INS.
 489         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 490         (operand_entry): New field - 'flags'.
 491         (operand flags): New.
 492
 493         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 494         * crx.h (operand_type): Remove redundant types i3, i4,
 495         i5, i8, i12.
 496         Add new unsigned immediate types us3, us4, us5, us16.
 497
 498 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
 499
 500         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
 501         adjust them accordingly.
 502
 503 2005-04-01  Jan Beulich  <jbeulich@novell.com>
 504
 505         * i386.h (i386_optab): Add rdtscp.
 506
 507 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
 508
 509         * i386.h (i386_optab): Don't allow the `l' suffix for moving
 510         between memory and segment register. Allow movq for moving between
 511         general-purpose register and segment register.
 512
 513 2005-02-09  Jan Beulich  <jbeulich@novell.com>
 514
 515         PR gas/707
 516         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
 517         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
 518         fnstsw.
 519
 520 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
 521
 522         * m68k.h (m68008, m68ec030, m68882): Remove.
 523         (m68k_mask): New.
 524         (cpu_m68k, cpu_cf): New.
 525         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
 526         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
 527
 528 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
 529
 530         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
 531         * cgen.h (enum cgen_parse_operand_type): Add
 532         CGEN_PARSE_OPERAND_SYMBOLIC.
 533
 534 2005-01-21  Fred Fish  <fnf@specifixinc.com>
 535
 536         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
 537         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
 538         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
 539
 540 2005-01-19  Fred Fish  <fnf@specifixinc.com>
 541
 542         * mips.h (struct mips_opcode): Add new pinfo2 member.
 543         (INSN_ALIAS): New define for opcode table entries that are
 544         specific instances of another entry, such as 'move' for an 'or'
 545         with a zero operand.
 546         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
 547         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
 548
 549 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
 550
 551         * mips.h (CPU_RM9000): Define.
 552         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
 553
 554 2004-11-25 Jan Beulich  <jbeulich@novell.com>
 555
 556         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
 557         to/from test registers are illegal in 64-bit mode. Add missing
 558         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
 559         (previously one had to explicitly encode a rex64 prefix). Re-enable
 560         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
 561         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
 562
 563 2004-11-23 Jan Beulich  <jbeulich@novell.com>
 564
 565         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
 566         available only with SSE2. Change the MMX additions introduced by SSE
 567         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
 568         instructions by their now designated identifier (since combining i686
 569         and 3DNow! does not really imply 3DNow!A).
 570
 571 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
 572
 573         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
 574         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
 575
 576 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
 577             Vineet Sharma      <vineets@noida.hcltech.com>
 578
 579         * maxq.h: New file: Disassembly information for the maxq port.
 580
 581 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
 582
 583         * i386.h (i386_optab): Put back "movzb".
 584
 585 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
 586
 587         * cris.h (enum cris_insn_version_usage): Tweak formatting and
 588         comments.  Remove member cris_ver_sim.  Add members
 589         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
 590         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
 591         (struct cris_support_reg, struct cris_cond15): New types.
 592         (cris_conds15): Declare.
 593         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
 594         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
 595         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
 596         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
 597         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
 598         SIZE_FIELD_UNSIGNED.
 599
 600 2004-11-04 Jan Beulich  <jbeulich@novell.com>
 601
 602         * i386.h (sldx_Suf): Remove.
 603         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
 604         (q_FP): Define, implying no REX64.
 605         (x_FP, sl_FP): Imply FloatMF.
 606         (i386_optab): Split reg and mem forms of moving from segment registers
 607         so that the memory forms can ignore the 16-/32-bit operand size
 608         distinction. Adjust a few others for Intel mode. Remove *FP uses from
 609         all non-floating-point instructions. Unite 32- and 64-bit forms of
 610         movsx, movzx, and movd. Adjust floating point operations for the above
 611         changes to the *FP macros. Add DefaultSize to floating point control
 612         insns operating on larger memory ranges. Remove left over comments
 613         hinting at certain insns being Intel-syntax ones where the ones
 614         actually meant are already gone.
 615
 616 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
 617
 618         * crx.h: Add COPS_REG_INS - Coprocessor Special register
 619         instruction type.
 620
 621 2004-09-30  Paul Brook  <paul@codesourcery.com>
 622
 623         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
 624         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
 625
 626 2004-09-11  Theodore A. Roth  <troth@openavr.org>
 627
 628         * avr.h: Add support for
 629         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
 630
 631 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
 632
 633         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
 634
 635 2004-08-24  Dmitry Diky  <diwil@spec.ru>
 636
 637         * msp430.h (msp430_opc): Add new instructions.
 638         (msp430_rcodes): Declare new instructions.
 639         (msp430_hcodes): Likewise..
 640
 641 2004-08-13  Nick Clifton  <nickc@redhat.com>
 642
 643         PR/301
 644         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
 645         processors.
 646
 647 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
 648
 649         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
 650
 651 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
 652
 653         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
 654
 655 2004-07-21  Jan Beulich  <jbeulich@novell.com>
 656
 657         * i386.h: Adjust instruction descriptions to better match the
 658         specification.
 659
 660 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
 661
 662         * arm.h: Remove all old content.  Replace with architecture defines
 663         from gas/config/tc-arm.c.
 664
 665 2004-07-09  Andreas Schwab  <schwab@suse.de>
 666
 667         * m68k.h: Fix comment.
 668
 669 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
 670
 671         * crx.h: New file.
 672
 673 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
 674
 675         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
 676
 677 2004-05-24  Peter Barada  <peter@the-baradas.com>
 678
 679         * m68k.h: Add 'size' to m68k_opcode.
 680
 681 2004-05-05  Peter Barada  <peter@the-baradas.com>
 682
 683         * m68k.h: Switch from ColdFire chip name to core variant.
 684
 685 2004-04-22  Peter Barada  <peter@the-baradas.com>
 686
 687         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
 688         descriptions for new EMAC cases.
 689         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
 690         handle Motorola MAC syntax.
 691         Allow disassembly of ColdFire V4e object files.
 692
 693 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
 694
 695         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
 696
 697 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
 698
 699         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
 700
 701 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 702
 703         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
 704
 705 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
 706
 707         * i386.h (i386_optab): Added xstore/xcrypt insns.
 708
 709 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 710
 711         * h8300.h (32bit ldc/stc): Add relaxing support.
 712
 713 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
 714
 715         * h8300.h (BITOP): Pass MEMRELAX flag.
 716
 717 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
 718
 719         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
 720         except for the H8S.
 721
 722 For older changes see ChangeLog-9103
 723 \f
 724 Local Variables:
 725 mode: change-log
 726 left-margin: 8
 727 fill-column: 74
 728 version-control: never
 729 End: