include/opcode/ChangeLog

   1 2011-06-18  Robin Getz  <robin.getz@analog.com>
   2
   3         * bfin.h (is_macmod_signed): New func
   4
   5 2011-06-18  Mike Frysinger  <vapier@gentoo.org>
   6
   7         * bfin.h (is_macmod_pmove): Add missing space before func args.
   8         (is_macmod_hmove): Likewise.
   9
  10 2011-06-13  Walter Lee  <walt@tilera.com>
  11
  12         * tilegx.h: New file.
  13         * tilepro.h: New file.
  14
  15 2011-05-31  Paul Brook  <paul@codesourcery.com>
  16
  17         * arm.h (ARM_ARCH_V7R_IDIV): Define.
  18
  19 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  20
  21         * s390.h: Replace S390_OPERAND_REG_EVEN with
  22         S390_OPERAND_REG_PAIR.
  23
  24 2011-05-24  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  25
  26         * s390.h: Add S390_OPCODE_REG_EVEN flag.
  27
  28 2011-04-18  Julian Brown  <julian@codesourcery.com>
  29
  30         * arm.h (ARM_AEXT_V7_ARM): Remove ARM_EXT_OS from bitmask.
  31
  32 2011-04-11  Dan McDonald  <dan@wellkeeper.com>
  33
  34         PR gas/12296
  35         * arm.h (ARM_AEXT_V7_ARM): Add ARM_EXT_OS.
  36
  37 2011-03-22  Eric B. Weddington  <eric.weddington@atmel.com>
  38
  39         * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
  40         New instruction set flags.
  41         (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
  42
  43 2011-02-28  Maciej W. Rozycki  <macro@codesourcery.com>
  44
  45         * mips.h (M_PREF_AB): New enum value.
  46
  47 2011-02-12  Mike Frysinger  <vapier@gentoo.org>
  48
  49         * bfin.h (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, M_IH,
  50         M_IU): Define.
  51         (is_macmod_pmove, is_macmod_hmove): New functions.
  52
  53 2011-02-11  Mike Frysinger  <vapier@gentoo.org>
  54
  55         * bfin.h: Add OPCODE_BFIN_H ifdef multiple include protection.
  56
  57 2011-02-04  Bernd Schmidt  <bernds@codesourcery.com>
  58
  59         * tic6x-opcode-table.h (cmtl, ll, sl): Available on C64XP.
  60         * tic6x.h (TIC6X_INSN_ATOMIC): Remove.
  61
  62 2010-12-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  63
  64         PR gas/11395
  65         * hppa.h (pa_opcodes): Revert last change.  Exchange 32 and 64-bit
  66         "bb" entries.
  67
  68 2010-12-26  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
  69
  70         PR gas/11395
  71         * hppa.h: Clear "d" bit in "add" and "sub" patterns.
  72
  73 2010-12-18  Richard Sandiford  <rdsandiford@googlemail.com>
  74
  75         * mips.h: Update commentary after last commit.
  76
  77 2010-12-18  Mingjie Xing  <mingjie.xing@gmail.com>
  78
  79         * mips.h (OP_*_OFFSET_A, OP_*_OFFSET_B, OP_*_OFFSET_C)
  80         (OP_*_RZ, OP_*_FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z)
  81         (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define.
  82
  83 2010-11-25  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
  84
  85         * s390.h (enum s390_opcode_cpu_val): Add S390_OPCODE_MAXCPU.
  86
  87 2010-11-23  Richard Sandiford  <rdsandiford@googlemail.com>
  88
  89         * mips.h: Fix previous commit.
  90
  91 2010-11-23  Maciej W. Rozycki  <macro@linux-mips.org>
  92
  93         * mips.h (INSN_CHIP_MASK): Update according to INSN_LOONGSON_3A.
  94         (INSN_LOONGSON_3A): Clear bit 31.
  95
  96 2010-11-15  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
  97
  98         PR gas/12198
  99         * arm.h (ARM_AEXT_V6M_ONLY): New define.
 100         (ARM_AEXT_V6M): Rewrite in terms of ARM_AEXT_V6M_ONLY.
 101         (ARM_ARCH_V6M_ONLY): New define.
 102
 103 2010-11-11  Mingming Sun  <mingm.sun@gmail.com>
 104
 105         * mips.h (INSN_LOONGSON_3A): Defined.
 106         (CPU_LOONGSON_3A): Defined.
 107         (OPCODE_IS_MEMBER): Add LOONGSON_3A.
 108
 109 2010-10-09  Matt Rice  <ratmice@gmail.com>
 110
 111         * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_.
 112         (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise.
 113
 114 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 115
 116         * arm.h (ARM_EXT_VIRT): New define.
 117         (ARM_ARCH_V7A_IDIV_MP_SEC): Rename...
 118         (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization
 119         Extensions.
 120
 121 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 122
 123         * arm.h (ARM_AEXT_ADIV): New define.
 124         (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise.
 125
 126 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 127
 128         * arm.h (ARM_EXT_OS): New define.
 129         (ARM_AEXT_V6SM): Likewise.
 130         (ARM_ARCH_V6SM): Likewise.
 131
 132 2010-09-23  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>
 133
 134         * arm.h (ARM_EXT_MP): Add.
 135         (ARM_ARCH_V7A_MP): Likewise.
 136
 137 2010-09-22  Mike Frysinger  <vapier@gentoo.org>
 138
 139         * bfin.h: Declare pseudoChr structs/defines.
 140
 141 2010-09-21  Mike Frysinger  <vapier@gentoo.org>
 142
 143         * bfin.h: Strip trailing whitespace.
 144
 145 2010-07-29  DJ Delorie  <dj@redhat.com>
 146
 147         * rx.h (RX_Operand_Type): Add TwoReg.
 148         (RX_Opcode_ID): Remove ediv and ediv2.
 149
 150 2010-07-27  DJ Delorie  <dj@redhat.com>
 151
 152         * rx.h (RX_Opcode_ID): Add nop2 and nop3 for statistics.
 153
 154 2010-07-23  Naveen.H.S  <naveen.S@kpitcummins.com>
 155             Ina Pandit  <ina.pandit@kpitcummins.com>
 156
 157         * v850.h: Define PROCESSOR_MASK, PROCESSOR_OPTION_EXTENSION,
 158         PROCESSOR_OPTION_ALIAS, PROCESSOR_V850E2, PROCESSOR_V850E2V3 and
 159         PROCESSOR_V850E2_ALL.
 160         Remove PROCESSOR_V850EA support.
 161         (v850_operand): Define V850_OPERAND_EP, V850_OPERAND_FLOAT_CC,
 162         V850_OPERAND_VREG, V850E_IMMEDIATE16, V850E_IMMEDIATE16HI,
 163         V850E_IMMEDIATE23, V850E_IMMEDIATE32, V850_OPERAND_SIGNED,
 164         V850_OPERAND_DISP, V850_PCREL, V850_REG_EVEN, V850E_PUSH_POP,
 165         V850_NOT_IMM0, V850_NOT_SA, V850_OPERAND_BANG and
 166         V850_OPERAND_PERCENT.
 167         Update V850_OPERAND_SRG, V850_OPERAND_CC, V850_OPERAND_RELAX and
 168         V850_NOT_R0.
 169         Remove V850_OPERAND_SIGNED, V850_OPERAND_EP, V850_OPERAND_DISP
 170         and V850E_PUSH_POP
 171
 172 2010-07-06  Maciej W. Rozycki  <macro@codesourcery.com>
 173
 174         * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
 175         (MIPS16_INSN_BRANCH): Rename to...
 176         (MIPS16_INSN_COND_BRANCH): ... this.
 177
 178 2010-07-03  Alan Modra  <amodra@gmail.com>
 179
 180         * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
 181         Renumber other PPC_OPCODE defines.
 182
 183 2010-07-03  Alan Modra  <amodra@gmail.com>
 184
 185         * ppc.h (PPC_OPCODE_COMMON): Expand comment.
 186
 187 2010-06-29  Alan Modra  <amodra@gmail.com>
 188
 189         * maxq.h: Delete file.
 190
 191 2010-06-14  Sebastian Andrzej Siewior  <bigeasy@linutronix.de>
 192
 193         * ppc.h (PPC_OPCODE_E500): Define.
 194
 195 2010-05-26  Catherine Moore  <clm@codesourcery.com>
 196
 197         * opcode/mips.h (INSN_MIPS16): Remove.
 198
 199 2010-04-21  Joseph Myers  <joseph@codesourcery.com>
 200
 201         * tic6x-insn-formats.h (s_branch): Correct typo in bitmask.
 202
 203 2010-04-15  Nick Clifton  <nickc@redhat.com>
 204
 205         * alpha.h: Update copyright notice to use GPLv3.
 206         * arc.h: Likewise.
 207         * arm.h: Likewise.
 208         * avr.h: Likewise.
 209         * bfin.h: Likewise.
 210         * cgen.h: Likewise.
 211         * convex.h: Likewise.
 212         * cr16.h: Likewise.
 213         * cris.h: Likewise.
 214         * crx.h: Likewise.
 215         * d10v.h: Likewise.
 216         * d30v.h: Likewise.
 217         * dlx.h: Likewise.
 218         * h8300.h: Likewise.
 219         * hppa.h: Likewise.
 220         * i370.h: Likewise.
 221         * i386.h: Likewise.
 222         * i860.h: Likewise.
 223         * i960.h: Likewise.
 224         * ia64.h: Likewise.
 225         * m68hc11.h: Likewise.
 226         * m68k.h: Likewise.
 227         * m88k.h: Likewise.
 228         * maxq.h: Likewise.
 229         * mips.h: Likewise.
 230         * mmix.h: Likewise.
 231         * mn10200.h: Likewise.
 232         * mn10300.h: Likewise.
 233         * msp430.h: Likewise.
 234         * np1.h: Likewise.
 235         * ns32k.h: Likewise.
 236         * or32.h: Likewise.
 237         * pdp11.h: Likewise.
 238         * pj.h: Likewise.
 239         * pn.h: Likewise.
 240         * ppc.h: Likewise.
 241         * pyr.h: Likewise.
 242         * rx.h: Likewise.
 243         * s390.h: Likewise.
 244         * score-datadep.h: Likewise.
 245         * score-inst.h: Likewise.
 246         * sparc.h: Likewise.
 247         * spu-insns.h: Likewise.
 248         * spu.h: Likewise.
 249         * tic30.h: Likewise.
 250         * tic4x.h: Likewise.
 251         * tic54x.h: Likewise.
 252         * tic80.h: Likewise.
 253         * v850.h: Likewise.
 254         * vax.h: Likewise.
 255
 256 2010-03-25  Joseph Myers  <joseph@codesourcery.com>
 257
 258         * tic6x-control-registers.h, tic6x-insn-formats.h,
 259         tic6x-opcode-table.h, tic6x.h: New.
 260
 261 2010-02-25  Wu Zhangjin  <wuzhangjin@gmail.com>
 262
 263         * mips.h: (LOONGSON2F_NOP_INSN): New macro.
 264
 265 2010-02-08  Philipp Tomsich  <philipp.tomsich@theobroma-systems.com>
 266
 267         * opcode/ppc.h (PPC_OPCODE_TITAN): Define.
 268
 269 2010-01-14  H.J. Lu  <hongjiu.lu@intel.com>
 270
 271         * ia64.h (ia64_find_opcode): Remove argument name.
 272         (ia64_find_next_opcode): Likewise.
 273         (ia64_dis_opcode): Likewise.
 274         (ia64_free_opcode): Likewise.
 275         (ia64_find_dependency): Likewise.
 276
 277 2009-11-22  Doug Evans  <dje@sebabeach.org>
 278
 279         * cgen.h: Include bfd_stdint.h.
 280         (CGEN_INSN_LGSINT, CGEN_INSN_LGUINT): New types.
 281
 282 2009-11-18  Paul Brook  <paul@codesourcery.com>
 283
 284         * arm.h (FPU_VFP_V4_SP_D16, FPU_ARCH_VFP_V4_SP_D16): Define.
 285
 286 2009-11-17  Paul Brook  <paul@codesourcery.com>
 287         Daniel Jacobowitz  <dan@codesourcery.com>
 288
 289         * arm.h (ARM_EXT_V6_DSP): Define.
 290         (ARM_AEXT_V6T2, ARM_AEXT_NOTM): Include ARM_EXT_V6_DSP.
 291         (ARM_AEXT_V7EM, ARM_ARCH_V7EM): Define.
 292
 293 2009-11-04  DJ Delorie  <dj@redhat.com>
 294
 295         * rx.h (rx_decode_opcode) (mvtipl): Add.
 296         (mvtcp, mvfcp, opecp): Remove.
 297
 298 2009-11-02  Paul Brook  <paul@codesourcery.com>
 299
 300         * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA,
 301         FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define.
 302         (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD,
 303         FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16,
 304         FPU_ARCH_NEON_VFP_V4): Define.
 305
 306 2009-10-23  Doug Evans  <dje@sebabeach.org>
 307
 308         * cgen-bitset.h: Delete, moved to ../cgen/bitset.h.
 309         * cgen.h: Update.  Improve multi-inclusion macro name.
 310
 311 2009-10-02  Peter Bergner  <bergner@vnet.ibm.com>
 312
 313         * ppc.h (PPC_OPCODE_476): Define.
 314
 315 2009-10-01  Peter Bergner  <bergner@vnet.ibm.com>
 316
 317         * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2.
 318
 319 2009-09-29  DJ Delorie  <dj@redhat.com>
 320
 321         * rx.h: New file.
 322
 323 2009-09-22  Peter Bergner  <bergner@vnet.ibm.com>
 324
 325         * ppc.h (ppc_cpu_t): Typedef to uint64_t.
 326
 327 2009-09-21  Ben Elliston  <bje@au.ibm.com>
 328
 329         * ppc.h (PPC_OPCODE_PPCA2): New.
 330
 331 2009-09-05  Martin Thuresson  <martin@mtme.org>
 332
 333         * ia64.h (struct ia64_operand): Renamed member class to op_class.
 334
 335 2009-08-29  Martin Thuresson  <martin@mtme.org>
 336
 337         * tic30.h (template): Rename type template to
 338         insn_template. Updated code to use new name.
 339         * tic54x.h (template): Rename type template to
 340         insn_template.
 341
 342 2009-08-20  Nick Hudson  <nick.hudson@gmx.co.uk>
 343
 344         * hppa.h (pa_opcodes): Add a pa10 bb without FLAG_STRICT.
 345
 346 2009-06-11  Anthony Green  <green@moxielogic.com>
 347
 348         * moxie.h (MOXIE_F3_PCREL): Define.
 349         (moxie_form3_opc_info): Grow.
 350
 351 2009-06-06  Anthony Green  <green@moxielogic.com>
 352
 353         * moxie.h (MOXIE_F1_M): Define.
 354
 355 2009-04-15  Anthony Green  <green@moxielogic.com>
 356
 357         * moxie.h: Created.
 358
 359 2009-04-06  DJ Delorie  <dj@redhat.com>
 360
 361         * h8300.h: Add relaxation attributes to MOVA opcodes.
 362
 363 2009-03-10  Alan Modra  <amodra@bigpond.net.au>
 364
 365         * ppc.h (ppc_parse_cpu): Declare.
 366
 367 2009-03-02  Qinwei  <qinwei@sunnorth.com.cn>
 368
 369         * score-inst.h (score_insn_type, score_data_type): Add Ra_I9_I5
 370         and _IMM11 for mbitclr and mbitset.
 371         * score-datadep.h: Update dependency information.
 372
 373 2009-02-26  Peter Bergner  <bergner@vnet.ibm.com>
 374
 375         * ppc.h (PPC_OPCODE_POWER7): New.
 376
 377 2009-02-06  Doug Evans  <dje@google.com>
 378
 379         * i386.h: Add comment regarding sse* insns and prefixes.
 380
 381 2009-02-03  Sandip Matte  <sandip@rmicorp.com>
 382
 383         * mips.h (INSN_XLR): Define.
 384         (INSN_CHIP_MASK): Update.
 385         (CPU_XLR): Define.
 386         (OPCODE_IS_MEMBER): Update.
 387         (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define.
 388
 389 2009-01-28  Doug Evans  <dje@google.com>
 390
 391         * opcode/i386.h: Add multiple inclusion protection.
 392         (EAX_REG_NUM,ECX_REG_NUM,EDX_REGNUM,EBX_REG_NUM,ESI_REG_NUM)
 393         (EDI_REG_NUM): New macros.
 394         (MODRM_MOD_FIELD,MODRM_REG_FIELD,MODRM_RM_FIELD): New macros.
 395         (SIB_SCALE_FIELD,SIB_INDEX_FIELD,SIB_BASE_FIELD): New macros.
 396         (REX_PREFIX_P): New macro.
 397
 398 2009-01-09  Peter Bergner  <bergner@vnet.ibm.com>
 399
 400         * ppc.h (struct powerpc_opcode): New field "deprecated".
 401         (PPC_OPCODE_NOPOWER4): Delete.
 402
 403 2008-11-28  Joshua Kinard  <kumba@gentoo.org>
 404
 405         * mips.h: Define CPU_R14000, CPU_R16000.
 406         (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
 407
 408 2008-11-18  Catherine Moore  <clm@codesourcery.com>
 409
 410         * arm.h (FPU_NEON_FP16): New.
 411         (FPU_ARCH_NEON_FP16): New.
 412
 413 2008-11-06  Chao-ying Fu  <fu@mips.com>
 414
 415         * mips.h: Doucument '1' for 5-bit sync type.
 416
 417 2008-08-28  H.J. Lu  <hongjiu.lu@intel.com>
 418
 419         * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB.  Update
 420         IA64_RS_CR.
 421
 422 2008-08-01  Peter Bergner  <bergner@vnet.ibm.com>
 423
 424         * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New.
 425
 426 2008-07-30  Michael J. Eager  <eager@eagercon.com>
 427
 428         * ppc.h (PPC_OPCODE_405): Define.
 429         (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define.
 430
 431 2008-06-13  Peter Bergner  <bergner@vnet.ibm.com>
 432
 433         * ppc.h (ppc_cpu_t): New typedef.
 434         (struct powerpc_opcode <flags>): Use it.
 435         (struct powerpc_operand <insert, extract>): Likewise.
 436         (struct powerpc_macro <flags>): Likewise.
 437
 438 2008-06-12  Adam Nemet  <anemet@caviumnetworks.com>
 439
 440         * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S.
 441         Update comment before MIPS16 field descriptors to mention MIPS16.
 442         (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for
 443         BBIT.
 444         (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1):
 445         New bit masks and shift counts for cins and exts.
 446
 447         * mips.h: Document new field descriptors +Q.
 448         (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI.
 449
 450 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 451
 452         * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
 453         (INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
 454
 455 2008-04-14  Edmar Wienskoski  <edmar@freescale.com>
 456
 457         * ppc.h: (PPC_OPCODE_E500MC): New.
 458
 459 2008-04-03  H.J. Lu  <hongjiu.lu@intel.com>
 460
 461         * i386.h (MAX_OPERANDS): Set to 5.
 462         (MAX_MNEM_SIZE): Changed to 20.
 463
 464 2008-03-28  Eric B. Weddington  <eric.weddington@atmel.com>
 465
 466         * avr.h (AVR_ISA_TINY3): Define new opcode set for attiny167.
 467
 468 2008-03-09  Paul Brook  <paul@codesourcery.com>
 469
 470         * arm.h (FPU_VFP_EXT_D32, FPU_VFP_V3D16, FPU_ARCH_VFP_V3D16): Define.
 471
 472 2008-03-04  Paul Brook  <paul@codesourcery.com>
 473
 474         * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
 475         (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
 476         (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
 477
 478 2008-02-27  Denis Vlasenko  <vda.linux@googlemail.com>
 479             Nick Clifton  <nickc@redhat.com>
 480
 481         PR 3134
 482         * h8300.h (h8_opcodes): Add an encoding for a mov.l instruction
 483         with a 32-bit displacement but without the top bit of the 4th byte
 484         set.
 485
 486 2008-02-18  M R Swami Reddy <MR.Swami.Reddy@nsc.com>
 487
 488         * cr16.h (cr16_num_optab): Declared.
 489
 490 2008-02-14  Hakan Ardo  <hakan@debian.org>
 491
 492         PR gas/2626
 493         * avr.h (AVR_ISA_2xxe): Define.
 494
 495 2008-02-04  Adam Nemet  <anemet@caviumnetworks.com>
 496
 497         * mips.h: Update copyright.
 498         (INSN_CHIP_MASK): New macro.
 499         (INSN_OCTEON): New macro.
 500         (CPU_OCTEON): New macro.
 501         (OPCODE_IS_MEMBER): Handle Octeon instructions.
 502
 503 2008-01-23  Eric B. Weddington  <eric.weddington@atmel.com>
 504
 505         * avr.h (AVR_ISA_RF401): Add new opcode set for at86rf401.
 506
 507 2008-01-03  Eric B. Weddington  <eric.weddington@atmel.com>
 508
 509         * avr.h (AVR_ISA_USB162): Add new opcode set.
 510         (AVR_ISA_AVR3): Likewise.
 511
 512 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 513
 514         * mips.h (INSN_LOONGSON_2E): New.
 515         (INSN_LOONGSON_2F): New.
 516         (CPU_LOONGSON_2E): New.
 517         (CPU_LOONGSON_2F): New.
 518         (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
 519
 520 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 521
 522         * mips.h (INSN_ISA*): Redefine certain values as an
 523         enumeration.  Update comments.
 524         (mips_isa_table): New.
 525         (ISA_MIPS*): Redefine to match enumeration.
 526         (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA*
 527         values.
 528
 529 2007-08-08  Ben Elliston  <bje@au.ibm.com>
 530
 531         * ppc.h (PPC_OPCODE_PPCPS): New.
 532
 533 2007-07-03  Nathan Sidwell  <nathan@codesourcery.com>
 534
 535         * m68k.h: Document j K & E.
 536
 537 2007-06-29  M R Swami Reddy  <MR.Swami.Reddy@nsc.com>
 538
 539         * cr16.h: New file for CR16 target.
 540
 541 2007-05-02  Alan Modra  <amodra@bigpond.net.au>
 542
 543         * ppc.h (PPC_OPERAND_PLUS1): Update comment.
 544
 545 2007-04-23  Nathan Sidwell  <nathan@codesourcery.com>
 546
 547         * m68k.h (mcfisa_c): New.
 548         (mcfusp, mcf_mask): Adjust.
 549
 550 2007-04-20  Alan Modra  <amodra@bigpond.net.au>
 551
 552         * ppc.h (struct powerpc_operand): Replace "bits" with "bitm".
 553         (num_powerpc_operands): Declare.
 554         (PPC_OPERAND_SIGNED et al): Redefine as hex.
 555         (PPC_OPERAND_PLUS1): Define.
 556
 557 2007-03-21  H.J. Lu  <hongjiu.lu@intel.com>
 558
 559         * i386.h (REX_MODE64): Renamed to ...
 560         (REX_W): This.
 561         (REX_EXTX): Renamed to ...
 562         (REX_R): This.
 563         (REX_EXTY): Renamed to ...
 564         (REX_X): This.
 565         (REX_EXTZ): Renamed to ...
 566         (REX_B): This.
 567
 568 2007-03-15  H.J. Lu  <hongjiu.lu@intel.com>
 569
 570         * i386.h: Add entries from config/tc-i386.h and move tables
 571         to opcodes/i386-opc.h.
 572
 573 2007-03-13  H.J. Lu  <hongjiu.lu@intel.com>
 574
 575         * i386.h (FloatDR): Removed.
 576         (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR.
 577
 578 2007-03-01  Alan Modra  <amodra@bigpond.net.au>
 579
 580         * spu-insns.h: Add soma double-float insns.
 581
 582 2007-02-20  Thiemo Seufer  <ths@mips.com>
 583             Chao-Ying Fu  <fu@mips.com>
 584
 585         * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
 586         (INSN_DSPR2): Add flag for DSP R2 instructions.
 587         (M_BALIGN): New macro.
 588
 589 2007-02-14  Alan Modra  <amodra@bigpond.net.au>
 590
 591         * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm
 592         and Seg3ShortFrom with Shortform.
 593
 594 2007-02-11  H.J. Lu  <hongjiu.lu@intel.com>
 595
 596         PR gas/4027
 597         * i386.h (i386_optab): Put the real "test" before the pseudo
 598         one.
 599
 600 2007-01-08  Kazu Hirata  <kazu@codesourcery.com>
 601
 602         * m68k.h (m68010up): OR fido_a.
 603
 604 2006-12-25  Kazu Hirata  <kazu@codesourcery.com>
 605
 606         * m68k.h (fido_a): New.
 607
 608 2006-12-24  Kazu Hirata  <kazu@codesourcery.com>
 609
 610         * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a,
 611         mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined
 612         values.
 613
 614 2006-11-08  H.J. Lu  <hongjiu.lu@intel.com>
 615
 616         * i386.h (i386_optab): Replace CpuPNI with CpuSSE3.
 617
 618 2006-10-31  Mei Ligang  <ligang@sunnorth.com.cn>
 619
 620         * score-inst.h (enum score_insn_type): Add Insn_internal.
 621
 622 2006-10-25  Trevor Smigiel  <Trevor_Smigiel@playstation.sony.com>
 623             Yukishige Shibata  <shibata@rd.scei.sony.co.jp>
 624             Nobuhisa Fujinami  <fnami@rd.scei.sony.co.jp>
 625             Takeaki Fukuoka  <fukuoka@rd.scei.sony.co.jp>
 626             Alan Modra  <amodra@bigpond.net.au>
 627
 628         * spu-insns.h: New file.
 629         * spu.h: New file.
 630
 631 2006-10-24  Andrew Pinski  <andrew_pinski@playstation.sony.com>
 632
 633         * ppc.h (PPC_OPCODE_CELL): Define.
 634
 635 2006-10-23  Dwarakanath Rajagopal  <dwarak.rajagopal@amd.com>
 636
 637         * i386.h :  Modify opcode to support for the change in POPCNT opcode
 638         in amdfam10 architecture.
 639
 640 2006-09-28  H.J. Lu  <hongjiu.lu@intel.com>
 641
 642         * i386.h: Replace CpuMNI with CpuSSSE3.
 643
 644 2006-09-26  Mark Shinwell  <shinwell@codesourcery.com>
 645             Joseph Myers  <joseph@codesourcery.com>
 646             Ian Lance Taylor  <ian@wasabisystems.com>
 647             Ben Elliston  <bje@wasabisystems.com>
 648
 649         * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
 650
 651 2006-09-17  Mei Ligang  <ligang@sunnorth.com.cn>
 652
 653         * score-datadep.h: New file.
 654         * score-inst.h: New file.
 655
 656 2006-07-14  H.J. Lu  <hongjiu.lu@intel.com>
 657
 658         * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps,
 659         movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu,
 660         movdq2q and movq2dq.
 661
 662 2006-07-10 Dwarakanath Rajagopal        <dwarak.rajagopal@amd.com>
 663            Michael Meissner             <michael.meissner@amd.com>
 664
 665         * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions).
 666
 667 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 668
 669         * i386.h (i386_optab): Add "nop" with memory reference.
 670
 671 2006-06-12  H.J. Lu  <hongjiu.lu@intel.com>
 672
 673         * i386.h (i386_optab): Update comment for 64bit NOP.
 674
 675 2006-06-06  Ben Elliston  <bje@au.ibm.com>
 676             Anton Blanchard  <anton@samba.org>
 677
 678         * ppc.h (PPC_OPCODE_POWER6): Define.
 679         Adjust whitespace.
 680
 681 2006-06-05  Thiemo Seufer  <ths@mips.com>
 682
 683         * mips.h: Improve description of MT flags.
 684
 685 2006-05-25  Richard Sandiford  <richard@codesourcery.com>
 686
 687         * m68k.h (mcf_mask): Define.
 688
 689 2006-05-05  Thiemo Seufer  <ths@mips.com>
 690             David Ung  <davidu@mips.com>
 691
 692         * mips.h (enum): Add macro M_CACHE_AB.
 693
 694 2006-05-04  Thiemo Seufer  <ths@mips.com>
 695             Nigel Stephens  <nigel@mips.com>
 696             David Ung  <davidu@mips.com>
 697
 698         * mips.h: Add INSN_SMARTMIPS define.
 699
 700 2006-04-30  Thiemo Seufer  <ths@mips.com>
 701             David Ung  <davidu@mips.com>
 702
 703         * mips.h: Defines udi bits and masks.  Add description of
 704         characters which may appear in the args field of udi
 705         instructions.
 706
 707 2006-04-26  Thiemo Seufer  <ths@networkno.de>
 708
 709         * mips.h: Improve comments describing the bitfield instruction
 710         fields.
 711
 712 2006-04-26  Julian Brown  <julian@codesourcery.com>
 713
 714         * arm.h (FPU_VFP_EXT_V3): Define constant.
 715         (FPU_NEON_EXT_V1): Likewise.
 716         (FPU_VFP_HARD): Update.
 717         (FPU_VFP_V3): Define macro.
 718         (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros.
 719
 720 2006-04-07  Joerg Wunsch  <j.gnu@uriah.heep.sax.de>
 721
 722         * avr.h (AVR_ISA_PWMx): New.
 723
 724 2006-03-28  Nathan Sidwell  <nathan@codesourcery.com>
 725
 726         * m68k.h (cpu_m68k, cpu_cf, cpu_m68000, cpu_m68008, cpu_m68010,
 727         cpu_m68020, cpu_m68ec030, cpu_m68040, cpu_m68060, cpu_m68851,
 728         cpu_m68881, cpu_m68882, cpu_cpu32, cpu_cf5200, cpu_cf5206e,
 729         cpu_cf5208, cpu_cf521x, cpu_cf5213, cpu_cf5249, cpu_cf528x,
 730         cpu_cf5307, cpu_cf5329, cpu_cf5407, cpu_cf547x, cpu_cf548x): Remove.
 731
 732 2006-03-10  Paul Brook  <paul@codesourcery.com>
 733
 734         * arm.h (ARM_AEXT_V7_ARM): Include v6ZK extensions.
 735
 736 2006-03-04  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 737
 738         * hppa.h (pa_opcodes): Reorder bb opcodes so that pa10 opcodes come
 739         first.  Correct mask of bb "B" opcode.
 740
 741 2006-02-27  H.J. Lu <hongjiu.lu@intel.com>
 742
 743         * i386.h (i386_optab): Support Intel Merom New Instructions.
 744
 745 2006-02-24  Paul Brook  <paul@codesourcery.com>
 746
 747         * arm.h: Add V7 feature bits.
 748
 749 2006-02-23  H.J. Lu  <hongjiu.lu@intel.com>
 750
 751         * ia64.h (ia64_opnd): Add IA64_OPND_IMMU5b.
 752
 753 2006-01-31  Paul Brook  <paul@codesourcery.com>
 754         Richard Earnshaw <rearnsha@arm.com>
 755
 756         * arm.h: Use ARM_CPU_FEATURE.
 757         (ARM_AEXT_*, FPU_ENDIAN_PURE, FPU_VFP_HARD): New.
 758         (arm_feature_set): Change to a structure.
 759         (ARM_CPU_HAS_FEATURE, ARM_MERGE_FEATURE_SETS, ARM_CLEAR_FEATURE,
 760         ARM_FEATURE): New macros.
 761
 762 2005-12-07  Hans-Peter Nilsson  <hp@axis.com>
 763
 764         * cris.h (MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS)
 765         (MOVE_PC_INCR_OPCODE_PREFIX, MOVE_PC_INCR_OPCODE_SUFFIX): New macros.
 766         (ADD_PC_INCR_OPCODE): Don't define.
 767
 768 2005-12-06  H.J. Lu  <hongjiu.lu@intel.com>
 769
 770         PR gas/1874
 771         * i386.h (i386_optab): Add 64bit support for monitor and mwait.
 772
 773 2005-11-14  David Ung  <davidu@mips.com>
 774
 775         * mips.h: Assign 'm'/'M' codes to MIPS16e save/restore
 776         instructions.  Define MIPS16_ALL_ARGS and MIPS16_ALL_STATICS for
 777         save/restore encoding of the args field.
 778
 779 2005-10-28  Dave Brolley  <brolley@redhat.com>
 780
 781         Contribute the following changes:
 782         2005-02-16  Dave Brolley  <brolley@redhat.com>
 783
 784         * cgen-bitset.h: Rename CGEN_ISA_MASK to CGEN_BITSET. Rename
 785         cgen_isa_mask_* to cgen_bitset_*.
 786         * cgen.h: Likewise.
 787
 788         2003-10-21  Richard Sandiford  <rsandifo@redhat.com>
 789
 790         * cgen.h (CGEN_BITSET_ATTR_VALUE): Fix definition.
 791         (CGEN_ATTR_ENTRY): Change "value" to type "unsigned".
 792         (CGEN_CPU_TABLE): Make isas a ponter.
 793
 794         2003-09-29  Dave Brolley  <brolley@redhat.com>
 795
 796         * cgen.h (CGEN_ATTR_VALUE_BITSET_TYPE): New typedef.
 797         (CGEN_ATTR_VALUE_ENUM_TYPE): Ditto.
 798         (CGEN_ATTR_VALUE_TYPE): Use these new typedefs.
 799
 800         2002-12-13  Dave Brolley  <brolley@redhat.com>
 801
 802         * cgen.h (symcat.h): #include it.
 803         (cgen-bitset.h): #include it.
 804         (CGEN_ATTR_VALUE_TYPE): Now a union.
 805         (CGEN_ATTR_VALUE): Reference macros generated in opcodes/<arch>-desc.h.
 806         (CGEN_ATTR_ENTRY): 'value' now unsigned.
 807         (cgen_cpu_desc): 'isas' now (CGEN_ISA_MASK*).
 808         * cgen-bitset.h: New file.
 809
 810 2005-09-30  Catherine Moore  <clm@cm00re.com>
 811
 812         * bfin.h: New file.
 813
 814 2005-10-24  Jan Beulich  <jbeulich@novell.com>
 815
 816         * ia64.h (enum ia64_opnd): Move memory operand out of set of
 817         indirect operands.
 818
 819 2005-10-16  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 820
 821         * hppa.h (pa_opcodes): Add two fcmp opcodes.  Reorder ftest opcodes.
 822         Add FLAG_STRICT to pa10 ftest opcode.
 823
 824 2005-10-12  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 825
 826         * hppa.h (pa_opcodes): Remove lha entries.
 827
 828 2005-10-08  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 829
 830         * hppa.h (FLAG_STRICT): Revise comment.
 831         (pa_opcode): Revise ordering rules.  Add/move strict pa10 variants
 832         before corresponding pa11 opcodes.  Add strict pa10 register-immediate
 833         entries for "fdc".
 834
 835 2005-09-30  Catherine Moore  <clm@cm00re.com>
 836
 837         * bfin.h: New file.
 838
 839 2005-09-24  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 840
 841         * hppa.h (pa_opcodes): Add new "fdc" and "fic" opcode entries.
 842
 843 2005-09-06  Chao-ying Fu  <fu@mips.com>
 844
 845         * mips.h (OP_SH_MT_U, OP_MASK_MT_U, OP_SH_MT_H, OP_MASK_MT_H,
 846         OP_SH_MTACC_T, OP_MASK_MTACC_T, OP_SH_MTACC_D, OP_MASK_MTACC_D): New
 847         define.
 848         Document !, $, *, &, g, +t, +T operand formats for MT instructions.
 849         (INSN_ASE_MASK): Update to include INSN_MT.
 850         (INSN_MT): New define for MT ASE.
 851
 852 2005-08-25  Chao-ying Fu  <fu@mips.com>
 853
 854         * mips.h (OP_SH_DSPACC, OP_MASK_DSPACC, OP_SH_DSPACC_S,
 855         OP_MASK_DSPACC_S, OP_SH_DSPSFT, OP_MASK_DSPSFT, OP_SH_DSPSFT_7,
 856         OP_MASK_DSPSFT_7, OP_SH_SA3, OP_MASK_SA3, OP_SH_SA4, OP_MASK_SA4,
 857         OP_SH_IMM8, OP_MASK_IMM8, OP_SH_IMM10, OP_MASK_IMM10, OP_SH_WRDSP,
 858         OP_MASK_WRDSP, OP_SH_RDDSP, OP_MASK_RDDSP): New define.
 859         Document 3, 4, 5, 6, 7, 8, 9, 0, :, ', @ operand formats for DSP
 860         instructions.
 861         (INSN_DSP): New define for DSP ASE.
 862
 863 2005-08-18  Alan Modra  <amodra@bigpond.net.au>
 864
 865         * a29k.h: Delete.
 866
 867 2005-08-15  Daniel Jacobowitz  <dan@codesourcery.com>
 868
 869         * ppc.h (PPC_OPCODE_E300): Define.
 870
 871 2005-08-12 Martin Schwidefsky  <schwidefsky@de.ibm.com>
 872
 873         * s390.h (s390_opcode_cpu_val): Add enum for cpu type z9-109.
 874
 875 2005-07-28  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 876
 877         PR gas/336
 878         * hppa.h (pa_opcodes): Allow 0 immediates in PA 2.0 variants of pdtlb
 879         and pitlb.
 880
 881 2005-07-27  Jan Beulich  <jbeulich@novell.com>
 882
 883         * i386.h (i386_optab): Add comment to movd. Use LongMem for all
 884         movd-s. Add NoRex64 to movq-s dealing only with mmx or xmm registers.
 885         Add movq-s as 64-bit variants of movd-s.
 886
 887 2005-07-18  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 888
 889         * hppa.h: Fix punctuation in comment.
 890
 891         * hppa.h (pa_opcode):  Add rules for opcode ordering.  Check first for
 892         implicit space-register addressing.  Set space-register bits on opcodes
 893         using implicit space-register addressing.  Add various missing pa20
 894         long-immediate opcodes.  Remove various opcodes using implicit 3-bit
 895         space-register addressing.  Use "fE" instead of "fe" in various
 896         fstw opcodes.
 897
 898 2005-07-18  Jan Beulich  <jbeulich@novell.com>
 899
 900         * i386.h (i386_optab): Operands of aam and aad are unsigned.
 901
 902 2007-07-15  H.J. Lu <hongjiu.lu@intel.com>
 903
 904         * i386.h (i386_optab): Support Intel VMX Instructions.
 905
 906 2005-07-10  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 907
 908         * hppa.h (pa_opcode): Don't set FLAG_STRICT in pa10 loads and stores.
 909
 910 2005-07-05  Jan Beulich  <jbeulich@novell.com>
 911
 912         * i386.h (i386_optab): Add new insns.
 913
 914 2005-07-01  Nick Clifton  <nickc@redhat.com>
 915
 916         * sparc.h: Add typedefs to structure declarations.
 917
 918 2005-06-20  H.J. Lu  <hongjiu.lu@intel.com>
 919
 920         PR 1013
 921         * i386.h (i386_optab): Update comments for 64bit addressing on
 922         mov. Allow 64bit addressing for mov and movq.
 923
 924 2005-06-11  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 925
 926         * hppa.h (pa_opcodes): Use cM and cX instead of cm and cx,
 927         respectively, in various floating-point load and store patterns.
 928
 929 2005-05-23  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>
 930
 931         * hppa.h (FLAG_STRICT): Correct comment.
 932         (pa_opcodes): Update load and store entries to allow both PA 1.X and
 933         PA 2.0 mneumonics when equivalent.  Entries with cache control
 934         completers now require PA 1.1.  Adjust whitespace.
 935
 936 2005-05-19  Anton Blanchard  <anton@samba.org>
 937
 938         * ppc.h (PPC_OPCODE_POWER5): Define.
 939
 940 2005-05-10  Nick Clifton  <nickc@redhat.com>
 941
 942         * Update the address and phone number of the FSF organization in
 943         the GPL notices in the following files:
 944         a29k.h, alpha.h, arc.h, arm.h, avr.h, cgen.h, convex.h, cris.h,
 945         crx.h, d10v.h, d30v.h, dlx.h, h8300.h, hppa.h, i370.h, i386.h,
 946         i860.h, i960.h, m68hc11.h, m68k.h, m88k.h, maxq.h, mips.h, mmix.h,
 947         mn10200.h, mn10300.h, msp430.h, np1.h, ns32k.h, or32.h, pdp11.h,
 948         pj.h, pn.h, ppc.h, pyr.h, s390.h, sparc.h, tic30.h, tic4x.h,
 949         tic54x.h, tic80.h, v850.h, vax.h
 950
 951 2005-05-09  Jan Beulich  <jbeulich@novell.com>
 952
 953         * i386.h (i386_optab): Add ht and hnt.
 954
 955 2005-04-18  Mark Kettenis  <kettenis@gnu.org>
 956
 957         * i386.h: Insert hyphens into selected VIA PadLock extensions.
 958         Add xcrypt-ctr.  Provide aliases without hyphens.
 959
 960 2005-04-13  H.J. Lu  <hongjiu.lu@intel.com>
 961
 962         Moved from ../ChangeLog
 963
 964         2005-04-12  Paul Brook  <paul@codesourcery.com>
 965         * m88k.h: Rename psr macros to avoid conflicts.
 966
 967         2005-03-12  Zack Weinberg  <zack@codesourcery.com>
 968         * arm.h: Adjust comments for ARM_EXT_V4T and ARM_EXT_V5T.
 969         Add ARM_EXT_V6T2, ARM_ARCH_V6T2, ARM_ARCH_V6KT2, ARM_ARCH_V6ZT2,
 970         and ARM_ARCH_V6ZKT2.
 971
 972         2004-11-29  Tomer Levi  <Tomer.Levi@nsc.com>
 973         * crx.h (enum operand_type): Rename rbase_cst4 to rbase_dispu4.
 974         Remove redundant instruction types.
 975         (struct argument): X_op - new field.
 976         (struct cst4_entry): Remove.
 977         (no_op_insn): Declare.
 978
 979         2004-11-05  Tomer Levi  <Tomer.Levi@nsc.com>
 980         * crx.h (enum argtype): Rename types, remove unused types.
 981
 982         2004-10-27  Tomer Levi  <Tomer.Levi@nsc.com>
 983         * crx.h (enum reg): Rearrange registers, remove 'ccfg' and `'pc'.
 984         (enum reg_type): Remove CRX_PC_REGTYPE, CRX_MTPR_REGTYPE.
 985         (enum operand_type): Rearrange operands, edit comments.
 986         replace us<N> with ui<N> for unsigned immediate.
 987         replace d<N> with disps<N>/dispu<N>/dispe<N> for signed/unsigned/escaped
 988         displacements (respectively).
 989         replace rbase_ridx_scl2_dispu<N> with rindex_disps<N> for register index.
 990         (instruction type): Add NO_TYPE_INS.
 991         (instruction flags): Add USER_REG, CST4MAP, NO_SP, NO_RPTR.
 992         (operand_entry): New field - 'flags'.
 993         (operand flags): New.
 994
 995         2004-10-21  Tomer Levi  <Tomer.Levi@nsc.com>
 996         * crx.h (operand_type): Remove redundant types i3, i4,
 997         i5, i8, i12.
 998         Add new unsigned immediate types us3, us4, us5, us16.
 999
1000 2005-04-12  Mark Kettenis  <kettenis@gnu.org>
1001
1002         * i386.h (i386_optab): Mark VIA PadLock instructions as ImmExt and
1003         adjust them accordingly.
1004
1005 2005-04-01  Jan Beulich  <jbeulich@novell.com>
1006
1007         * i386.h (i386_optab): Add rdtscp.
1008
1009 2005-03-29  H.J. Lu  <hongjiu.lu@intel.com>
1010
1011         * i386.h (i386_optab): Don't allow the `l' suffix for moving
1012         between memory and segment register. Allow movq for moving between
1013         general-purpose register and segment register.
1014
1015 2005-02-09  Jan Beulich  <jbeulich@novell.com>
1016
1017         PR gas/707
1018         * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and
1019         FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and
1020         fnstsw.
1021
1022 2006-02-07  Nathan Sidwell  <nathan@codesourcery.com>
1023
1024         * m68k.h (m68008, m68ec030, m68882): Remove.
1025         (m68k_mask): New.
1026         (cpu_m68k, cpu_cf): New.
1027         (mcf5200, mcf5206e, mcf521x, mcf5249, mcf528x, mcf5307, mcf5407,
1028         mcf5470, mcf5480): Rename to cpu_<foo>. Add m680x0 variants.
1029
1030 2005-01-25  Alexandre Oliva  <aoliva@redhat.com>
1031
1032         2004-11-10  Alexandre Oliva  <aoliva@redhat.com>
1033         * cgen.h (enum cgen_parse_operand_type): Add
1034         CGEN_PARSE_OPERAND_SYMBOLIC.
1035
1036 2005-01-21  Fred Fish  <fnf@specifixinc.com>
1037
1038         * mips.h: Change INSN_ALIAS to INSN2_ALIAS.
1039         Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
1040         Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
1041
1042 2005-01-19  Fred Fish  <fnf@specifixinc.com>
1043
1044         * mips.h (struct mips_opcode): Add new pinfo2 member.
1045         (INSN_ALIAS): New define for opcode table entries that are
1046         specific instances of another entry, such as 'move' for an 'or'
1047         with a zero operand.
1048         (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2.
1049         (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4.
1050
1051 2004-12-09  Ian Lance Taylor  <ian@wasabisystems.com>
1052
1053         * mips.h (CPU_RM9000): Define.
1054         (OPCODE_IS_MEMBER): Handle CPU_RM9000.
1055
1056 2004-11-25 Jan Beulich  <jbeulich@novell.com>
1057
1058         * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
1059         to/from test registers are illegal in 64-bit mode. Add missing
1060         NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
1061         (previously one had to explicitly encode a rex64 prefix). Re-enable
1062         lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
1063         support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
1064
1065 2004-11-23 Jan Beulich  <jbeulich@novell.com>
1066
1067         * i386.h (i386_optab): paddq and psubq, even in their MMX form, are
1068         available only with SSE2. Change the MMX additions introduced by SSE
1069         and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A
1070         instructions by their now designated identifier (since combining i686
1071         and 3DNow! does not really imply 3DNow!A).
1072
1073 2004-11-19  Alan Modra  <amodra@bigpond.net.au>
1074
1075         * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes,
1076         struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c.
1077
1078 2004-11-08  Inderpreet Singh   <inderpreetb@nioda.hcltech.com>
1079             Vineet Sharma      <vineets@noida.hcltech.com>
1080
1081         * maxq.h: New file: Disassembly information for the maxq port.
1082
1083 2004-11-05  H.J. Lu  <hongjiu.lu@intel.com>
1084
1085         * i386.h (i386_optab): Put back "movzb".
1086
1087 2004-11-04  Hans-Peter Nilsson  <hp@axis.com>
1088
1089         * cris.h (enum cris_insn_version_usage): Tweak formatting and
1090         comments.  Remove member cris_ver_sim.  Add members
1091         cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10,
1092         cris_ver_v8_10, cris_ver_v10, cris_ver_v10p.
1093         (struct cris_support_reg, struct cris_cond15): New types.
1094         (cris_conds15): Declare.
1095         (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON)
1096         (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS)
1097         (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros.
1098         (NOP_Z_BITS): Define in terms of NOP_OPCODE.
1099         (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and
1100         SIZE_FIELD_UNSIGNED.
1101
1102 2004-11-04 Jan Beulich  <jbeulich@novell.com>
1103
1104         * i386.h (sldx_Suf): Remove.
1105         (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize.
1106         (q_FP): Define, implying no REX64.
1107         (x_FP, sl_FP): Imply FloatMF.
1108         (i386_optab): Split reg and mem forms of moving from segment registers
1109         so that the memory forms can ignore the 16-/32-bit operand size
1110         distinction. Adjust a few others for Intel mode. Remove *FP uses from
1111         all non-floating-point instructions. Unite 32- and 64-bit forms of
1112         movsx, movzx, and movd. Adjust floating point operations for the above
1113         changes to the *FP macros. Add DefaultSize to floating point control
1114         insns operating on larger memory ranges. Remove left over comments
1115         hinting at certain insns being Intel-syntax ones where the ones
1116         actually meant are already gone.
1117
1118 2004-10-07  Tomer Levi  <Tomer.Levi@nsc.com>
1119
1120         * crx.h: Add COPS_REG_INS - Coprocessor Special register
1121         instruction type.
1122
1123 2004-09-30  Paul Brook  <paul@codesourcery.com>
1124
1125         * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
1126         (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define.
1127
1128 2004-09-11  Theodore A. Roth  <troth@openavr.org>
1129
1130         * avr.h: Add support for
1131         atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128.
1132
1133 2004-09-09  Segher Boessenkool  <segher@kernel.crashing.org>
1134
1135         * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment.
1136
1137 2004-08-24  Dmitry Diky  <diwil@spec.ru>
1138
1139         * msp430.h (msp430_opc): Add new instructions.
1140         (msp430_rcodes): Declare new instructions.
1141         (msp430_hcodes): Likewise..
1142
1143 2004-08-13  Nick Clifton  <nickc@redhat.com>
1144
1145         PR/301
1146         * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX
1147         processors.
1148
1149 2004-08-30  Michal Ludvig  <mludvig@suse.cz>
1150
1151         * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns.
1152
1153 2004-07-22  H.J. Lu  <hongjiu.lu@intel.com>
1154
1155         * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints.
1156
1157 2004-07-21  Jan Beulich  <jbeulich@novell.com>
1158
1159         * i386.h: Adjust instruction descriptions to better match the
1160         specification.
1161
1162 2004-07-16  Richard Earnshaw  <rearnsha@arm.com>
1163
1164         * arm.h: Remove all old content.  Replace with architecture defines
1165         from gas/config/tc-arm.c.
1166
1167 2004-07-09  Andreas Schwab  <schwab@suse.de>
1168
1169         * m68k.h: Fix comment.
1170
1171 2004-07-07  Tomer Levi  <Tomer.Levi@nsc.com>
1172
1173         * crx.h: New file.
1174
1175 2004-06-24  Alan Modra  <amodra@bigpond.net.au>
1176
1177         * i386.h (i386_optab): Remove fildd, fistpd and fisttpd.
1178
1179 2004-05-24  Peter Barada  <peter@the-baradas.com>
1180
1181         * m68k.h: Add 'size' to m68k_opcode.
1182
1183 2004-05-05  Peter Barada  <peter@the-baradas.com>
1184
1185         * m68k.h: Switch from ColdFire chip name to core variant.
1186
1187 2004-04-22  Peter Barada  <peter@the-baradas.com>
1188
1189         * m68k.h: Add mcfmac/mcfemac definitions.  Update operand
1190         descriptions for new EMAC cases.
1191         Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly
1192         handle Motorola MAC syntax.
1193         Allow disassembly of ColdFire V4e object files.
1194
1195 2004-03-16  Alan Modra  <amodra@bigpond.net.au>
1196
1197         * ppc.h (PPC_OPERAND_GPR_0): Define.  Bump other operand defines.
1198
1199 2004-03-12  Jakub Jelinek  <jakub@redhat.com>
1200
1201         * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit.
1202
1203 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1204
1205         * i386.h (i386_optab): Added xstore as an alias for xstorerng.
1206
1207 2004-03-12  Michal Ludvig  <mludvig@suse.cz>
1208
1209         * i386.h (i386_optab): Added xstore/xcrypt insns.
1210
1211 2004-02-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1212
1213         * h8300.h (32bit ldc/stc): Add relaxing support.
1214
1215 2004-01-12  Anil Paranjpe  <anilp1@KPITCummins.com>
1216
1217         * h8300.h (BITOP): Pass MEMRELAX flag.
1218
1219 2004-01-09  Anil Paranjpe  <anilp1@KPITCummins.com>
1220
1221         * h8300.h (BITOP): Dissallow operations on @aa:16 and @aa:32
1222         except for the H8S.
1223
1224 For older changes see ChangeLog-9103
1225 \f
1226 Local Variables:
1227 mode: change-log
1228 left-margin: 8
1229 fill-column: 74
1230 version-control: never
1231 End: