1 /* AArch64 assembler/disassembler support.
3 Copyright (C) 2009-2016 Free Software Foundation, Inc.
4 Contributed by ARM Ltd.
6 This file is part of GNU Binutils.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
22 #ifndef OPCODE_AARCH64_H
23 #define OPCODE_AARCH64_H
26 #include "bfd_stdint.h"
34 /* The offset for pc-relative addressing is currently defined to be 0. */
35 #define AARCH64_PCREL_OFFSET 0
37 typedef uint32_t aarch64_insn
;
39 /* The following bitmasks control CPU features. */
40 #define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
41 #define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
42 #define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
43 #define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
44 #define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
45 #define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
46 #define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
47 #define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
48 #define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
49 #define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
50 #define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
51 #define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
52 #define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
53 #define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
55 /* Architectures are the sum of the base and extensions. */
56 #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
58 | AARCH64_FEATURE_SIMD)
59 #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
61 | AARCH64_FEATURE_SIMD \
62 | AARCH64_FEATURE_CRC \
63 | AARCH64_FEATURE_V8_1 \
64 | AARCH64_FEATURE_LSE \
65 | AARCH64_FEATURE_PAN \
66 | AARCH64_FEATURE_LOR \
67 | AARCH64_FEATURE_RDMA)
68 #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
69 AARCH64_FEATURE_V8_2 \
70 | AARCH64_FEATURE_F16 \
71 | AARCH64_FEATURE_RAS \
72 | AARCH64_FEATURE_FP \
73 | AARCH64_FEATURE_SIMD \
74 | AARCH64_FEATURE_CRC \
75 | AARCH64_FEATURE_V8_1 \
76 | AARCH64_FEATURE_LSE \
77 | AARCH64_FEATURE_PAN \
78 | AARCH64_FEATURE_LOR \
79 | AARCH64_FEATURE_RDMA)
81 #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
82 #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
84 /* CPU-specific features. */
85 typedef unsigned long aarch64_feature_set
;
87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
88 ((~(CPU) & (FEAT)) == 0)
90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
91 (((CPU) & (FEAT)) != 0)
93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
94 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
99 (TARG) = (F1) | (F2); \
103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
106 (TARG) = (F1) &~ (F2); \
110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
112 enum aarch64_operand_class
114 AARCH64_OPND_CLASS_NIL
,
115 AARCH64_OPND_CLASS_INT_REG
,
116 AARCH64_OPND_CLASS_MODIFIED_REG
,
117 AARCH64_OPND_CLASS_FP_REG
,
118 AARCH64_OPND_CLASS_SIMD_REG
,
119 AARCH64_OPND_CLASS_SIMD_ELEMENT
,
120 AARCH64_OPND_CLASS_SISD_REG
,
121 AARCH64_OPND_CLASS_SIMD_REGLIST
,
122 AARCH64_OPND_CLASS_CP_REG
,
123 AARCH64_OPND_CLASS_SVE_REG
,
124 AARCH64_OPND_CLASS_PRED_REG
,
125 AARCH64_OPND_CLASS_ADDRESS
,
126 AARCH64_OPND_CLASS_IMMEDIATE
,
127 AARCH64_OPND_CLASS_SYSTEM
,
128 AARCH64_OPND_CLASS_COND
,
131 /* Operand code that helps both parsing and coding.
132 Keep AARCH64_OPERANDS synced. */
136 AARCH64_OPND_NIL
, /* no operand---MUST BE FIRST!*/
138 AARCH64_OPND_Rd
, /* Integer register as destination. */
139 AARCH64_OPND_Rn
, /* Integer register as source. */
140 AARCH64_OPND_Rm
, /* Integer register as source. */
141 AARCH64_OPND_Rt
, /* Integer register used in ld/st instructions. */
142 AARCH64_OPND_Rt2
, /* Integer register used in ld/st pair instructions. */
143 AARCH64_OPND_Rs
, /* Integer register used in ld/st exclusive. */
144 AARCH64_OPND_Ra
, /* Integer register used in ddp_3src instructions. */
145 AARCH64_OPND_Rt_SYS
, /* Integer register used in system instructions. */
147 AARCH64_OPND_Rd_SP
, /* Integer Rd or SP. */
148 AARCH64_OPND_Rn_SP
, /* Integer Rn or SP. */
149 AARCH64_OPND_PAIRREG
, /* Paired register operand. */
150 AARCH64_OPND_Rm_EXT
, /* Integer Rm extended. */
151 AARCH64_OPND_Rm_SFT
, /* Integer Rm shifted. */
153 AARCH64_OPND_Fd
, /* Floating-point Fd. */
154 AARCH64_OPND_Fn
, /* Floating-point Fn. */
155 AARCH64_OPND_Fm
, /* Floating-point Fm. */
156 AARCH64_OPND_Fa
, /* Floating-point Fa. */
157 AARCH64_OPND_Ft
, /* Floating-point Ft. */
158 AARCH64_OPND_Ft2
, /* Floating-point Ft2. */
160 AARCH64_OPND_Sd
, /* AdvSIMD Scalar Sd. */
161 AARCH64_OPND_Sn
, /* AdvSIMD Scalar Sn. */
162 AARCH64_OPND_Sm
, /* AdvSIMD Scalar Sm. */
164 AARCH64_OPND_Vd
, /* AdvSIMD Vector Vd. */
165 AARCH64_OPND_Vn
, /* AdvSIMD Vector Vn. */
166 AARCH64_OPND_Vm
, /* AdvSIMD Vector Vm. */
167 AARCH64_OPND_VdD1
, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
168 AARCH64_OPND_VnD1
, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
169 AARCH64_OPND_Ed
, /* AdvSIMD Vector Element Vd. */
170 AARCH64_OPND_En
, /* AdvSIMD Vector Element Vn. */
171 AARCH64_OPND_Em
, /* AdvSIMD Vector Element Vm. */
172 AARCH64_OPND_LVn
, /* AdvSIMD Vector register list used in e.g. TBL. */
173 AARCH64_OPND_LVt
, /* AdvSIMD Vector register list used in ld/st. */
174 AARCH64_OPND_LVt_AL
, /* AdvSIMD Vector register list for loading single
175 structure to all lanes. */
176 AARCH64_OPND_LEt
, /* AdvSIMD Vector Element list. */
178 AARCH64_OPND_Cn
, /* Co-processor register in CRn field. */
179 AARCH64_OPND_Cm
, /* Co-processor register in CRm field. */
181 AARCH64_OPND_IDX
, /* AdvSIMD EXT index operand. */
182 AARCH64_OPND_IMM_VLSL
,/* Immediate for shifting vector registers left. */
183 AARCH64_OPND_IMM_VLSR
,/* Immediate for shifting vector registers right. */
184 AARCH64_OPND_SIMD_IMM
,/* AdvSIMD modified immediate without shift. */
185 AARCH64_OPND_SIMD_IMM_SFT
, /* AdvSIMD modified immediate with shift. */
186 AARCH64_OPND_SIMD_FPIMM
,/* AdvSIMD 8-bit fp immediate. */
187 AARCH64_OPND_SHLL_IMM
,/* Immediate shift for AdvSIMD SHLL instruction
189 AARCH64_OPND_IMM0
, /* Immediate for #0. */
190 AARCH64_OPND_FPIMM0
, /* Immediate for #0.0. */
191 AARCH64_OPND_FPIMM
, /* Floating-point Immediate. */
192 AARCH64_OPND_IMMR
, /* Immediate #<immr> in e.g. BFM. */
193 AARCH64_OPND_IMMS
, /* Immediate #<imms> in e.g. BFM. */
194 AARCH64_OPND_WIDTH
, /* Immediate #<width> in e.g. BFI. */
195 AARCH64_OPND_IMM
, /* Immediate. */
196 AARCH64_OPND_UIMM3_OP1
,/* Unsigned 3-bit immediate in the op1 field. */
197 AARCH64_OPND_UIMM3_OP2
,/* Unsigned 3-bit immediate in the op2 field. */
198 AARCH64_OPND_UIMM4
, /* Unsigned 4-bit immediate in the CRm field. */
199 AARCH64_OPND_UIMM7
, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
200 AARCH64_OPND_BIT_NUM
, /* Immediate. */
201 AARCH64_OPND_EXCEPTION
,/* imm16 operand in exception instructions. */
202 AARCH64_OPND_CCMP_IMM
,/* Immediate in conditional compare instructions. */
203 AARCH64_OPND_SIMM5
, /* 5-bit signed immediate in the imm5 field. */
204 AARCH64_OPND_NZCV
, /* Flag bit specifier giving an alternative value for
205 each condition flag. */
207 AARCH64_OPND_LIMM
, /* Logical Immediate. */
208 AARCH64_OPND_AIMM
, /* Arithmetic immediate. */
209 AARCH64_OPND_HALF
, /* #<imm16>{, LSL #<shift>} operand in move wide. */
210 AARCH64_OPND_FBITS
, /* FP #<fbits> operand in e.g. SCVTF */
211 AARCH64_OPND_IMM_MOV
, /* Immediate operand for the MOV alias. */
213 AARCH64_OPND_COND
, /* Standard condition as the last operand. */
214 AARCH64_OPND_COND1
, /* Same as the above, but excluding AL and NV. */
216 AARCH64_OPND_ADDR_ADRP
, /* Memory address for ADRP */
217 AARCH64_OPND_ADDR_PCREL14
, /* 14-bit PC-relative address for e.g. TBZ. */
218 AARCH64_OPND_ADDR_PCREL19
, /* 19-bit PC-relative address for e.g. LDR. */
219 AARCH64_OPND_ADDR_PCREL21
, /* 21-bit PC-relative address for e.g. ADR. */
220 AARCH64_OPND_ADDR_PCREL26
, /* 26-bit PC-relative address for e.g. BL. */
222 AARCH64_OPND_ADDR_SIMPLE
, /* Address of ld/st exclusive. */
223 AARCH64_OPND_ADDR_REGOFF
, /* Address of register offset. */
224 AARCH64_OPND_ADDR_SIMM7
, /* Address of signed 7-bit immediate. */
225 AARCH64_OPND_ADDR_SIMM9
, /* Address of signed 9-bit immediate. */
226 AARCH64_OPND_ADDR_SIMM9_2
, /* Same as the above, but the immediate is
227 negative or unaligned and there is
228 no writeback allowed. This operand code
229 is only used to support the programmer-
230 friendly feature of using LDR/STR as the
231 the mnemonic name for LDUR/STUR instructions
232 wherever there is no ambiguity. */
233 AARCH64_OPND_ADDR_UIMM12
, /* Address of unsigned 12-bit immediate. */
234 AARCH64_OPND_SIMD_ADDR_SIMPLE
,/* Address of ld/st multiple structures. */
235 AARCH64_OPND_SIMD_ADDR_POST
, /* Address of ld/st multiple post-indexed. */
237 AARCH64_OPND_SYSREG
, /* System register operand. */
238 AARCH64_OPND_PSTATEFIELD
, /* PSTATE field name operand. */
239 AARCH64_OPND_SYSREG_AT
, /* System register <at_op> operand. */
240 AARCH64_OPND_SYSREG_DC
, /* System register <dc_op> operand. */
241 AARCH64_OPND_SYSREG_IC
, /* System register <ic_op> operand. */
242 AARCH64_OPND_SYSREG_TLBI
, /* System register <tlbi_op> operand. */
243 AARCH64_OPND_BARRIER
, /* Barrier operand. */
244 AARCH64_OPND_BARRIER_ISB
, /* Barrier operand for ISB. */
245 AARCH64_OPND_PRFOP
, /* Prefetch operation. */
246 AARCH64_OPND_BARRIER_PSB
, /* Barrier operand for PSB. */
248 AARCH64_OPND_SVE_ADDR_RI_S4xVL
, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
249 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
250 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
251 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
252 AARCH64_OPND_SVE_ADDR_RI_S6xVL
, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
253 AARCH64_OPND_SVE_ADDR_RI_S9xVL
, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
254 AARCH64_OPND_SVE_ADDR_RI_U6
, /* SVE [<Xn|SP>, #<uimm6>]. */
255 AARCH64_OPND_SVE_ADDR_RI_U6x2
, /* SVE [<Xn|SP>, #<uimm6>*2]. */
256 AARCH64_OPND_SVE_ADDR_RI_U6x4
, /* SVE [<Xn|SP>, #<uimm6>*4]. */
257 AARCH64_OPND_SVE_ADDR_RI_U6x8
, /* SVE [<Xn|SP>, #<uimm6>*8]. */
258 AARCH64_OPND_SVE_ADDR_RR
, /* SVE [<Xn|SP>, <Xm|XZR>]. */
259 AARCH64_OPND_SVE_ADDR_RR_LSL1
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
260 AARCH64_OPND_SVE_ADDR_RR_LSL2
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
261 AARCH64_OPND_SVE_ADDR_RR_LSL3
, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
262 AARCH64_OPND_SVE_ADDR_RX
, /* SVE [<Xn|SP>, <Xm>]. */
263 AARCH64_OPND_SVE_ADDR_RX_LSL1
, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
264 AARCH64_OPND_SVE_ADDR_RX_LSL2
, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
265 AARCH64_OPND_SVE_ADDR_RX_LSL3
, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
266 AARCH64_OPND_SVE_ADDR_RZ
, /* SVE [<Xn|SP>, Zm.D]. */
267 AARCH64_OPND_SVE_ADDR_RZ_LSL1
, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
268 AARCH64_OPND_SVE_ADDR_RZ_LSL2
, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
269 AARCH64_OPND_SVE_ADDR_RZ_LSL3
, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
270 AARCH64_OPND_SVE_ADDR_RZ_XTW_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
271 Bit 14 controls S/U choice. */
272 AARCH64_OPND_SVE_ADDR_RZ_XTW_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
273 Bit 22 controls S/U choice. */
274 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
275 Bit 14 controls S/U choice. */
276 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
277 Bit 22 controls S/U choice. */
278 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
279 Bit 14 controls S/U choice. */
280 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
281 Bit 22 controls S/U choice. */
282 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
283 Bit 14 controls S/U choice. */
284 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
285 Bit 22 controls S/U choice. */
286 AARCH64_OPND_SVE_ADDR_ZI_U5
, /* SVE [Zn.<T>, #<uimm5>]. */
287 AARCH64_OPND_SVE_ADDR_ZI_U5x2
, /* SVE [Zn.<T>, #<uimm5>*2]. */
288 AARCH64_OPND_SVE_ADDR_ZI_U5x4
, /* SVE [Zn.<T>, #<uimm5>*4]. */
289 AARCH64_OPND_SVE_ADDR_ZI_U5x8
, /* SVE [Zn.<T>, #<uimm5>*8]. */
290 AARCH64_OPND_SVE_ADDR_ZZ_LSL
, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
291 AARCH64_OPND_SVE_ADDR_ZZ_SXTW
, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
292 AARCH64_OPND_SVE_ADDR_ZZ_UXTW
, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
293 AARCH64_OPND_SVE_AIMM
, /* SVE unsigned arithmetic immediate. */
294 AARCH64_OPND_SVE_ASIMM
, /* SVE signed arithmetic immediate. */
295 AARCH64_OPND_SVE_FPIMM8
, /* SVE 8-bit floating-point immediate. */
296 AARCH64_OPND_SVE_I1_HALF_ONE
, /* SVE choice between 0.5 and 1.0. */
297 AARCH64_OPND_SVE_I1_HALF_TWO
, /* SVE choice between 0.5 and 2.0. */
298 AARCH64_OPND_SVE_I1_ZERO_ONE
, /* SVE choice between 0.0 and 1.0. */
299 AARCH64_OPND_SVE_INV_LIMM
, /* SVE inverted logical immediate. */
300 AARCH64_OPND_SVE_LIMM
, /* SVE logical immediate. */
301 AARCH64_OPND_SVE_LIMM_MOV
, /* SVE logical immediate for MOV. */
302 AARCH64_OPND_SVE_PATTERN
, /* SVE vector pattern enumeration. */
303 AARCH64_OPND_SVE_PATTERN_SCALED
, /* Likewise, with additional MUL factor. */
304 AARCH64_OPND_SVE_PRFOP
, /* SVE prefetch operation. */
305 AARCH64_OPND_SVE_Pd
, /* SVE p0-p15 in Pd. */
306 AARCH64_OPND_SVE_Pg3
, /* SVE p0-p7 in Pg. */
307 AARCH64_OPND_SVE_Pg4_5
, /* SVE p0-p15 in Pg, bits [8,5]. */
308 AARCH64_OPND_SVE_Pg4_10
, /* SVE p0-p15 in Pg, bits [13,10]. */
309 AARCH64_OPND_SVE_Pg4_16
, /* SVE p0-p15 in Pg, bits [19,16]. */
310 AARCH64_OPND_SVE_Pm
, /* SVE p0-p15 in Pm. */
311 AARCH64_OPND_SVE_Pn
, /* SVE p0-p15 in Pn. */
312 AARCH64_OPND_SVE_Pt
, /* SVE p0-p15 in Pt. */
313 AARCH64_OPND_SVE_Rm
, /* Integer Rm or ZR, alt. SVE position. */
314 AARCH64_OPND_SVE_Rn_SP
, /* Integer Rn or SP, alt. SVE position. */
315 AARCH64_OPND_SVE_SHLIMM_PRED
, /* SVE shift left amount (predicated). */
316 AARCH64_OPND_SVE_SHLIMM_UNPRED
, /* SVE shift left amount (unpredicated). */
317 AARCH64_OPND_SVE_SHRIMM_PRED
, /* SVE shift right amount (predicated). */
318 AARCH64_OPND_SVE_SHRIMM_UNPRED
, /* SVE shift right amount (unpredicated). */
319 AARCH64_OPND_SVE_SIMM5
, /* SVE signed 5-bit immediate. */
320 AARCH64_OPND_SVE_SIMM5B
, /* SVE secondary signed 5-bit immediate. */
321 AARCH64_OPND_SVE_SIMM6
, /* SVE signed 6-bit immediate. */
322 AARCH64_OPND_SVE_SIMM8
, /* SVE signed 8-bit immediate. */
323 AARCH64_OPND_SVE_UIMM3
, /* SVE unsigned 3-bit immediate. */
324 AARCH64_OPND_SVE_UIMM7
, /* SVE unsigned 7-bit immediate. */
325 AARCH64_OPND_SVE_UIMM8
, /* SVE unsigned 8-bit immediate. */
326 AARCH64_OPND_SVE_UIMM8_53
, /* SVE split unsigned 8-bit immediate. */
327 AARCH64_OPND_SVE_VZn
, /* Scalar SIMD&FP register in Zn field. */
328 AARCH64_OPND_SVE_Vd
, /* Scalar SIMD&FP register in Vd. */
329 AARCH64_OPND_SVE_Vm
, /* Scalar SIMD&FP register in Vm. */
330 AARCH64_OPND_SVE_Vn
, /* Scalar SIMD&FP register in Vn. */
331 AARCH64_OPND_SVE_Za_5
, /* SVE vector register in Za, bits [9,5]. */
332 AARCH64_OPND_SVE_Za_16
, /* SVE vector register in Za, bits [20,16]. */
333 AARCH64_OPND_SVE_Zd
, /* SVE vector register in Zd. */
334 AARCH64_OPND_SVE_Zm_5
, /* SVE vector register in Zm, bits [9,5]. */
335 AARCH64_OPND_SVE_Zm_16
, /* SVE vector register in Zm, bits [20,16]. */
336 AARCH64_OPND_SVE_Zn
, /* SVE vector register in Zn. */
337 AARCH64_OPND_SVE_Zn_INDEX
, /* Indexed SVE vector register, for DUP. */
338 AARCH64_OPND_SVE_ZnxN
, /* SVE vector register list in Zn. */
339 AARCH64_OPND_SVE_Zt
, /* SVE vector register in Zt. */
340 AARCH64_OPND_SVE_ZtxN
, /* SVE vector register list in Zt. */
343 /* Qualifier constrains an operand. It either specifies a variant of an
344 operand type or limits values available to an operand type.
346 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
348 enum aarch64_opnd_qualifier
350 /* Indicating no further qualification on an operand. */
351 AARCH64_OPND_QLF_NIL
,
353 /* Qualifying an operand which is a general purpose (integer) register;
354 indicating the operand data size or a specific register. */
355 AARCH64_OPND_QLF_W
, /* Wn, WZR or WSP. */
356 AARCH64_OPND_QLF_X
, /* Xn, XZR or XSP. */
357 AARCH64_OPND_QLF_WSP
, /* WSP. */
358 AARCH64_OPND_QLF_SP
, /* SP. */
360 /* Qualifying an operand which is a floating-point register, a SIMD
361 vector element or a SIMD vector element list; indicating operand data
362 size or the size of each SIMD vector element in the case of a SIMD
364 These qualifiers are also used to qualify an address operand to
365 indicate the size of data element a load/store instruction is
367 They are also used for the immediate shift operand in e.g. SSHR. Such
368 a use is only for the ease of operand encoding/decoding and qualifier
369 sequence matching; such a use should not be applied widely; use the value
370 constraint qualifiers for immediate operands wherever possible. */
371 AARCH64_OPND_QLF_S_B
,
372 AARCH64_OPND_QLF_S_H
,
373 AARCH64_OPND_QLF_S_S
,
374 AARCH64_OPND_QLF_S_D
,
375 AARCH64_OPND_QLF_S_Q
,
377 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
378 register list; indicating register shape.
379 They are also used for the immediate shift operand in e.g. SSHR. Such
380 a use is only for the ease of operand encoding/decoding and qualifier
381 sequence matching; such a use should not be applied widely; use the value
382 constraint qualifiers for immediate operands wherever possible. */
383 AARCH64_OPND_QLF_V_8B
,
384 AARCH64_OPND_QLF_V_16B
,
385 AARCH64_OPND_QLF_V_2H
,
386 AARCH64_OPND_QLF_V_4H
,
387 AARCH64_OPND_QLF_V_8H
,
388 AARCH64_OPND_QLF_V_2S
,
389 AARCH64_OPND_QLF_V_4S
,
390 AARCH64_OPND_QLF_V_1D
,
391 AARCH64_OPND_QLF_V_2D
,
392 AARCH64_OPND_QLF_V_1Q
,
394 AARCH64_OPND_QLF_P_Z
,
395 AARCH64_OPND_QLF_P_M
,
397 /* Constraint on value. */
398 AARCH64_OPND_QLF_imm_0_7
,
399 AARCH64_OPND_QLF_imm_0_15
,
400 AARCH64_OPND_QLF_imm_0_31
,
401 AARCH64_OPND_QLF_imm_0_63
,
402 AARCH64_OPND_QLF_imm_1_32
,
403 AARCH64_OPND_QLF_imm_1_64
,
405 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
407 AARCH64_OPND_QLF_LSL
,
408 AARCH64_OPND_QLF_MSL
,
410 /* Special qualifier helping retrieve qualifier information during the
411 decoding time (currently not in use). */
412 AARCH64_OPND_QLF_RETRIEVE
,
415 /* Instruction class. */
417 enum aarch64_insn_class
472 ldst_imm9
, /* immpost or immpre */
491 /* Opcode enumerators. */
535 OP_MOV_IMM_LOG
, /* MOV alias for moving bitmask immediate. */
536 OP_MOV_IMM_WIDE
, /* MOV alias for moving wide immediate. */
537 OP_MOV_IMM_WIDEN
, /* MOV alias for moving wide immediate (negated). */
539 OP_MOV_V
, /* MOV alias for moving vector register. */
552 OP_BFC
, /* ARMv8.2. */
569 OP_FCVTXN_S
, /* Scalar version. */
578 OP_TOTAL_NUM
, /* Pseudo. */
581 /* Maximum number of operands an instruction can have. */
582 #define AARCH64_MAX_OPND_NUM 6
583 /* Maximum number of qualifier sequences an instruction can have. */
584 #define AARCH64_MAX_QLF_SEQ_NUM 10
585 /* Operand qualifier typedef; optimized for the size. */
586 typedef unsigned char aarch64_opnd_qualifier_t
;
587 /* Operand qualifier sequence typedef. */
588 typedef aarch64_opnd_qualifier_t \
589 aarch64_opnd_qualifier_seq_t
[AARCH64_MAX_OPND_NUM
];
591 /* FIXME: improve the efficiency. */
592 static inline bfd_boolean
593 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t
*qualifiers
)
596 for (i
= 0; i
< AARCH64_MAX_OPND_NUM
; ++i
)
597 if (qualifiers
[i
] != AARCH64_OPND_QLF_NIL
)
602 /* This structure holds information for a particular opcode. */
604 struct aarch64_opcode
606 /* The name of the mnemonic. */
609 /* The opcode itself. Those bits which will be filled in with
610 operands are zeroes. */
613 /* The opcode mask. This is used by the disassembler. This is a
614 mask containing ones indicating those bits which must match the
615 opcode field, and zeroes indicating those bits which need not
616 match (and are presumably filled in by operands). */
619 /* Instruction class. */
620 enum aarch64_insn_class iclass
;
622 /* Enumerator identifier. */
625 /* Which architecture variant provides this instruction. */
626 const aarch64_feature_set
*avariant
;
628 /* An array of operand codes. Each code is an index into the
629 operand table. They appear in the order which the operands must
630 appear in assembly code, and are terminated by a zero. */
631 enum aarch64_opnd operands
[AARCH64_MAX_OPND_NUM
];
633 /* A list of operand qualifier code sequence. Each operand qualifier
634 code qualifies the corresponding operand code. Each operand
635 qualifier sequence specifies a valid opcode variant and related
636 constraint on operands. */
637 aarch64_opnd_qualifier_seq_t qualifiers_list
[AARCH64_MAX_QLF_SEQ_NUM
];
639 /* Flags providing information about this instruction */
642 /* If nonzero, this operand and operand 0 are both registers and
643 are required to have the same register number. */
644 unsigned char tied_operand
;
646 /* If non-NULL, a function to verify that a given instruction is valid. */
647 bfd_boolean (* verifier
) (const struct aarch64_opcode
*, const aarch64_insn
);
650 typedef struct aarch64_opcode aarch64_opcode
;
652 /* Table describing all the AArch64 opcodes. */
653 extern aarch64_opcode aarch64_opcode_table
[];
656 #define F_ALIAS (1 << 0)
657 #define F_HAS_ALIAS (1 << 1)
658 /* Disassembly preference priority 1-3 (the larger the higher). If nothing
659 is specified, it is the priority 0 by default, i.e. the lowest priority. */
660 #define F_P1 (1 << 2)
661 #define F_P2 (2 << 2)
662 #define F_P3 (3 << 2)
663 /* Flag an instruction that is truly conditional executed, e.g. b.cond. */
664 #define F_COND (1 << 4)
665 /* Instruction has the field of 'sf'. */
666 #define F_SF (1 << 5)
667 /* Instruction has the field of 'size:Q'. */
668 #define F_SIZEQ (1 << 6)
669 /* Floating-point instruction has the field of 'type'. */
670 #define F_FPTYPE (1 << 7)
671 /* AdvSIMD scalar instruction has the field of 'size'. */
672 #define F_SSIZE (1 << 8)
673 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
675 /* Size of GPR operand in AdvSIMD instructions encoded in Q. */
676 #define F_GPRSIZE_IN_Q (1 << 10)
677 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
678 #define F_LDS_SIZE (1 << 11)
679 /* Optional operand; assume maximum of 1 operand can be optional. */
680 #define F_OPD0_OPT (1 << 12)
681 #define F_OPD1_OPT (2 << 12)
682 #define F_OPD2_OPT (3 << 12)
683 #define F_OPD3_OPT (4 << 12)
684 #define F_OPD4_OPT (5 << 12)
685 /* Default value for the optional operand when omitted from the assembly. */
686 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
687 /* Instruction that is an alias of another instruction needs to be
688 encoded/decoded by converting it to/from the real form, followed by
689 the encoding/decoding according to the rules of the real opcode.
690 This compares to the direct coding using the alias's information.
691 N.B. this flag requires F_ALIAS to be used together. */
692 #define F_CONV (1 << 20)
693 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
694 friendly pseudo instruction available only in the assembly code (thus will
695 not show up in the disassembly). */
696 #define F_PSEUDO (1 << 21)
697 /* Instruction has miscellaneous encoding/decoding rules. */
698 #define F_MISC (1 << 22)
699 /* Instruction has the field of 'N'; used in conjunction with F_SF. */
700 #define F_N (1 << 23)
701 /* Opcode dependent field. */
702 #define F_OD(X) (((X) & 0x7) << 24)
703 /* Instruction has the field of 'sz'. */
704 #define F_LSE_SZ (1 << 27)
705 /* Require an exact qualifier match, even for NIL qualifiers. */
706 #define F_STRICT (1ULL << 28)
707 /* Next bit is 29. */
709 static inline bfd_boolean
710 alias_opcode_p (const aarch64_opcode
*opcode
)
712 return (opcode
->flags
& F_ALIAS
) ? TRUE
: FALSE
;
715 static inline bfd_boolean
716 opcode_has_alias (const aarch64_opcode
*opcode
)
718 return (opcode
->flags
& F_HAS_ALIAS
) ? TRUE
: FALSE
;
721 /* Priority for disassembling preference. */
723 opcode_priority (const aarch64_opcode
*opcode
)
725 return (opcode
->flags
>> 2) & 0x3;
728 static inline bfd_boolean
729 pseudo_opcode_p (const aarch64_opcode
*opcode
)
731 return (opcode
->flags
& F_PSEUDO
) != 0lu ? TRUE
: FALSE
;
734 static inline bfd_boolean
735 optional_operand_p (const aarch64_opcode
*opcode
, unsigned int idx
)
737 return (((opcode
->flags
>> 12) & 0x7) == idx
+ 1)
741 static inline aarch64_insn
742 get_optional_operand_default_value (const aarch64_opcode
*opcode
)
744 return (opcode
->flags
>> 15) & 0x1f;
747 static inline unsigned int
748 get_opcode_dependent_value (const aarch64_opcode
*opcode
)
750 return (opcode
->flags
>> 24) & 0x7;
753 static inline bfd_boolean
754 opcode_has_special_coder (const aarch64_opcode
*opcode
)
756 return (opcode
->flags
& (F_SF
| F_LSE_SZ
| F_SIZEQ
| F_FPTYPE
| F_SSIZE
| F_T
757 | F_GPRSIZE_IN_Q
| F_LDS_SIZE
| F_MISC
| F_N
| F_COND
)) ? TRUE
761 struct aarch64_name_value_pair
767 extern const struct aarch64_name_value_pair aarch64_operand_modifiers
[];
768 extern const struct aarch64_name_value_pair aarch64_barrier_options
[16];
769 extern const struct aarch64_name_value_pair aarch64_prfops
[32];
770 extern const struct aarch64_name_value_pair aarch64_hint_options
[];
779 extern const aarch64_sys_reg aarch64_sys_regs
[];
780 extern const aarch64_sys_reg aarch64_pstatefields
[];
781 extern bfd_boolean
aarch64_sys_reg_deprecated_p (const aarch64_sys_reg
*);
782 extern bfd_boolean
aarch64_sys_reg_supported_p (const aarch64_feature_set
,
783 const aarch64_sys_reg
*);
784 extern bfd_boolean
aarch64_pstatefield_supported_p (const aarch64_feature_set
,
785 const aarch64_sys_reg
*);
792 } aarch64_sys_ins_reg
;
794 extern bfd_boolean
aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg
*);
796 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set
,
797 const aarch64_sys_ins_reg
*);
799 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic
[];
800 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc
[];
801 extern const aarch64_sys_ins_reg aarch64_sys_regs_at
[];
802 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi
[];
804 /* Shift/extending operator kinds.
805 N.B. order is important; keep aarch64_operand_modifiers synced. */
806 enum aarch64_modifier_kind
827 aarch64_extend_operator_p (enum aarch64_modifier_kind
);
829 enum aarch64_modifier_kind
830 aarch64_get_operand_modifier (const struct aarch64_name_value_pair
*);
835 /* A list of names with the first one as the disassembly preference;
836 terminated by NULL if fewer than 3. */
837 const char *names
[3];
841 extern const aarch64_cond aarch64_conds
[16];
843 const aarch64_cond
* get_cond_from_value (aarch64_insn value
);
844 const aarch64_cond
* get_inverted_cond (const aarch64_cond
*cond
);
846 /* Structure representing an operand. */
848 struct aarch64_opnd_info
850 enum aarch64_opnd type
;
851 aarch64_opnd_qualifier_t qualifier
;
868 unsigned first_regno
: 5;
869 unsigned num_regs
: 3;
870 /* 1 if it is a list of reg element. */
871 unsigned has_index
: 1;
872 /* Lane index; valid only when has_index is 1. */
875 /* e.g. immediate or pc relative address offset. */
881 /* e.g. address in STR (register offset). */
894 unsigned pcrel
: 1; /* PC-relative. */
895 unsigned writeback
: 1;
896 unsigned preind
: 1; /* Pre-indexed. */
897 unsigned postind
: 1; /* Post-indexed. */
899 const aarch64_cond
*cond
;
900 /* The encoding of the system register. */
902 /* The encoding of the PSTATE field. */
903 aarch64_insn pstatefield
;
904 const aarch64_sys_ins_reg
*sysins_op
;
905 const struct aarch64_name_value_pair
*barrier
;
906 const struct aarch64_name_value_pair
*hint_option
;
907 const struct aarch64_name_value_pair
*prfop
;
910 /* Operand shifter; in use when the operand is a register offset address,
911 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
914 enum aarch64_modifier_kind kind
;
915 unsigned operator_present
: 1; /* Only valid during encoding. */
916 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
917 unsigned amount_present
: 1;
921 unsigned skip
:1; /* Operand is not completed if there is a fixup needed
922 to be done on it. In some (but not all) of these
923 cases, we need to tell libopcodes to skip the
924 constraint checking and the encoding for this
925 operand, so that the libopcodes can pick up the
926 right opcode before the operand is fixed-up. This
927 flag should only be used during the
928 assembling/encoding. */
929 unsigned present
:1; /* Whether this operand is present in the assembly
930 line; not used during the disassembly. */
933 typedef struct aarch64_opnd_info aarch64_opnd_info
;
935 /* Structure representing an instruction.
937 It is used during both the assembling and disassembling. The assembler
938 fills an aarch64_inst after a successful parsing and then passes it to the
939 encoding routine to do the encoding. During the disassembling, the
940 disassembler calls the decoding routine to decode a binary instruction; on a
941 successful return, such a structure will be filled with information of the
942 instruction; then the disassembler uses the information to print out the
947 /* The value of the binary instruction. */
950 /* Corresponding opcode entry. */
951 const aarch64_opcode
*opcode
;
953 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
954 const aarch64_cond
*cond
;
956 /* Operands information. */
957 aarch64_opnd_info operands
[AARCH64_MAX_OPND_NUM
];
960 typedef struct aarch64_inst aarch64_inst
;
962 /* Diagnosis related declaration and interface. */
964 /* Operand error kind enumerators.
966 AARCH64_OPDE_RECOVERABLE
967 Less severe error found during the parsing, very possibly because that
968 GAS has picked up a wrong instruction template for the parsing.
970 AARCH64_OPDE_SYNTAX_ERROR
971 General syntax error; it can be either a user error, or simply because
972 that GAS is trying a wrong instruction template.
974 AARCH64_OPDE_FATAL_SYNTAX_ERROR
975 Definitely a user syntax error.
977 AARCH64_OPDE_INVALID_VARIANT
978 No syntax error, but the operands are not a valid combination, e.g.
981 AARCH64_OPDE_UNTIED_OPERAND
982 The asm failed to use the same register for a destination operand
983 and a tied source operand.
985 AARCH64_OPDE_OUT_OF_RANGE
986 Error about some immediate value out of a valid range.
988 AARCH64_OPDE_UNALIGNED
989 Error about some immediate value not properly aligned (i.e. not being a
990 multiple times of a certain value).
992 AARCH64_OPDE_REG_LIST
993 Error about the register list operand having unexpected number of
996 AARCH64_OPDE_OTHER_ERROR
997 Error of the highest severity and used for any severe issue that does not
998 fall into any of the above categories.
1000 The enumerators are only interesting to GAS. They are declared here (in
1001 libopcodes) because that some errors are detected (and then notified to GAS)
1002 by libopcodes (rather than by GAS solely).
1004 The first three errors are only deteced by GAS while the
1005 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1006 only libopcodes has the information about the valid variants of each
1009 The enumerators have an increasing severity. This is helpful when there are
1010 multiple instruction templates available for a given mnemonic name (e.g.
1011 FMOV); this mechanism will help choose the most suitable template from which
1012 the generated diagnostics can most closely describe the issues, if any. */
1014 enum aarch64_operand_error_kind
1017 AARCH64_OPDE_RECOVERABLE
,
1018 AARCH64_OPDE_SYNTAX_ERROR
,
1019 AARCH64_OPDE_FATAL_SYNTAX_ERROR
,
1020 AARCH64_OPDE_INVALID_VARIANT
,
1021 AARCH64_OPDE_UNTIED_OPERAND
,
1022 AARCH64_OPDE_OUT_OF_RANGE
,
1023 AARCH64_OPDE_UNALIGNED
,
1024 AARCH64_OPDE_REG_LIST
,
1025 AARCH64_OPDE_OTHER_ERROR
1028 /* N.B. GAS assumes that this structure work well with shallow copy. */
1029 struct aarch64_operand_error
1031 enum aarch64_operand_error_kind kind
;
1034 int data
[3]; /* Some data for extra information. */
1037 typedef struct aarch64_operand_error aarch64_operand_error
;
1039 /* Encoding entrypoint. */
1042 aarch64_opcode_encode (const aarch64_opcode
*, const aarch64_inst
*,
1043 aarch64_insn
*, aarch64_opnd_qualifier_t
*,
1044 aarch64_operand_error
*);
1046 extern const aarch64_opcode
*
1047 aarch64_replace_opcode (struct aarch64_inst
*,
1048 const aarch64_opcode
*);
1050 /* Given the opcode enumerator OP, return the pointer to the corresponding
1053 extern const aarch64_opcode
*
1054 aarch64_get_opcode (enum aarch64_op
);
1056 /* Generate the string representation of an operand. */
1058 aarch64_print_operand (char *, size_t, bfd_vma
, const aarch64_opcode
*,
1059 const aarch64_opnd_info
*, int, int *, bfd_vma
*);
1061 /* Miscellaneous interface. */
1064 aarch64_operand_index (const enum aarch64_opnd
*, enum aarch64_opnd
);
1066 extern aarch64_opnd_qualifier_t
1067 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t
*, int,
1068 const aarch64_opnd_qualifier_t
, int);
1071 aarch64_num_of_operands (const aarch64_opcode
*);
1074 aarch64_stack_pointer_p (const aarch64_opnd_info
*);
1077 aarch64_zero_register_p (const aarch64_opnd_info
*);
1080 aarch64_decode_insn (aarch64_insn
, aarch64_inst
*, bfd_boolean
);
1082 /* Given an operand qualifier, return the expected data element size
1083 of a qualified operand. */
1084 extern unsigned char
1085 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t
);
1087 extern enum aarch64_operand_class
1088 aarch64_get_operand_class (enum aarch64_opnd
);
1091 aarch64_get_operand_name (enum aarch64_opnd
);
1094 aarch64_get_operand_desc (enum aarch64_opnd
);
1097 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1099 #ifdef DEBUG_AARCH64
1100 extern int debug_dump
;
1103 aarch64_verbose (const char *, ...) __attribute__ ((format (printf
, 1, 2)));
1105 #define DEBUG_TRACE(M, ...) \
1108 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1111 #define DEBUG_TRACE_IF(C, M, ...) \
1113 if (debug_dump && (C)) \
1114 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1116 #else /* !DEBUG_AARCH64 */
1117 #define DEBUG_TRACE(M, ...) ;
1118 #define DEBUG_TRACE_IF(C, M, ...) ;
1119 #endif /* DEBUG_AARCH64 */
1121 extern const char *const aarch64_sve_pattern_array
[32];
1122 extern const char *const aarch64_sve_prfop_array
[16];
1128 #endif /* OPCODE_AARCH64_H */