include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 204   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 205                            each condition flag.  */
 206
 207   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 208   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 209   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 210   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 211   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 212
 213   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 214   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 215
 216   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 217   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 218   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 219   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 220   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 221
 222   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 223   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 224   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 226   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 227                                    negative or unaligned and there is
 228                                    no writeback allowed.  This operand code
 229                                    is only used to support the programmer-
 230                                    friendly feature of using LDR/STR as the
 231                                    the mnemonic name for LDUR/STUR instructions
 232                                    wherever there is no ambiguity.  */
 233   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 234   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 235   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 236
 237   AARCH64_OPND_SYSREG,          /* System register operand.  */
 238   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 239   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 240   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 241   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 242   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 243   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 244   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 245   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 246   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 247
 248   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 249   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 250   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 251   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 252   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 253   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 254   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 255   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 256   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 257   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 258   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 259   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 260   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 261   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 262   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 263   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 264   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 265   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 266   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 267   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 268   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 269   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 270   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 271                                        Bit 14 controls S/U choice.  */
 272   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 273                                        Bit 22 controls S/U choice.  */
 274   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 275                                        Bit 14 controls S/U choice.  */
 276   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 277                                        Bit 22 controls S/U choice.  */
 278   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 279                                        Bit 14 controls S/U choice.  */
 280   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 281                                        Bit 22 controls S/U choice.  */
 282   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 283                                        Bit 14 controls S/U choice.  */
 284   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 285                                        Bit 22 controls S/U choice.  */
 286   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 287   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 288   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 289   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 290   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 291   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 292   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 293   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 294   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 295   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 296   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 297   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 298   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 299   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 300   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 301   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 302   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 303   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 304   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 305   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 306   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 307   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 308   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 309   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 310   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 311   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 312   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 313   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 314   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 315   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 316   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 317   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 318   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 319   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 320   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 321   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 322   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 323   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 324   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 325   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 326   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 327   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 328   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 329   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 330   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 331   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 332   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 333   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 334   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 335 };
 336
 337 /* Qualifier constrains an operand.  It either specifies a variant of an
 338    operand type or limits values available to an operand type.
 339
 340    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 341
 342 enum aarch64_opnd_qualifier
 343 {
 344   /* Indicating no further qualification on an operand.  */
 345   AARCH64_OPND_QLF_NIL,
 346
 347   /* Qualifying an operand which is a general purpose (integer) register;
 348      indicating the operand data size or a specific register.  */
 349   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 350   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 351   AARCH64_OPND_QLF_WSP, /* WSP.  */
 352   AARCH64_OPND_QLF_SP,  /* SP.  */
 353
 354   /* Qualifying an operand which is a floating-point register, a SIMD
 355      vector element or a SIMD vector element list; indicating operand data
 356      size or the size of each SIMD vector element in the case of a SIMD
 357      vector element list.
 358      These qualifiers are also used to qualify an address operand to
 359      indicate the size of data element a load/store instruction is
 360      accessing.
 361      They are also used for the immediate shift operand in e.g. SSHR.  Such
 362      a use is only for the ease of operand encoding/decoding and qualifier
 363      sequence matching; such a use should not be applied widely; use the value
 364      constraint qualifiers for immediate operands wherever possible.  */
 365   AARCH64_OPND_QLF_S_B,
 366   AARCH64_OPND_QLF_S_H,
 367   AARCH64_OPND_QLF_S_S,
 368   AARCH64_OPND_QLF_S_D,
 369   AARCH64_OPND_QLF_S_Q,
 370
 371   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 372      register list; indicating register shape.
 373      They are also used for the immediate shift operand in e.g. SSHR.  Such
 374      a use is only for the ease of operand encoding/decoding and qualifier
 375      sequence matching; such a use should not be applied widely; use the value
 376      constraint qualifiers for immediate operands wherever possible.  */
 377   AARCH64_OPND_QLF_V_8B,
 378   AARCH64_OPND_QLF_V_16B,
 379   AARCH64_OPND_QLF_V_2H,
 380   AARCH64_OPND_QLF_V_4H,
 381   AARCH64_OPND_QLF_V_8H,
 382   AARCH64_OPND_QLF_V_2S,
 383   AARCH64_OPND_QLF_V_4S,
 384   AARCH64_OPND_QLF_V_1D,
 385   AARCH64_OPND_QLF_V_2D,
 386   AARCH64_OPND_QLF_V_1Q,
 387
 388   AARCH64_OPND_QLF_P_Z,
 389   AARCH64_OPND_QLF_P_M,
 390
 391   /* Constraint on value.  */
 392   AARCH64_OPND_QLF_imm_0_7,
 393   AARCH64_OPND_QLF_imm_0_15,
 394   AARCH64_OPND_QLF_imm_0_31,
 395   AARCH64_OPND_QLF_imm_0_63,
 396   AARCH64_OPND_QLF_imm_1_32,
 397   AARCH64_OPND_QLF_imm_1_64,
 398
 399   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 400      or shift-ones.  */
 401   AARCH64_OPND_QLF_LSL,
 402   AARCH64_OPND_QLF_MSL,
 403
 404   /* Special qualifier helping retrieve qualifier information during the
 405      decoding time (currently not in use).  */
 406   AARCH64_OPND_QLF_RETRIEVE,
 407 };
 408 \f
 409 /* Instruction class.  */
 410
 411 enum aarch64_insn_class
 412 {
 413   addsub_carry,
 414   addsub_ext,
 415   addsub_imm,
 416   addsub_shift,
 417   asimdall,
 418   asimddiff,
 419   asimdelem,
 420   asimdext,
 421   asimdimm,
 422   asimdins,
 423   asimdmisc,
 424   asimdperm,
 425   asimdsame,
 426   asimdshf,
 427   asimdtbl,
 428   asisddiff,
 429   asisdelem,
 430   asisdlse,
 431   asisdlsep,
 432   asisdlso,
 433   asisdlsop,
 434   asisdmisc,
 435   asisdone,
 436   asisdpair,
 437   asisdsame,
 438   asisdshf,
 439   bitfield,
 440   branch_imm,
 441   branch_reg,
 442   compbranch,
 443   condbranch,
 444   condcmp_imm,
 445   condcmp_reg,
 446   condsel,
 447   cryptoaes,
 448   cryptosha2,
 449   cryptosha3,
 450   dp_1src,
 451   dp_2src,
 452   dp_3src,
 453   exception,
 454   extract,
 455   float2fix,
 456   float2int,
 457   floatccmp,
 458   floatcmp,
 459   floatdp1,
 460   floatdp2,
 461   floatdp3,
 462   floatimm,
 463   floatsel,
 464   ldst_immpost,
 465   ldst_immpre,
 466   ldst_imm9,    /* immpost or immpre */
 467   ldst_pos,
 468   ldst_regoff,
 469   ldst_unpriv,
 470   ldst_unscaled,
 471   ldstexcl,
 472   ldstnapair_offs,
 473   ldstpair_off,
 474   ldstpair_indexed,
 475   loadlit,
 476   log_imm,
 477   log_shift,
 478   lse_atomic,
 479   movewide,
 480   pcreladdr,
 481   ic_system,
 482   testbranch,
 483 };
 484
 485 /* Opcode enumerators.  */
 486
 487 enum aarch64_op
 488 {
 489   OP_NIL,
 490   OP_STRB_POS,
 491   OP_LDRB_POS,
 492   OP_LDRSB_POS,
 493   OP_STRH_POS,
 494   OP_LDRH_POS,
 495   OP_LDRSH_POS,
 496   OP_STR_POS,
 497   OP_LDR_POS,
 498   OP_STRF_POS,
 499   OP_LDRF_POS,
 500   OP_LDRSW_POS,
 501   OP_PRFM_POS,
 502
 503   OP_STURB,
 504   OP_LDURB,
 505   OP_LDURSB,
 506   OP_STURH,
 507   OP_LDURH,
 508   OP_LDURSH,
 509   OP_STUR,
 510   OP_LDUR,
 511   OP_STURV,
 512   OP_LDURV,
 513   OP_LDURSW,
 514   OP_PRFUM,
 515
 516   OP_LDR_LIT,
 517   OP_LDRV_LIT,
 518   OP_LDRSW_LIT,
 519   OP_PRFM_LIT,
 520
 521   OP_ADD,
 522   OP_B,
 523   OP_BL,
 524
 525   OP_MOVN,
 526   OP_MOVZ,
 527   OP_MOVK,
 528
 529   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 530   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 531   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 532
 533   OP_MOV_V,             /* MOV alias for moving vector register.  */
 534
 535   OP_ASR_IMM,
 536   OP_LSR_IMM,
 537   OP_LSL_IMM,
 538
 539   OP_BIC,
 540
 541   OP_UBFX,
 542   OP_BFXIL,
 543   OP_SBFX,
 544   OP_SBFIZ,
 545   OP_BFI,
 546   OP_BFC,               /* ARMv8.2.  */
 547   OP_UBFIZ,
 548   OP_UXTB,
 549   OP_UXTH,
 550   OP_UXTW,
 551
 552   OP_CINC,
 553   OP_CINV,
 554   OP_CNEG,
 555   OP_CSET,
 556   OP_CSETM,
 557
 558   OP_FCVT,
 559   OP_FCVTN,
 560   OP_FCVTN2,
 561   OP_FCVTL,
 562   OP_FCVTL2,
 563   OP_FCVTXN_S,          /* Scalar version.  */
 564
 565   OP_ROR_IMM,
 566
 567   OP_SXTL,
 568   OP_SXTL2,
 569   OP_UXTL,
 570   OP_UXTL2,
 571
 572   OP_TOTAL_NUM,         /* Pseudo.  */
 573 };
 574
 575 /* Maximum number of operands an instruction can have.  */
 576 #define AARCH64_MAX_OPND_NUM 6
 577 /* Maximum number of qualifier sequences an instruction can have.  */
 578 #define AARCH64_MAX_QLF_SEQ_NUM 10
 579 /* Operand qualifier typedef; optimized for the size.  */
 580 typedef unsigned char aarch64_opnd_qualifier_t;
 581 /* Operand qualifier sequence typedef.  */
 582 typedef aarch64_opnd_qualifier_t        \
 583           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 584
 585 /* FIXME: improve the efficiency.  */
 586 static inline bfd_boolean
 587 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 588 {
 589   int i;
 590   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 591     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 592       return FALSE;
 593   return TRUE;
 594 }
 595
 596 /* This structure holds information for a particular opcode.  */
 597
 598 struct aarch64_opcode
 599 {
 600   /* The name of the mnemonic.  */
 601   const char *name;
 602
 603   /* The opcode itself.  Those bits which will be filled in with
 604      operands are zeroes.  */
 605   aarch64_insn opcode;
 606
 607   /* The opcode mask.  This is used by the disassembler.  This is a
 608      mask containing ones indicating those bits which must match the
 609      opcode field, and zeroes indicating those bits which need not
 610      match (and are presumably filled in by operands).  */
 611   aarch64_insn mask;
 612
 613   /* Instruction class.  */
 614   enum aarch64_insn_class iclass;
 615
 616   /* Enumerator identifier.  */
 617   enum aarch64_op op;
 618
 619   /* Which architecture variant provides this instruction.  */
 620   const aarch64_feature_set *avariant;
 621
 622   /* An array of operand codes.  Each code is an index into the
 623      operand table.  They appear in the order which the operands must
 624      appear in assembly code, and are terminated by a zero.  */
 625   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 626
 627   /* A list of operand qualifier code sequence.  Each operand qualifier
 628      code qualifies the corresponding operand code.  Each operand
 629      qualifier sequence specifies a valid opcode variant and related
 630      constraint on operands.  */
 631   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 632
 633   /* Flags providing information about this instruction */
 634   uint32_t flags;
 635
 636   /* If nonzero, this operand and operand 0 are both registers and
 637      are required to have the same register number.  */
 638   unsigned char tied_operand;
 639
 640   /* If non-NULL, a function to verify that a given instruction is valid.  */
 641   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 642 };
 643
 644 typedef struct aarch64_opcode aarch64_opcode;
 645
 646 /* Table describing all the AArch64 opcodes.  */
 647 extern aarch64_opcode aarch64_opcode_table[];
 648
 649 /* Opcode flags.  */
 650 #define F_ALIAS (1 << 0)
 651 #define F_HAS_ALIAS (1 << 1)
 652 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 653    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 654 #define F_P1 (1 << 2)
 655 #define F_P2 (2 << 2)
 656 #define F_P3 (3 << 2)
 657 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 658 #define F_COND (1 << 4)
 659 /* Instruction has the field of 'sf'.  */
 660 #define F_SF (1 << 5)
 661 /* Instruction has the field of 'size:Q'.  */
 662 #define F_SIZEQ (1 << 6)
 663 /* Floating-point instruction has the field of 'type'.  */
 664 #define F_FPTYPE (1 << 7)
 665 /* AdvSIMD scalar instruction has the field of 'size'.  */
 666 #define F_SSIZE (1 << 8)
 667 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 668 #define F_T (1 << 9)
 669 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 670 #define F_GPRSIZE_IN_Q (1 << 10)
 671 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 672 #define F_LDS_SIZE (1 << 11)
 673 /* Optional operand; assume maximum of 1 operand can be optional.  */
 674 #define F_OPD0_OPT (1 << 12)
 675 #define F_OPD1_OPT (2 << 12)
 676 #define F_OPD2_OPT (3 << 12)
 677 #define F_OPD3_OPT (4 << 12)
 678 #define F_OPD4_OPT (5 << 12)
 679 /* Default value for the optional operand when omitted from the assembly.  */
 680 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 681 /* Instruction that is an alias of another instruction needs to be
 682    encoded/decoded by converting it to/from the real form, followed by
 683    the encoding/decoding according to the rules of the real opcode.
 684    This compares to the direct coding using the alias's information.
 685    N.B. this flag requires F_ALIAS to be used together.  */
 686 #define F_CONV (1 << 20)
 687 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 688    friendly pseudo instruction available only in the assembly code (thus will
 689    not show up in the disassembly).  */
 690 #define F_PSEUDO (1 << 21)
 691 /* Instruction has miscellaneous encoding/decoding rules.  */
 692 #define F_MISC (1 << 22)
 693 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 694 #define F_N (1 << 23)
 695 /* Opcode dependent field.  */
 696 #define F_OD(X) (((X) & 0x7) << 24)
 697 /* Instruction has the field of 'sz'.  */
 698 #define F_LSE_SZ (1 << 27)
 699 /* Require an exact qualifier match, even for NIL qualifiers.  */
 700 #define F_STRICT (1ULL << 28)
 701 /* Next bit is 29.  */
 702
 703 static inline bfd_boolean
 704 alias_opcode_p (const aarch64_opcode *opcode)
 705 {
 706   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 707 }
 708
 709 static inline bfd_boolean
 710 opcode_has_alias (const aarch64_opcode *opcode)
 711 {
 712   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 713 }
 714
 715 /* Priority for disassembling preference.  */
 716 static inline int
 717 opcode_priority (const aarch64_opcode *opcode)
 718 {
 719   return (opcode->flags >> 2) & 0x3;
 720 }
 721
 722 static inline bfd_boolean
 723 pseudo_opcode_p (const aarch64_opcode *opcode)
 724 {
 725   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 726 }
 727
 728 static inline bfd_boolean
 729 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 730 {
 731   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 732     ? TRUE : FALSE;
 733 }
 734
 735 static inline aarch64_insn
 736 get_optional_operand_default_value (const aarch64_opcode *opcode)
 737 {
 738   return (opcode->flags >> 15) & 0x1f;
 739 }
 740
 741 static inline unsigned int
 742 get_opcode_dependent_value (const aarch64_opcode *opcode)
 743 {
 744   return (opcode->flags >> 24) & 0x7;
 745 }
 746
 747 static inline bfd_boolean
 748 opcode_has_special_coder (const aarch64_opcode *opcode)
 749 {
 750   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 751           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 752     : FALSE;
 753 }
 754 \f
 755 struct aarch64_name_value_pair
 756 {
 757   const char *  name;
 758   aarch64_insn  value;
 759 };
 760
 761 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 762 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 763 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 764 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 765
 766 typedef struct
 767 {
 768   const char *  name;
 769   aarch64_insn  value;
 770   uint32_t      flags;
 771 } aarch64_sys_reg;
 772
 773 extern const aarch64_sys_reg aarch64_sys_regs [];
 774 extern const aarch64_sys_reg aarch64_pstatefields [];
 775 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 776 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 777                                                 const aarch64_sys_reg *);
 778 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 779                                                     const aarch64_sys_reg *);
 780
 781 typedef struct
 782 {
 783   const char *name;
 784   uint32_t value;
 785   uint32_t flags ;
 786 } aarch64_sys_ins_reg;
 787
 788 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 789 extern bfd_boolean
 790 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 791                                  const aarch64_sys_ins_reg *);
 792
 793 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 794 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 795 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 796 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 797
 798 /* Shift/extending operator kinds.
 799    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 800 enum aarch64_modifier_kind
 801 {
 802   AARCH64_MOD_NONE,
 803   AARCH64_MOD_MSL,
 804   AARCH64_MOD_ROR,
 805   AARCH64_MOD_ASR,
 806   AARCH64_MOD_LSR,
 807   AARCH64_MOD_LSL,
 808   AARCH64_MOD_UXTB,
 809   AARCH64_MOD_UXTH,
 810   AARCH64_MOD_UXTW,
 811   AARCH64_MOD_UXTX,
 812   AARCH64_MOD_SXTB,
 813   AARCH64_MOD_SXTH,
 814   AARCH64_MOD_SXTW,
 815   AARCH64_MOD_SXTX,
 816   AARCH64_MOD_MUL,
 817   AARCH64_MOD_MUL_VL,
 818 };
 819
 820 bfd_boolean
 821 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 822
 823 enum aarch64_modifier_kind
 824 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 825 /* Condition.  */
 826
 827 typedef struct
 828 {
 829   /* A list of names with the first one as the disassembly preference;
 830      terminated by NULL if fewer than 3.  */
 831   const char *names[3];
 832   aarch64_insn value;
 833 } aarch64_cond;
 834
 835 extern const aarch64_cond aarch64_conds[16];
 836
 837 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 838 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 839 \f
 840 /* Structure representing an operand.  */
 841
 842 struct aarch64_opnd_info
 843 {
 844   enum aarch64_opnd type;
 845   aarch64_opnd_qualifier_t qualifier;
 846   int idx;
 847
 848   union
 849     {
 850       struct
 851         {
 852           unsigned regno;
 853         } reg;
 854       struct
 855         {
 856           unsigned int regno;
 857           int64_t index;
 858         } reglane;
 859       /* e.g. LVn.  */
 860       struct
 861         {
 862           unsigned first_regno : 5;
 863           unsigned num_regs : 3;
 864           /* 1 if it is a list of reg element.  */
 865           unsigned has_index : 1;
 866           /* Lane index; valid only when has_index is 1.  */
 867           int64_t index;
 868         } reglist;
 869       /* e.g. immediate or pc relative address offset.  */
 870       struct
 871         {
 872           int64_t value;
 873           unsigned is_fp : 1;
 874         } imm;
 875       /* e.g. address in STR (register offset).  */
 876       struct
 877         {
 878           unsigned base_regno;
 879           struct
 880             {
 881               union
 882                 {
 883                   int imm;
 884                   unsigned regno;
 885                 };
 886               unsigned is_reg;
 887             } offset;
 888           unsigned pcrel : 1;           /* PC-relative.  */
 889           unsigned writeback : 1;
 890           unsigned preind : 1;          /* Pre-indexed.  */
 891           unsigned postind : 1;         /* Post-indexed.  */
 892         } addr;
 893       const aarch64_cond *cond;
 894       /* The encoding of the system register.  */
 895       aarch64_insn sysreg;
 896       /* The encoding of the PSTATE field.  */
 897       aarch64_insn pstatefield;
 898       const aarch64_sys_ins_reg *sysins_op;
 899       const struct aarch64_name_value_pair *barrier;
 900       const struct aarch64_name_value_pair *hint_option;
 901       const struct aarch64_name_value_pair *prfop;
 902     };
 903
 904   /* Operand shifter; in use when the operand is a register offset address,
 905      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 906   struct
 907     {
 908       enum aarch64_modifier_kind kind;
 909       unsigned operator_present: 1;     /* Only valid during encoding.  */
 910       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 911       unsigned amount_present: 1;
 912       int64_t amount;
 913     } shifter;
 914
 915   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 916                            to be done on it.  In some (but not all) of these
 917                            cases, we need to tell libopcodes to skip the
 918                            constraint checking and the encoding for this
 919                            operand, so that the libopcodes can pick up the
 920                            right opcode before the operand is fixed-up.  This
 921                            flag should only be used during the
 922                            assembling/encoding.  */
 923   unsigned present:1;   /* Whether this operand is present in the assembly
 924                            line; not used during the disassembly.  */
 925 };
 926
 927 typedef struct aarch64_opnd_info aarch64_opnd_info;
 928
 929 /* Structure representing an instruction.
 930
 931    It is used during both the assembling and disassembling.  The assembler
 932    fills an aarch64_inst after a successful parsing and then passes it to the
 933    encoding routine to do the encoding.  During the disassembling, the
 934    disassembler calls the decoding routine to decode a binary instruction; on a
 935    successful return, such a structure will be filled with information of the
 936    instruction; then the disassembler uses the information to print out the
 937    instruction.  */
 938
 939 struct aarch64_inst
 940 {
 941   /* The value of the binary instruction.  */
 942   aarch64_insn value;
 943
 944   /* Corresponding opcode entry.  */
 945   const aarch64_opcode *opcode;
 946
 947   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 948   const aarch64_cond *cond;
 949
 950   /* Operands information.  */
 951   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 952 };
 953
 954 typedef struct aarch64_inst aarch64_inst;
 955 \f
 956 /* Diagnosis related declaration and interface.  */
 957
 958 /* Operand error kind enumerators.
 959
 960    AARCH64_OPDE_RECOVERABLE
 961      Less severe error found during the parsing, very possibly because that
 962      GAS has picked up a wrong instruction template for the parsing.
 963
 964    AARCH64_OPDE_SYNTAX_ERROR
 965      General syntax error; it can be either a user error, or simply because
 966      that GAS is trying a wrong instruction template.
 967
 968    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 969      Definitely a user syntax error.
 970
 971    AARCH64_OPDE_INVALID_VARIANT
 972      No syntax error, but the operands are not a valid combination, e.g.
 973      FMOV D0,S0
 974
 975    AARCH64_OPDE_UNTIED_OPERAND
 976      The asm failed to use the same register for a destination operand
 977      and a tied source operand.
 978
 979    AARCH64_OPDE_OUT_OF_RANGE
 980      Error about some immediate value out of a valid range.
 981
 982    AARCH64_OPDE_UNALIGNED
 983      Error about some immediate value not properly aligned (i.e. not being a
 984      multiple times of a certain value).
 985
 986    AARCH64_OPDE_REG_LIST
 987      Error about the register list operand having unexpected number of
 988      registers.
 989
 990    AARCH64_OPDE_OTHER_ERROR
 991      Error of the highest severity and used for any severe issue that does not
 992      fall into any of the above categories.
 993
 994    The enumerators are only interesting to GAS.  They are declared here (in
 995    libopcodes) because that some errors are detected (and then notified to GAS)
 996    by libopcodes (rather than by GAS solely).
 997
 998    The first three errors are only deteced by GAS while the
 999    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1000    only libopcodes has the information about the valid variants of each
1001    instruction.
1002
1003    The enumerators have an increasing severity.  This is helpful when there are
1004    multiple instruction templates available for a given mnemonic name (e.g.
1005    FMOV); this mechanism will help choose the most suitable template from which
1006    the generated diagnostics can most closely describe the issues, if any.  */
1007
1008 enum aarch64_operand_error_kind
1009 {
1010   AARCH64_OPDE_NIL,
1011   AARCH64_OPDE_RECOVERABLE,
1012   AARCH64_OPDE_SYNTAX_ERROR,
1013   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1014   AARCH64_OPDE_INVALID_VARIANT,
1015   AARCH64_OPDE_UNTIED_OPERAND,
1016   AARCH64_OPDE_OUT_OF_RANGE,
1017   AARCH64_OPDE_UNALIGNED,
1018   AARCH64_OPDE_REG_LIST,
1019   AARCH64_OPDE_OTHER_ERROR
1020 };
1021
1022 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1023 struct aarch64_operand_error
1024 {
1025   enum aarch64_operand_error_kind kind;
1026   int index;
1027   const char *error;
1028   int data[3];  /* Some data for extra information.  */
1029 };
1030
1031 typedef struct aarch64_operand_error aarch64_operand_error;
1032
1033 /* Encoding entrypoint.  */
1034
1035 extern int
1036 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1037                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1038                        aarch64_operand_error *);
1039
1040 extern const aarch64_opcode *
1041 aarch64_replace_opcode (struct aarch64_inst *,
1042                         const aarch64_opcode *);
1043
1044 /* Given the opcode enumerator OP, return the pointer to the corresponding
1045    opcode entry.  */
1046
1047 extern const aarch64_opcode *
1048 aarch64_get_opcode (enum aarch64_op);
1049
1050 /* Generate the string representation of an operand.  */
1051 extern void
1052 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1053                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1054
1055 /* Miscellaneous interface.  */
1056
1057 extern int
1058 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1059
1060 extern aarch64_opnd_qualifier_t
1061 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1062                                 const aarch64_opnd_qualifier_t, int);
1063
1064 extern int
1065 aarch64_num_of_operands (const aarch64_opcode *);
1066
1067 extern int
1068 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1069
1070 extern int
1071 aarch64_zero_register_p (const aarch64_opnd_info *);
1072
1073 extern int
1074 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1075
1076 /* Given an operand qualifier, return the expected data element size
1077    of a qualified operand.  */
1078 extern unsigned char
1079 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1080
1081 extern enum aarch64_operand_class
1082 aarch64_get_operand_class (enum aarch64_opnd);
1083
1084 extern const char *
1085 aarch64_get_operand_name (enum aarch64_opnd);
1086
1087 extern const char *
1088 aarch64_get_operand_desc (enum aarch64_opnd);
1089
1090 extern bfd_boolean
1091 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1092
1093 #ifdef DEBUG_AARCH64
1094 extern int debug_dump;
1095
1096 extern void
1097 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1098
1099 #define DEBUG_TRACE(M, ...)                                     \
1100   {                                                             \
1101     if (debug_dump)                                             \
1102       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1103   }
1104
1105 #define DEBUG_TRACE_IF(C, M, ...)                               \
1106   {                                                             \
1107     if (debug_dump && (C))                                      \
1108       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1109   }
1110 #else  /* !DEBUG_AARCH64 */
1111 #define DEBUG_TRACE(M, ...) ;
1112 #define DEBUG_TRACE_IF(C, M, ...) ;
1113 #endif /* DEBUG_AARCH64 */
1114
1115 extern const char *const aarch64_sve_pattern_array[32];
1116 extern const char *const aarch64_sve_prfop_array[16];
1117
1118 #ifdef __cplusplus
1119 }
1120 #endif
1121
1122 #endif /* OPCODE_AARCH64_H */