include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 204                            each condition flag.  */
 205
 206   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 207   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 208   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 209   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 210   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 211
 212   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 213   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 214
 215   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 216   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 217   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 218   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 219   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 220
 221   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 222   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 223   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 224   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 226                                    negative or unaligned and there is
 227                                    no writeback allowed.  This operand code
 228                                    is only used to support the programmer-
 229                                    friendly feature of using LDR/STR as the
 230                                    the mnemonic name for LDUR/STUR instructions
 231                                    wherever there is no ambiguity.  */
 232   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 233   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 234   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 235
 236   AARCH64_OPND_SYSREG,          /* System register operand.  */
 237   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 238   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 239   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 240   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 241   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 242   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 243   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 244   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 245   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 246
 247   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 248   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 249   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 250   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 251   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 252   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 253   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 254   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 255   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 256   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 257   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 258   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 259   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 260   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 261   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 262   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 263   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 264                                        Bit 14 controls S/U choice.  */
 265   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 266                                        Bit 22 controls S/U choice.  */
 267   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 268                                        Bit 14 controls S/U choice.  */
 269   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 270                                        Bit 22 controls S/U choice.  */
 271   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 272                                        Bit 14 controls S/U choice.  */
 273   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 274                                        Bit 22 controls S/U choice.  */
 275   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 276                                        Bit 14 controls S/U choice.  */
 277   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 278                                        Bit 22 controls S/U choice.  */
 279   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 280   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 281   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 282   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 283   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 284   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 285   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 286   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 287   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 288   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 289   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 290   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 291   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 292   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 293   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 294   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 295   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 296   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 297   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 298   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 299   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 300   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 301   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 302   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 303   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 304   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 305   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 306   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 307 };
 308
 309 /* Qualifier constrains an operand.  It either specifies a variant of an
 310    operand type or limits values available to an operand type.
 311
 312    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 313
 314 enum aarch64_opnd_qualifier
 315 {
 316   /* Indicating no further qualification on an operand.  */
 317   AARCH64_OPND_QLF_NIL,
 318
 319   /* Qualifying an operand which is a general purpose (integer) register;
 320      indicating the operand data size or a specific register.  */
 321   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 322   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 323   AARCH64_OPND_QLF_WSP, /* WSP.  */
 324   AARCH64_OPND_QLF_SP,  /* SP.  */
 325
 326   /* Qualifying an operand which is a floating-point register, a SIMD
 327      vector element or a SIMD vector element list; indicating operand data
 328      size or the size of each SIMD vector element in the case of a SIMD
 329      vector element list.
 330      These qualifiers are also used to qualify an address operand to
 331      indicate the size of data element a load/store instruction is
 332      accessing.
 333      They are also used for the immediate shift operand in e.g. SSHR.  Such
 334      a use is only for the ease of operand encoding/decoding and qualifier
 335      sequence matching; such a use should not be applied widely; use the value
 336      constraint qualifiers for immediate operands wherever possible.  */
 337   AARCH64_OPND_QLF_S_B,
 338   AARCH64_OPND_QLF_S_H,
 339   AARCH64_OPND_QLF_S_S,
 340   AARCH64_OPND_QLF_S_D,
 341   AARCH64_OPND_QLF_S_Q,
 342
 343   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 344      register list; indicating register shape.
 345      They are also used for the immediate shift operand in e.g. SSHR.  Such
 346      a use is only for the ease of operand encoding/decoding and qualifier
 347      sequence matching; such a use should not be applied widely; use the value
 348      constraint qualifiers for immediate operands wherever possible.  */
 349   AARCH64_OPND_QLF_V_8B,
 350   AARCH64_OPND_QLF_V_16B,
 351   AARCH64_OPND_QLF_V_2H,
 352   AARCH64_OPND_QLF_V_4H,
 353   AARCH64_OPND_QLF_V_8H,
 354   AARCH64_OPND_QLF_V_2S,
 355   AARCH64_OPND_QLF_V_4S,
 356   AARCH64_OPND_QLF_V_1D,
 357   AARCH64_OPND_QLF_V_2D,
 358   AARCH64_OPND_QLF_V_1Q,
 359
 360   AARCH64_OPND_QLF_P_Z,
 361   AARCH64_OPND_QLF_P_M,
 362
 363   /* Constraint on value.  */
 364   AARCH64_OPND_QLF_imm_0_7,
 365   AARCH64_OPND_QLF_imm_0_15,
 366   AARCH64_OPND_QLF_imm_0_31,
 367   AARCH64_OPND_QLF_imm_0_63,
 368   AARCH64_OPND_QLF_imm_1_32,
 369   AARCH64_OPND_QLF_imm_1_64,
 370
 371   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 372      or shift-ones.  */
 373   AARCH64_OPND_QLF_LSL,
 374   AARCH64_OPND_QLF_MSL,
 375
 376   /* Special qualifier helping retrieve qualifier information during the
 377      decoding time (currently not in use).  */
 378   AARCH64_OPND_QLF_RETRIEVE,
 379 };
 380 \f
 381 /* Instruction class.  */
 382
 383 enum aarch64_insn_class
 384 {
 385   addsub_carry,
 386   addsub_ext,
 387   addsub_imm,
 388   addsub_shift,
 389   asimdall,
 390   asimddiff,
 391   asimdelem,
 392   asimdext,
 393   asimdimm,
 394   asimdins,
 395   asimdmisc,
 396   asimdperm,
 397   asimdsame,
 398   asimdshf,
 399   asimdtbl,
 400   asisddiff,
 401   asisdelem,
 402   asisdlse,
 403   asisdlsep,
 404   asisdlso,
 405   asisdlsop,
 406   asisdmisc,
 407   asisdone,
 408   asisdpair,
 409   asisdsame,
 410   asisdshf,
 411   bitfield,
 412   branch_imm,
 413   branch_reg,
 414   compbranch,
 415   condbranch,
 416   condcmp_imm,
 417   condcmp_reg,
 418   condsel,
 419   cryptoaes,
 420   cryptosha2,
 421   cryptosha3,
 422   dp_1src,
 423   dp_2src,
 424   dp_3src,
 425   exception,
 426   extract,
 427   float2fix,
 428   float2int,
 429   floatccmp,
 430   floatcmp,
 431   floatdp1,
 432   floatdp2,
 433   floatdp3,
 434   floatimm,
 435   floatsel,
 436   ldst_immpost,
 437   ldst_immpre,
 438   ldst_imm9,    /* immpost or immpre */
 439   ldst_pos,
 440   ldst_regoff,
 441   ldst_unpriv,
 442   ldst_unscaled,
 443   ldstexcl,
 444   ldstnapair_offs,
 445   ldstpair_off,
 446   ldstpair_indexed,
 447   loadlit,
 448   log_imm,
 449   log_shift,
 450   lse_atomic,
 451   movewide,
 452   pcreladdr,
 453   ic_system,
 454   testbranch,
 455 };
 456
 457 /* Opcode enumerators.  */
 458
 459 enum aarch64_op
 460 {
 461   OP_NIL,
 462   OP_STRB_POS,
 463   OP_LDRB_POS,
 464   OP_LDRSB_POS,
 465   OP_STRH_POS,
 466   OP_LDRH_POS,
 467   OP_LDRSH_POS,
 468   OP_STR_POS,
 469   OP_LDR_POS,
 470   OP_STRF_POS,
 471   OP_LDRF_POS,
 472   OP_LDRSW_POS,
 473   OP_PRFM_POS,
 474
 475   OP_STURB,
 476   OP_LDURB,
 477   OP_LDURSB,
 478   OP_STURH,
 479   OP_LDURH,
 480   OP_LDURSH,
 481   OP_STUR,
 482   OP_LDUR,
 483   OP_STURV,
 484   OP_LDURV,
 485   OP_LDURSW,
 486   OP_PRFUM,
 487
 488   OP_LDR_LIT,
 489   OP_LDRV_LIT,
 490   OP_LDRSW_LIT,
 491   OP_PRFM_LIT,
 492
 493   OP_ADD,
 494   OP_B,
 495   OP_BL,
 496
 497   OP_MOVN,
 498   OP_MOVZ,
 499   OP_MOVK,
 500
 501   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 502   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 503   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 504
 505   OP_MOV_V,             /* MOV alias for moving vector register.  */
 506
 507   OP_ASR_IMM,
 508   OP_LSR_IMM,
 509   OP_LSL_IMM,
 510
 511   OP_BIC,
 512
 513   OP_UBFX,
 514   OP_BFXIL,
 515   OP_SBFX,
 516   OP_SBFIZ,
 517   OP_BFI,
 518   OP_BFC,               /* ARMv8.2.  */
 519   OP_UBFIZ,
 520   OP_UXTB,
 521   OP_UXTH,
 522   OP_UXTW,
 523
 524   OP_CINC,
 525   OP_CINV,
 526   OP_CNEG,
 527   OP_CSET,
 528   OP_CSETM,
 529
 530   OP_FCVT,
 531   OP_FCVTN,
 532   OP_FCVTN2,
 533   OP_FCVTL,
 534   OP_FCVTL2,
 535   OP_FCVTXN_S,          /* Scalar version.  */
 536
 537   OP_ROR_IMM,
 538
 539   OP_SXTL,
 540   OP_SXTL2,
 541   OP_UXTL,
 542   OP_UXTL2,
 543
 544   OP_TOTAL_NUM,         /* Pseudo.  */
 545 };
 546
 547 /* Maximum number of operands an instruction can have.  */
 548 #define AARCH64_MAX_OPND_NUM 6
 549 /* Maximum number of qualifier sequences an instruction can have.  */
 550 #define AARCH64_MAX_QLF_SEQ_NUM 10
 551 /* Operand qualifier typedef; optimized for the size.  */
 552 typedef unsigned char aarch64_opnd_qualifier_t;
 553 /* Operand qualifier sequence typedef.  */
 554 typedef aarch64_opnd_qualifier_t        \
 555           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 556
 557 /* FIXME: improve the efficiency.  */
 558 static inline bfd_boolean
 559 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 560 {
 561   int i;
 562   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 563     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 564       return FALSE;
 565   return TRUE;
 566 }
 567
 568 /* This structure holds information for a particular opcode.  */
 569
 570 struct aarch64_opcode
 571 {
 572   /* The name of the mnemonic.  */
 573   const char *name;
 574
 575   /* The opcode itself.  Those bits which will be filled in with
 576      operands are zeroes.  */
 577   aarch64_insn opcode;
 578
 579   /* The opcode mask.  This is used by the disassembler.  This is a
 580      mask containing ones indicating those bits which must match the
 581      opcode field, and zeroes indicating those bits which need not
 582      match (and are presumably filled in by operands).  */
 583   aarch64_insn mask;
 584
 585   /* Instruction class.  */
 586   enum aarch64_insn_class iclass;
 587
 588   /* Enumerator identifier.  */
 589   enum aarch64_op op;
 590
 591   /* Which architecture variant provides this instruction.  */
 592   const aarch64_feature_set *avariant;
 593
 594   /* An array of operand codes.  Each code is an index into the
 595      operand table.  They appear in the order which the operands must
 596      appear in assembly code, and are terminated by a zero.  */
 597   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 598
 599   /* A list of operand qualifier code sequence.  Each operand qualifier
 600      code qualifies the corresponding operand code.  Each operand
 601      qualifier sequence specifies a valid opcode variant and related
 602      constraint on operands.  */
 603   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 604
 605   /* Flags providing information about this instruction */
 606   uint32_t flags;
 607
 608   /* If nonzero, this operand and operand 0 are both registers and
 609      are required to have the same register number.  */
 610   unsigned char tied_operand;
 611
 612   /* If non-NULL, a function to verify that a given instruction is valid.  */
 613   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 614 };
 615
 616 typedef struct aarch64_opcode aarch64_opcode;
 617
 618 /* Table describing all the AArch64 opcodes.  */
 619 extern aarch64_opcode aarch64_opcode_table[];
 620
 621 /* Opcode flags.  */
 622 #define F_ALIAS (1 << 0)
 623 #define F_HAS_ALIAS (1 << 1)
 624 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 625    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 626 #define F_P1 (1 << 2)
 627 #define F_P2 (2 << 2)
 628 #define F_P3 (3 << 2)
 629 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 630 #define F_COND (1 << 4)
 631 /* Instruction has the field of 'sf'.  */
 632 #define F_SF (1 << 5)
 633 /* Instruction has the field of 'size:Q'.  */
 634 #define F_SIZEQ (1 << 6)
 635 /* Floating-point instruction has the field of 'type'.  */
 636 #define F_FPTYPE (1 << 7)
 637 /* AdvSIMD scalar instruction has the field of 'size'.  */
 638 #define F_SSIZE (1 << 8)
 639 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 640 #define F_T (1 << 9)
 641 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 642 #define F_GPRSIZE_IN_Q (1 << 10)
 643 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 644 #define F_LDS_SIZE (1 << 11)
 645 /* Optional operand; assume maximum of 1 operand can be optional.  */
 646 #define F_OPD0_OPT (1 << 12)
 647 #define F_OPD1_OPT (2 << 12)
 648 #define F_OPD2_OPT (3 << 12)
 649 #define F_OPD3_OPT (4 << 12)
 650 #define F_OPD4_OPT (5 << 12)
 651 /* Default value for the optional operand when omitted from the assembly.  */
 652 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 653 /* Instruction that is an alias of another instruction needs to be
 654    encoded/decoded by converting it to/from the real form, followed by
 655    the encoding/decoding according to the rules of the real opcode.
 656    This compares to the direct coding using the alias's information.
 657    N.B. this flag requires F_ALIAS to be used together.  */
 658 #define F_CONV (1 << 20)
 659 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 660    friendly pseudo instruction available only in the assembly code (thus will
 661    not show up in the disassembly).  */
 662 #define F_PSEUDO (1 << 21)
 663 /* Instruction has miscellaneous encoding/decoding rules.  */
 664 #define F_MISC (1 << 22)
 665 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 666 #define F_N (1 << 23)
 667 /* Opcode dependent field.  */
 668 #define F_OD(X) (((X) & 0x7) << 24)
 669 /* Instruction has the field of 'sz'.  */
 670 #define F_LSE_SZ (1 << 27)
 671 /* Require an exact qualifier match, even for NIL qualifiers.  */
 672 #define F_STRICT (1ULL << 28)
 673 /* Next bit is 29.  */
 674
 675 static inline bfd_boolean
 676 alias_opcode_p (const aarch64_opcode *opcode)
 677 {
 678   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 679 }
 680
 681 static inline bfd_boolean
 682 opcode_has_alias (const aarch64_opcode *opcode)
 683 {
 684   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 685 }
 686
 687 /* Priority for disassembling preference.  */
 688 static inline int
 689 opcode_priority (const aarch64_opcode *opcode)
 690 {
 691   return (opcode->flags >> 2) & 0x3;
 692 }
 693
 694 static inline bfd_boolean
 695 pseudo_opcode_p (const aarch64_opcode *opcode)
 696 {
 697   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 698 }
 699
 700 static inline bfd_boolean
 701 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 702 {
 703   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 704     ? TRUE : FALSE;
 705 }
 706
 707 static inline aarch64_insn
 708 get_optional_operand_default_value (const aarch64_opcode *opcode)
 709 {
 710   return (opcode->flags >> 15) & 0x1f;
 711 }
 712
 713 static inline unsigned int
 714 get_opcode_dependent_value (const aarch64_opcode *opcode)
 715 {
 716   return (opcode->flags >> 24) & 0x7;
 717 }
 718
 719 static inline bfd_boolean
 720 opcode_has_special_coder (const aarch64_opcode *opcode)
 721 {
 722   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 723           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 724     : FALSE;
 725 }
 726 \f
 727 struct aarch64_name_value_pair
 728 {
 729   const char *  name;
 730   aarch64_insn  value;
 731 };
 732
 733 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 734 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 735 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 736 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 737
 738 typedef struct
 739 {
 740   const char *  name;
 741   aarch64_insn  value;
 742   uint32_t      flags;
 743 } aarch64_sys_reg;
 744
 745 extern const aarch64_sys_reg aarch64_sys_regs [];
 746 extern const aarch64_sys_reg aarch64_pstatefields [];
 747 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 748 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 749                                                 const aarch64_sys_reg *);
 750 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 751                                                     const aarch64_sys_reg *);
 752
 753 typedef struct
 754 {
 755   const char *name;
 756   uint32_t value;
 757   uint32_t flags ;
 758 } aarch64_sys_ins_reg;
 759
 760 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 761 extern bfd_boolean
 762 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 763                                  const aarch64_sys_ins_reg *);
 764
 765 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 766 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 767 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 768 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 769
 770 /* Shift/extending operator kinds.
 771    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 772 enum aarch64_modifier_kind
 773 {
 774   AARCH64_MOD_NONE,
 775   AARCH64_MOD_MSL,
 776   AARCH64_MOD_ROR,
 777   AARCH64_MOD_ASR,
 778   AARCH64_MOD_LSR,
 779   AARCH64_MOD_LSL,
 780   AARCH64_MOD_UXTB,
 781   AARCH64_MOD_UXTH,
 782   AARCH64_MOD_UXTW,
 783   AARCH64_MOD_UXTX,
 784   AARCH64_MOD_SXTB,
 785   AARCH64_MOD_SXTH,
 786   AARCH64_MOD_SXTW,
 787   AARCH64_MOD_SXTX,
 788   AARCH64_MOD_MUL,
 789 };
 790
 791 bfd_boolean
 792 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 793
 794 enum aarch64_modifier_kind
 795 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 796 /* Condition.  */
 797
 798 typedef struct
 799 {
 800   /* A list of names with the first one as the disassembly preference;
 801      terminated by NULL if fewer than 3.  */
 802   const char *names[3];
 803   aarch64_insn value;
 804 } aarch64_cond;
 805
 806 extern const aarch64_cond aarch64_conds[16];
 807
 808 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 809 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 810 \f
 811 /* Structure representing an operand.  */
 812
 813 struct aarch64_opnd_info
 814 {
 815   enum aarch64_opnd type;
 816   aarch64_opnd_qualifier_t qualifier;
 817   int idx;
 818
 819   union
 820     {
 821       struct
 822         {
 823           unsigned regno;
 824         } reg;
 825       struct
 826         {
 827           unsigned int regno;
 828           int64_t index;
 829         } reglane;
 830       /* e.g. LVn.  */
 831       struct
 832         {
 833           unsigned first_regno : 5;
 834           unsigned num_regs : 3;
 835           /* 1 if it is a list of reg element.  */
 836           unsigned has_index : 1;
 837           /* Lane index; valid only when has_index is 1.  */
 838           int64_t index;
 839         } reglist;
 840       /* e.g. immediate or pc relative address offset.  */
 841       struct
 842         {
 843           int64_t value;
 844           unsigned is_fp : 1;
 845         } imm;
 846       /* e.g. address in STR (register offset).  */
 847       struct
 848         {
 849           unsigned base_regno;
 850           struct
 851             {
 852               union
 853                 {
 854                   int imm;
 855                   unsigned regno;
 856                 };
 857               unsigned is_reg;
 858             } offset;
 859           unsigned pcrel : 1;           /* PC-relative.  */
 860           unsigned writeback : 1;
 861           unsigned preind : 1;          /* Pre-indexed.  */
 862           unsigned postind : 1;         /* Post-indexed.  */
 863         } addr;
 864       const aarch64_cond *cond;
 865       /* The encoding of the system register.  */
 866       aarch64_insn sysreg;
 867       /* The encoding of the PSTATE field.  */
 868       aarch64_insn pstatefield;
 869       const aarch64_sys_ins_reg *sysins_op;
 870       const struct aarch64_name_value_pair *barrier;
 871       const struct aarch64_name_value_pair *hint_option;
 872       const struct aarch64_name_value_pair *prfop;
 873     };
 874
 875   /* Operand shifter; in use when the operand is a register offset address,
 876      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 877   struct
 878     {
 879       enum aarch64_modifier_kind kind;
 880       unsigned operator_present: 1;     /* Only valid during encoding.  */
 881       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 882       unsigned amount_present: 1;
 883       int64_t amount;
 884     } shifter;
 885
 886   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 887                            to be done on it.  In some (but not all) of these
 888                            cases, we need to tell libopcodes to skip the
 889                            constraint checking and the encoding for this
 890                            operand, so that the libopcodes can pick up the
 891                            right opcode before the operand is fixed-up.  This
 892                            flag should only be used during the
 893                            assembling/encoding.  */
 894   unsigned present:1;   /* Whether this operand is present in the assembly
 895                            line; not used during the disassembly.  */
 896 };
 897
 898 typedef struct aarch64_opnd_info aarch64_opnd_info;
 899
 900 /* Structure representing an instruction.
 901
 902    It is used during both the assembling and disassembling.  The assembler
 903    fills an aarch64_inst after a successful parsing and then passes it to the
 904    encoding routine to do the encoding.  During the disassembling, the
 905    disassembler calls the decoding routine to decode a binary instruction; on a
 906    successful return, such a structure will be filled with information of the
 907    instruction; then the disassembler uses the information to print out the
 908    instruction.  */
 909
 910 struct aarch64_inst
 911 {
 912   /* The value of the binary instruction.  */
 913   aarch64_insn value;
 914
 915   /* Corresponding opcode entry.  */
 916   const aarch64_opcode *opcode;
 917
 918   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 919   const aarch64_cond *cond;
 920
 921   /* Operands information.  */
 922   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 923 };
 924
 925 typedef struct aarch64_inst aarch64_inst;
 926 \f
 927 /* Diagnosis related declaration and interface.  */
 928
 929 /* Operand error kind enumerators.
 930
 931    AARCH64_OPDE_RECOVERABLE
 932      Less severe error found during the parsing, very possibly because that
 933      GAS has picked up a wrong instruction template for the parsing.
 934
 935    AARCH64_OPDE_SYNTAX_ERROR
 936      General syntax error; it can be either a user error, or simply because
 937      that GAS is trying a wrong instruction template.
 938
 939    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 940      Definitely a user syntax error.
 941
 942    AARCH64_OPDE_INVALID_VARIANT
 943      No syntax error, but the operands are not a valid combination, e.g.
 944      FMOV D0,S0
 945
 946    AARCH64_OPDE_UNTIED_OPERAND
 947      The asm failed to use the same register for a destination operand
 948      and a tied source operand.
 949
 950    AARCH64_OPDE_OUT_OF_RANGE
 951      Error about some immediate value out of a valid range.
 952
 953    AARCH64_OPDE_UNALIGNED
 954      Error about some immediate value not properly aligned (i.e. not being a
 955      multiple times of a certain value).
 956
 957    AARCH64_OPDE_REG_LIST
 958      Error about the register list operand having unexpected number of
 959      registers.
 960
 961    AARCH64_OPDE_OTHER_ERROR
 962      Error of the highest severity and used for any severe issue that does not
 963      fall into any of the above categories.
 964
 965    The enumerators are only interesting to GAS.  They are declared here (in
 966    libopcodes) because that some errors are detected (and then notified to GAS)
 967    by libopcodes (rather than by GAS solely).
 968
 969    The first three errors are only deteced by GAS while the
 970    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 971    only libopcodes has the information about the valid variants of each
 972    instruction.
 973
 974    The enumerators have an increasing severity.  This is helpful when there are
 975    multiple instruction templates available for a given mnemonic name (e.g.
 976    FMOV); this mechanism will help choose the most suitable template from which
 977    the generated diagnostics can most closely describe the issues, if any.  */
 978
 979 enum aarch64_operand_error_kind
 980 {
 981   AARCH64_OPDE_NIL,
 982   AARCH64_OPDE_RECOVERABLE,
 983   AARCH64_OPDE_SYNTAX_ERROR,
 984   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 985   AARCH64_OPDE_INVALID_VARIANT,
 986   AARCH64_OPDE_UNTIED_OPERAND,
 987   AARCH64_OPDE_OUT_OF_RANGE,
 988   AARCH64_OPDE_UNALIGNED,
 989   AARCH64_OPDE_REG_LIST,
 990   AARCH64_OPDE_OTHER_ERROR
 991 };
 992
 993 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 994 struct aarch64_operand_error
 995 {
 996   enum aarch64_operand_error_kind kind;
 997   int index;
 998   const char *error;
 999   int data[3];  /* Some data for extra information.  */
1000 };
1001
1002 typedef struct aarch64_operand_error aarch64_operand_error;
1003
1004 /* Encoding entrypoint.  */
1005
1006 extern int
1007 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1008                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1009                        aarch64_operand_error *);
1010
1011 extern const aarch64_opcode *
1012 aarch64_replace_opcode (struct aarch64_inst *,
1013                         const aarch64_opcode *);
1014
1015 /* Given the opcode enumerator OP, return the pointer to the corresponding
1016    opcode entry.  */
1017
1018 extern const aarch64_opcode *
1019 aarch64_get_opcode (enum aarch64_op);
1020
1021 /* Generate the string representation of an operand.  */
1022 extern void
1023 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1024                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1025
1026 /* Miscellaneous interface.  */
1027
1028 extern int
1029 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1030
1031 extern aarch64_opnd_qualifier_t
1032 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1033                                 const aarch64_opnd_qualifier_t, int);
1034
1035 extern int
1036 aarch64_num_of_operands (const aarch64_opcode *);
1037
1038 extern int
1039 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1040
1041 extern int
1042 aarch64_zero_register_p (const aarch64_opnd_info *);
1043
1044 extern int
1045 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1046
1047 /* Given an operand qualifier, return the expected data element size
1048    of a qualified operand.  */
1049 extern unsigned char
1050 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1051
1052 extern enum aarch64_operand_class
1053 aarch64_get_operand_class (enum aarch64_opnd);
1054
1055 extern const char *
1056 aarch64_get_operand_name (enum aarch64_opnd);
1057
1058 extern const char *
1059 aarch64_get_operand_desc (enum aarch64_opnd);
1060
1061 #ifdef DEBUG_AARCH64
1062 extern int debug_dump;
1063
1064 extern void
1065 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1066
1067 #define DEBUG_TRACE(M, ...)                                     \
1068   {                                                             \
1069     if (debug_dump)                                             \
1070       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1071   }
1072
1073 #define DEBUG_TRACE_IF(C, M, ...)                               \
1074   {                                                             \
1075     if (debug_dump && (C))                                      \
1076       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1077   }
1078 #else  /* !DEBUG_AARCH64 */
1079 #define DEBUG_TRACE(M, ...) ;
1080 #define DEBUG_TRACE_IF(C, M, ...) ;
1081 #endif /* DEBUG_AARCH64 */
1082
1083 extern const char *const aarch64_sve_pattern_array[32];
1084 extern const char *const aarch64_sve_prfop_array[16];
1085
1086 #ifdef __cplusplus
1087 }
1088 #endif
1089
1090 #endif /* OPCODE_AARCH64_H */