include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65
  66 /* Architectures are the sum of the base and extensions.  */
  67 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  68                                                  AARCH64_FEATURE_FP  \
  69                                                  | AARCH64_FEATURE_SIMD)
  70 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  71                                                  AARCH64_FEATURE_CRC    \
  72                                                  | AARCH64_FEATURE_V8_1 \
  73                                                  | AARCH64_FEATURE_LSE  \
  74                                                  | AARCH64_FEATURE_PAN  \
  75                                                  | AARCH64_FEATURE_LOR  \
  76                                                  | AARCH64_FEATURE_RDMA)
  77 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  78                                                  AARCH64_FEATURE_V8_2   \
  79                                                  | AARCH64_FEATURE_RAS)
  80 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  81                                                  AARCH64_FEATURE_V8_3   \
  82                                                  | AARCH64_FEATURE_RCPC \
  83                                                  | AARCH64_FEATURE_COMPNUM)
  84 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
  85                                                  AARCH64_FEATURE_V8_4   \
  86                                                  | AARCH64_FEATURE_DOTPROD \
  87                                                  | AARCH64_FEATURE_F16_FML)
  88
  89 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  90 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  91
  92 /* CPU-specific features.  */
  93 typedef unsigned long long aarch64_feature_set;
  94
  95 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  96   ((~(CPU) & (FEAT)) == 0)
  97
  98 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  99   (((CPU) & (FEAT)) != 0)
 100
 101 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 102   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 103
 104 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 105   do                                            \
 106     {                                           \
 107       (TARG) = (F1) | (F2);                     \
 108     }                                           \
 109   while (0)
 110
 111 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 112   do                                            \
 113     {                                           \
 114       (TARG) = (F1) &~ (F2);                    \
 115     }                                           \
 116   while (0)
 117
 118 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 119
 120 enum aarch64_operand_class
 121 {
 122   AARCH64_OPND_CLASS_NIL,
 123   AARCH64_OPND_CLASS_INT_REG,
 124   AARCH64_OPND_CLASS_MODIFIED_REG,
 125   AARCH64_OPND_CLASS_FP_REG,
 126   AARCH64_OPND_CLASS_SIMD_REG,
 127   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 128   AARCH64_OPND_CLASS_SISD_REG,
 129   AARCH64_OPND_CLASS_SIMD_REGLIST,
 130   AARCH64_OPND_CLASS_SVE_REG,
 131   AARCH64_OPND_CLASS_PRED_REG,
 132   AARCH64_OPND_CLASS_ADDRESS,
 133   AARCH64_OPND_CLASS_IMMEDIATE,
 134   AARCH64_OPND_CLASS_SYSTEM,
 135   AARCH64_OPND_CLASS_COND,
 136 };
 137
 138 /* Operand code that helps both parsing and coding.
 139    Keep AARCH64_OPERANDS synced.  */
 140
 141 enum aarch64_opnd
 142 {
 143   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 144
 145   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 146   AARCH64_OPND_Rn,      /* Integer register as source.  */
 147   AARCH64_OPND_Rm,      /* Integer register as source.  */
 148   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 149   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 150   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 151   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 152   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 153
 154   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 155   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 156   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 157   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 158   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 159   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 160
 161   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 162   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 163   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 164   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 165   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 166   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 167
 168   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 169   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 170   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 171
 172   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 173   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 174   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 175   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 176   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 177   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 178   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 179   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 180   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 181   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 182                            qualifier is S_H.  */
 183   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 184   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 185   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 186                            structure to all lanes.  */
 187   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 188
 189   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 190   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 191
 192   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 193   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 194   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 195   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 196   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 197   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 198   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 199   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 200                            (no encoding).  */
 201   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 202   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 203   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 204   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 205   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 206   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 207   AARCH64_OPND_IMM,     /* Immediate.  */
 208   AARCH64_OPND_IMM_2,   /* Immediate.  */
 209   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 210   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 211   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 212   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 213   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 214   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 215   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 216   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 217   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 218                            each condition flag.  */
 219
 220   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 221   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 222   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 223   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 224   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 225   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 226   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 227   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 228
 229   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 230   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 231
 232   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 233   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 234   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 235   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 236   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 237
 238   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 239   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 240   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 241   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 242   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 243                                    negative or unaligned and there is
 244                                    no writeback allowed.  This operand code
 245                                    is only used to support the programmer-
 246                                    friendly feature of using LDR/STR as the
 247                                    the mnemonic name for LDUR/STUR instructions
 248                                    wherever there is no ambiguity.  */
 249   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 250   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 251   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 252   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 253   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 254
 255   AARCH64_OPND_SYSREG,          /* System register operand.  */
 256   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 257   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 258   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 259   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 260   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 261   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 262   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 263   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 264   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 265
 266   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 267   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 268   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 269   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 270   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 271   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 272   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 273   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 274   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 275   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 276   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 277   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 278   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 279   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 280   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 281   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 282   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 283   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 284   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 285   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 286   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 287   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 288   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 289   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 290   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 291                                        Bit 14 controls S/U choice.  */
 292   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 293                                        Bit 22 controls S/U choice.  */
 294   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 295                                        Bit 14 controls S/U choice.  */
 296   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 297                                        Bit 22 controls S/U choice.  */
 298   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 299                                        Bit 14 controls S/U choice.  */
 300   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 301                                        Bit 22 controls S/U choice.  */
 302   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 303                                        Bit 14 controls S/U choice.  */
 304   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 305                                        Bit 22 controls S/U choice.  */
 306   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 307   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 308   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 309   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 310   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 311   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 312   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 313   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 314   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 315   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 316   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 317   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 318   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 319   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 320   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 321   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 322   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 323   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 324   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 325   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 326   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 327   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 328   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 329   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 330   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 331   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 332   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 333   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 334   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 335   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 336   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 337   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 338   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 339   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 340   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 341   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 342   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 343   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 344   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 345   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 346   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 347   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 348   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 349   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 350   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 351   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 352   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 353   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 354   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 355   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 356   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 357   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 358   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 359   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 360   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 361   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 362   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 363   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 364   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 365   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 366   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 367 };
 368
 369 /* Qualifier constrains an operand.  It either specifies a variant of an
 370    operand type or limits values available to an operand type.
 371
 372    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 373
 374 enum aarch64_opnd_qualifier
 375 {
 376   /* Indicating no further qualification on an operand.  */
 377   AARCH64_OPND_QLF_NIL,
 378
 379   /* Qualifying an operand which is a general purpose (integer) register;
 380      indicating the operand data size or a specific register.  */
 381   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 382   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 383   AARCH64_OPND_QLF_WSP, /* WSP.  */
 384   AARCH64_OPND_QLF_SP,  /* SP.  */
 385
 386   /* Qualifying an operand which is a floating-point register, a SIMD
 387      vector element or a SIMD vector element list; indicating operand data
 388      size or the size of each SIMD vector element in the case of a SIMD
 389      vector element list.
 390      These qualifiers are also used to qualify an address operand to
 391      indicate the size of data element a load/store instruction is
 392      accessing.
 393      They are also used for the immediate shift operand in e.g. SSHR.  Such
 394      a use is only for the ease of operand encoding/decoding and qualifier
 395      sequence matching; such a use should not be applied widely; use the value
 396      constraint qualifiers for immediate operands wherever possible.  */
 397   AARCH64_OPND_QLF_S_B,
 398   AARCH64_OPND_QLF_S_H,
 399   AARCH64_OPND_QLF_S_S,
 400   AARCH64_OPND_QLF_S_D,
 401   AARCH64_OPND_QLF_S_Q,
 402   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 403      are selected by the instruction.  Other than that it has no difference
 404      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 405      reasons and is an exception from normal AArch64 disassembly scheme.  */
 406   AARCH64_OPND_QLF_S_4B,
 407
 408   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 409      register list; indicating register shape.
 410      They are also used for the immediate shift operand in e.g. SSHR.  Such
 411      a use is only for the ease of operand encoding/decoding and qualifier
 412      sequence matching; such a use should not be applied widely; use the value
 413      constraint qualifiers for immediate operands wherever possible.  */
 414   AARCH64_OPND_QLF_V_4B,
 415   AARCH64_OPND_QLF_V_8B,
 416   AARCH64_OPND_QLF_V_16B,
 417   AARCH64_OPND_QLF_V_2H,
 418   AARCH64_OPND_QLF_V_4H,
 419   AARCH64_OPND_QLF_V_8H,
 420   AARCH64_OPND_QLF_V_2S,
 421   AARCH64_OPND_QLF_V_4S,
 422   AARCH64_OPND_QLF_V_1D,
 423   AARCH64_OPND_QLF_V_2D,
 424   AARCH64_OPND_QLF_V_1Q,
 425
 426   AARCH64_OPND_QLF_P_Z,
 427   AARCH64_OPND_QLF_P_M,
 428
 429   /* Constraint on value.  */
 430   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 431   AARCH64_OPND_QLF_imm_0_7,
 432   AARCH64_OPND_QLF_imm_0_15,
 433   AARCH64_OPND_QLF_imm_0_31,
 434   AARCH64_OPND_QLF_imm_0_63,
 435   AARCH64_OPND_QLF_imm_1_32,
 436   AARCH64_OPND_QLF_imm_1_64,
 437
 438   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 439      or shift-ones.  */
 440   AARCH64_OPND_QLF_LSL,
 441   AARCH64_OPND_QLF_MSL,
 442
 443   /* Special qualifier helping retrieve qualifier information during the
 444      decoding time (currently not in use).  */
 445   AARCH64_OPND_QLF_RETRIEVE,
 446 };
 447 \f
 448 /* Instruction class.  */
 449
 450 enum aarch64_insn_class
 451 {
 452   addsub_carry,
 453   addsub_ext,
 454   addsub_imm,
 455   addsub_shift,
 456   asimdall,
 457   asimddiff,
 458   asimdelem,
 459   asimdext,
 460   asimdimm,
 461   asimdins,
 462   asimdmisc,
 463   asimdperm,
 464   asimdsame,
 465   asimdshf,
 466   asimdtbl,
 467   asisddiff,
 468   asisdelem,
 469   asisdlse,
 470   asisdlsep,
 471   asisdlso,
 472   asisdlsop,
 473   asisdmisc,
 474   asisdone,
 475   asisdpair,
 476   asisdsame,
 477   asisdshf,
 478   bitfield,
 479   branch_imm,
 480   branch_reg,
 481   compbranch,
 482   condbranch,
 483   condcmp_imm,
 484   condcmp_reg,
 485   condsel,
 486   cryptoaes,
 487   cryptosha2,
 488   cryptosha3,
 489   dp_1src,
 490   dp_2src,
 491   dp_3src,
 492   exception,
 493   extract,
 494   float2fix,
 495   float2int,
 496   floatccmp,
 497   floatcmp,
 498   floatdp1,
 499   floatdp2,
 500   floatdp3,
 501   floatimm,
 502   floatsel,
 503   ldst_immpost,
 504   ldst_immpre,
 505   ldst_imm9,    /* immpost or immpre */
 506   ldst_imm10,   /* LDRAA/LDRAB */
 507   ldst_pos,
 508   ldst_regoff,
 509   ldst_unpriv,
 510   ldst_unscaled,
 511   ldstexcl,
 512   ldstnapair_offs,
 513   ldstpair_off,
 514   ldstpair_indexed,
 515   loadlit,
 516   log_imm,
 517   log_shift,
 518   lse_atomic,
 519   movewide,
 520   pcreladdr,
 521   ic_system,
 522   sve_cpy,
 523   sve_index,
 524   sve_limm,
 525   sve_misc,
 526   sve_movprfx,
 527   sve_pred_zm,
 528   sve_shift_pred,
 529   sve_shift_unpred,
 530   sve_size_bhs,
 531   sve_size_bhsd,
 532   sve_size_hsd,
 533   sve_size_sd,
 534   testbranch,
 535   cryptosm3,
 536   cryptosm4,
 537   dotproduct,
 538 };
 539
 540 /* Opcode enumerators.  */
 541
 542 enum aarch64_op
 543 {
 544   OP_NIL,
 545   OP_STRB_POS,
 546   OP_LDRB_POS,
 547   OP_LDRSB_POS,
 548   OP_STRH_POS,
 549   OP_LDRH_POS,
 550   OP_LDRSH_POS,
 551   OP_STR_POS,
 552   OP_LDR_POS,
 553   OP_STRF_POS,
 554   OP_LDRF_POS,
 555   OP_LDRSW_POS,
 556   OP_PRFM_POS,
 557
 558   OP_STURB,
 559   OP_LDURB,
 560   OP_LDURSB,
 561   OP_STURH,
 562   OP_LDURH,
 563   OP_LDURSH,
 564   OP_STUR,
 565   OP_LDUR,
 566   OP_STURV,
 567   OP_LDURV,
 568   OP_LDURSW,
 569   OP_PRFUM,
 570
 571   OP_LDR_LIT,
 572   OP_LDRV_LIT,
 573   OP_LDRSW_LIT,
 574   OP_PRFM_LIT,
 575
 576   OP_ADD,
 577   OP_B,
 578   OP_BL,
 579
 580   OP_MOVN,
 581   OP_MOVZ,
 582   OP_MOVK,
 583
 584   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 585   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 586   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 587
 588   OP_MOV_V,             /* MOV alias for moving vector register.  */
 589
 590   OP_ASR_IMM,
 591   OP_LSR_IMM,
 592   OP_LSL_IMM,
 593
 594   OP_BIC,
 595
 596   OP_UBFX,
 597   OP_BFXIL,
 598   OP_SBFX,
 599   OP_SBFIZ,
 600   OP_BFI,
 601   OP_BFC,               /* ARMv8.2.  */
 602   OP_UBFIZ,
 603   OP_UXTB,
 604   OP_UXTH,
 605   OP_UXTW,
 606
 607   OP_CINC,
 608   OP_CINV,
 609   OP_CNEG,
 610   OP_CSET,
 611   OP_CSETM,
 612
 613   OP_FCVT,
 614   OP_FCVTN,
 615   OP_FCVTN2,
 616   OP_FCVTL,
 617   OP_FCVTL2,
 618   OP_FCVTXN_S,          /* Scalar version.  */
 619
 620   OP_ROR_IMM,
 621
 622   OP_SXTL,
 623   OP_SXTL2,
 624   OP_UXTL,
 625   OP_UXTL2,
 626
 627   OP_MOV_P_P,
 628   OP_MOV_Z_P_Z,
 629   OP_MOV_Z_V,
 630   OP_MOV_Z_Z,
 631   OP_MOV_Z_Zi,
 632   OP_MOVM_P_P_P,
 633   OP_MOVS_P_P,
 634   OP_MOVZS_P_P_P,
 635   OP_MOVZ_P_P_P,
 636   OP_NOTS_P_P_P_Z,
 637   OP_NOT_P_P_P_Z,
 638
 639   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 640
 641   OP_TOTAL_NUM,         /* Pseudo.  */
 642 };
 643
 644 /* Maximum number of operands an instruction can have.  */
 645 #define AARCH64_MAX_OPND_NUM 6
 646 /* Maximum number of qualifier sequences an instruction can have.  */
 647 #define AARCH64_MAX_QLF_SEQ_NUM 10
 648 /* Operand qualifier typedef; optimized for the size.  */
 649 typedef unsigned char aarch64_opnd_qualifier_t;
 650 /* Operand qualifier sequence typedef.  */
 651 typedef aarch64_opnd_qualifier_t        \
 652           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 653
 654 /* FIXME: improve the efficiency.  */
 655 static inline bfd_boolean
 656 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 657 {
 658   int i;
 659   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 660     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 661       return FALSE;
 662   return TRUE;
 663 }
 664
 665 /*  Forward declare error reporting type.  */
 666 typedef struct aarch64_operand_error aarch64_operand_error;
 667 /* Forward declare instruction sequence type.  */
 668 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 669 /* Forward declare instruction definition.  */
 670 typedef struct aarch64_inst aarch64_inst;
 671
 672 /* This structure holds information for a particular opcode.  */
 673
 674 struct aarch64_opcode
 675 {
 676   /* The name of the mnemonic.  */
 677   const char *name;
 678
 679   /* The opcode itself.  Those bits which will be filled in with
 680      operands are zeroes.  */
 681   aarch64_insn opcode;
 682
 683   /* The opcode mask.  This is used by the disassembler.  This is a
 684      mask containing ones indicating those bits which must match the
 685      opcode field, and zeroes indicating those bits which need not
 686      match (and are presumably filled in by operands).  */
 687   aarch64_insn mask;
 688
 689   /* Instruction class.  */
 690   enum aarch64_insn_class iclass;
 691
 692   /* Enumerator identifier.  */
 693   enum aarch64_op op;
 694
 695   /* Which architecture variant provides this instruction.  */
 696   const aarch64_feature_set *avariant;
 697
 698   /* An array of operand codes.  Each code is an index into the
 699      operand table.  They appear in the order which the operands must
 700      appear in assembly code, and are terminated by a zero.  */
 701   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 702
 703   /* A list of operand qualifier code sequence.  Each operand qualifier
 704      code qualifies the corresponding operand code.  Each operand
 705      qualifier sequence specifies a valid opcode variant and related
 706      constraint on operands.  */
 707   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 708
 709   /* Flags providing information about this instruction */
 710   uint64_t flags;
 711
 712   /* Extra constraints on the instruction that the verifier checks.  */
 713   uint32_t constraints;
 714
 715   /* If nonzero, this operand and operand 0 are both registers and
 716      are required to have the same register number.  */
 717   unsigned char tied_operand;
 718
 719   /* If non-NULL, a function to verify that a given instruction is valid.  */
 720   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 721 };
 722
 723 typedef struct aarch64_opcode aarch64_opcode;
 724
 725 /* Table describing all the AArch64 opcodes.  */
 726 extern aarch64_opcode aarch64_opcode_table[];
 727
 728 /* Opcode flags.  */
 729 #define F_ALIAS (1 << 0)
 730 #define F_HAS_ALIAS (1 << 1)
 731 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 732    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 733 #define F_P1 (1 << 2)
 734 #define F_P2 (2 << 2)
 735 #define F_P3 (3 << 2)
 736 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 737 #define F_COND (1 << 4)
 738 /* Instruction has the field of 'sf'.  */
 739 #define F_SF (1 << 5)
 740 /* Instruction has the field of 'size:Q'.  */
 741 #define F_SIZEQ (1 << 6)
 742 /* Floating-point instruction has the field of 'type'.  */
 743 #define F_FPTYPE (1 << 7)
 744 /* AdvSIMD scalar instruction has the field of 'size'.  */
 745 #define F_SSIZE (1 << 8)
 746 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 747 #define F_T (1 << 9)
 748 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 749 #define F_GPRSIZE_IN_Q (1 << 10)
 750 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 751 #define F_LDS_SIZE (1 << 11)
 752 /* Optional operand; assume maximum of 1 operand can be optional.  */
 753 #define F_OPD0_OPT (1 << 12)
 754 #define F_OPD1_OPT (2 << 12)
 755 #define F_OPD2_OPT (3 << 12)
 756 #define F_OPD3_OPT (4 << 12)
 757 #define F_OPD4_OPT (5 << 12)
 758 /* Default value for the optional operand when omitted from the assembly.  */
 759 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 760 /* Instruction that is an alias of another instruction needs to be
 761    encoded/decoded by converting it to/from the real form, followed by
 762    the encoding/decoding according to the rules of the real opcode.
 763    This compares to the direct coding using the alias's information.
 764    N.B. this flag requires F_ALIAS to be used together.  */
 765 #define F_CONV (1 << 20)
 766 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 767    friendly pseudo instruction available only in the assembly code (thus will
 768    not show up in the disassembly).  */
 769 #define F_PSEUDO (1 << 21)
 770 /* Instruction has miscellaneous encoding/decoding rules.  */
 771 #define F_MISC (1 << 22)
 772 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 773 #define F_N (1 << 23)
 774 /* Opcode dependent field.  */
 775 #define F_OD(X) (((X) & 0x7) << 24)
 776 /* Instruction has the field of 'sz'.  */
 777 #define F_LSE_SZ (1 << 27)
 778 /* Require an exact qualifier match, even for NIL qualifiers.  */
 779 #define F_STRICT (1ULL << 28)
 780 /* This system instruction is used to read system registers.  */
 781 #define F_SYS_READ (1ULL << 29)
 782 /* This system instruction is used to write system registers.  */
 783 #define F_SYS_WRITE (1ULL << 30)
 784 /* This instruction has an extra constraint on it that imposes a requirement on
 785    subsequent instructions.  */
 786 #define F_SCAN (1ULL << 31)
 787 /* Next bit is 32.  */
 788
 789 /* Instruction constraints.  */
 790 /* This instruction has a predication constraint on the instruction at PC+4.  */
 791 #define C_SCAN_MOVPRFX (1U << 0)
 792 /* This instruction's operation width is determined by the operand with the
 793    largest element size.  */
 794 #define C_MAX_ELEM (1U << 1)
 795 /* Next bit is 2.  */
 796
 797 static inline bfd_boolean
 798 alias_opcode_p (const aarch64_opcode *opcode)
 799 {
 800   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 801 }
 802
 803 static inline bfd_boolean
 804 opcode_has_alias (const aarch64_opcode *opcode)
 805 {
 806   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 807 }
 808
 809 /* Priority for disassembling preference.  */
 810 static inline int
 811 opcode_priority (const aarch64_opcode *opcode)
 812 {
 813   return (opcode->flags >> 2) & 0x3;
 814 }
 815
 816 static inline bfd_boolean
 817 pseudo_opcode_p (const aarch64_opcode *opcode)
 818 {
 819   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 820 }
 821
 822 static inline bfd_boolean
 823 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 824 {
 825   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 826     ? TRUE : FALSE;
 827 }
 828
 829 static inline aarch64_insn
 830 get_optional_operand_default_value (const aarch64_opcode *opcode)
 831 {
 832   return (opcode->flags >> 15) & 0x1f;
 833 }
 834
 835 static inline unsigned int
 836 get_opcode_dependent_value (const aarch64_opcode *opcode)
 837 {
 838   return (opcode->flags >> 24) & 0x7;
 839 }
 840
 841 static inline bfd_boolean
 842 opcode_has_special_coder (const aarch64_opcode *opcode)
 843 {
 844   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 845           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 846     : FALSE;
 847 }
 848 \f
 849 struct aarch64_name_value_pair
 850 {
 851   const char *  name;
 852   aarch64_insn  value;
 853 };
 854
 855 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 856 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 857 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 858 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 859
 860 typedef struct
 861 {
 862   const char *  name;
 863   aarch64_insn  value;
 864   uint32_t      flags;
 865 } aarch64_sys_reg;
 866
 867 extern const aarch64_sys_reg aarch64_sys_regs [];
 868 extern const aarch64_sys_reg aarch64_pstatefields [];
 869 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 870 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 871                                                 const aarch64_sys_reg *);
 872 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 873                                                     const aarch64_sys_reg *);
 874
 875 typedef struct
 876 {
 877   const char *name;
 878   uint32_t value;
 879   uint32_t flags ;
 880 } aarch64_sys_ins_reg;
 881
 882 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 883 extern bfd_boolean
 884 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 885                                  const aarch64_sys_ins_reg *);
 886
 887 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 888 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 889 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 890 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 891
 892 /* Shift/extending operator kinds.
 893    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 894 enum aarch64_modifier_kind
 895 {
 896   AARCH64_MOD_NONE,
 897   AARCH64_MOD_MSL,
 898   AARCH64_MOD_ROR,
 899   AARCH64_MOD_ASR,
 900   AARCH64_MOD_LSR,
 901   AARCH64_MOD_LSL,
 902   AARCH64_MOD_UXTB,
 903   AARCH64_MOD_UXTH,
 904   AARCH64_MOD_UXTW,
 905   AARCH64_MOD_UXTX,
 906   AARCH64_MOD_SXTB,
 907   AARCH64_MOD_SXTH,
 908   AARCH64_MOD_SXTW,
 909   AARCH64_MOD_SXTX,
 910   AARCH64_MOD_MUL,
 911   AARCH64_MOD_MUL_VL,
 912 };
 913
 914 bfd_boolean
 915 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 916
 917 enum aarch64_modifier_kind
 918 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 919 /* Condition.  */
 920
 921 typedef struct
 922 {
 923   /* A list of names with the first one as the disassembly preference;
 924      terminated by NULL if fewer than 3.  */
 925   const char *names[4];
 926   aarch64_insn value;
 927 } aarch64_cond;
 928
 929 extern const aarch64_cond aarch64_conds[16];
 930
 931 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 932 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 933 \f
 934 /* Structure representing an operand.  */
 935
 936 struct aarch64_opnd_info
 937 {
 938   enum aarch64_opnd type;
 939   aarch64_opnd_qualifier_t qualifier;
 940   int idx;
 941
 942   union
 943     {
 944       struct
 945         {
 946           unsigned regno;
 947         } reg;
 948       struct
 949         {
 950           unsigned int regno;
 951           int64_t index;
 952         } reglane;
 953       /* e.g. LVn.  */
 954       struct
 955         {
 956           unsigned first_regno : 5;
 957           unsigned num_regs : 3;
 958           /* 1 if it is a list of reg element.  */
 959           unsigned has_index : 1;
 960           /* Lane index; valid only when has_index is 1.  */
 961           int64_t index;
 962         } reglist;
 963       /* e.g. immediate or pc relative address offset.  */
 964       struct
 965         {
 966           int64_t value;
 967           unsigned is_fp : 1;
 968         } imm;
 969       /* e.g. address in STR (register offset).  */
 970       struct
 971         {
 972           unsigned base_regno;
 973           struct
 974             {
 975               union
 976                 {
 977                   int imm;
 978                   unsigned regno;
 979                 };
 980               unsigned is_reg;
 981             } offset;
 982           unsigned pcrel : 1;           /* PC-relative.  */
 983           unsigned writeback : 1;
 984           unsigned preind : 1;          /* Pre-indexed.  */
 985           unsigned postind : 1;         /* Post-indexed.  */
 986         } addr;
 987
 988       struct
 989         {
 990           /* The encoding of the system register.  */
 991           aarch64_insn value;
 992
 993           /* The system register flags.  */
 994           uint32_t flags;
 995         } sysreg;
 996
 997       const aarch64_cond *cond;
 998       /* The encoding of the PSTATE field.  */
 999       aarch64_insn pstatefield;
1000       const aarch64_sys_ins_reg *sysins_op;
1001       const struct aarch64_name_value_pair *barrier;
1002       const struct aarch64_name_value_pair *hint_option;
1003       const struct aarch64_name_value_pair *prfop;
1004     };
1005
1006   /* Operand shifter; in use when the operand is a register offset address,
1007      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1008   struct
1009     {
1010       enum aarch64_modifier_kind kind;
1011       unsigned operator_present: 1;     /* Only valid during encoding.  */
1012       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1013       unsigned amount_present: 1;
1014       int64_t amount;
1015     } shifter;
1016
1017   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1018                            to be done on it.  In some (but not all) of these
1019                            cases, we need to tell libopcodes to skip the
1020                            constraint checking and the encoding for this
1021                            operand, so that the libopcodes can pick up the
1022                            right opcode before the operand is fixed-up.  This
1023                            flag should only be used during the
1024                            assembling/encoding.  */
1025   unsigned present:1;   /* Whether this operand is present in the assembly
1026                            line; not used during the disassembly.  */
1027 };
1028
1029 typedef struct aarch64_opnd_info aarch64_opnd_info;
1030
1031 /* Structure representing an instruction.
1032
1033    It is used during both the assembling and disassembling.  The assembler
1034    fills an aarch64_inst after a successful parsing and then passes it to the
1035    encoding routine to do the encoding.  During the disassembling, the
1036    disassembler calls the decoding routine to decode a binary instruction; on a
1037    successful return, such a structure will be filled with information of the
1038    instruction; then the disassembler uses the information to print out the
1039    instruction.  */
1040
1041 struct aarch64_inst
1042 {
1043   /* The value of the binary instruction.  */
1044   aarch64_insn value;
1045
1046   /* Corresponding opcode entry.  */
1047   const aarch64_opcode *opcode;
1048
1049   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1050   const aarch64_cond *cond;
1051
1052   /* Operands information.  */
1053   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1054 };
1055
1056 typedef struct aarch64_inst aarch64_inst;
1057 \f
1058 /* Diagnosis related declaration and interface.  */
1059
1060 /* Operand error kind enumerators.
1061
1062    AARCH64_OPDE_RECOVERABLE
1063      Less severe error found during the parsing, very possibly because that
1064      GAS has picked up a wrong instruction template for the parsing.
1065
1066    AARCH64_OPDE_SYNTAX_ERROR
1067      General syntax error; it can be either a user error, or simply because
1068      that GAS is trying a wrong instruction template.
1069
1070    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1071      Definitely a user syntax error.
1072
1073    AARCH64_OPDE_INVALID_VARIANT
1074      No syntax error, but the operands are not a valid combination, e.g.
1075      FMOV D0,S0
1076
1077    AARCH64_OPDE_UNTIED_OPERAND
1078      The asm failed to use the same register for a destination operand
1079      and a tied source operand.
1080
1081    AARCH64_OPDE_OUT_OF_RANGE
1082      Error about some immediate value out of a valid range.
1083
1084    AARCH64_OPDE_UNALIGNED
1085      Error about some immediate value not properly aligned (i.e. not being a
1086      multiple times of a certain value).
1087
1088    AARCH64_OPDE_REG_LIST
1089      Error about the register list operand having unexpected number of
1090      registers.
1091
1092    AARCH64_OPDE_OTHER_ERROR
1093      Error of the highest severity and used for any severe issue that does not
1094      fall into any of the above categories.
1095
1096    The enumerators are only interesting to GAS.  They are declared here (in
1097    libopcodes) because that some errors are detected (and then notified to GAS)
1098    by libopcodes (rather than by GAS solely).
1099
1100    The first three errors are only deteced by GAS while the
1101    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1102    only libopcodes has the information about the valid variants of each
1103    instruction.
1104
1105    The enumerators have an increasing severity.  This is helpful when there are
1106    multiple instruction templates available for a given mnemonic name (e.g.
1107    FMOV); this mechanism will help choose the most suitable template from which
1108    the generated diagnostics can most closely describe the issues, if any.  */
1109
1110 enum aarch64_operand_error_kind
1111 {
1112   AARCH64_OPDE_NIL,
1113   AARCH64_OPDE_RECOVERABLE,
1114   AARCH64_OPDE_SYNTAX_ERROR,
1115   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1116   AARCH64_OPDE_INVALID_VARIANT,
1117   AARCH64_OPDE_UNTIED_OPERAND,
1118   AARCH64_OPDE_OUT_OF_RANGE,
1119   AARCH64_OPDE_UNALIGNED,
1120   AARCH64_OPDE_REG_LIST,
1121   AARCH64_OPDE_OTHER_ERROR
1122 };
1123
1124 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1125 struct aarch64_operand_error
1126 {
1127   enum aarch64_operand_error_kind kind;
1128   int index;
1129   const char *error;
1130   int data[3];  /* Some data for extra information.  */
1131   bfd_boolean non_fatal;
1132 };
1133
1134 /* AArch64 sequence structure used to track instructions with F_SCAN
1135    dependencies for both assembler and disassembler.  */
1136 struct aarch64_instr_sequence
1137 {
1138   /* The instruction that caused this sequence to be opened.  */
1139   aarch64_inst *instr;
1140   /* The number of instructions the above instruction allows to be kept in the
1141      sequence before an automatic close is done.  */
1142   int num_insns;
1143   /* The instructions currently added to the sequence.  */
1144   aarch64_inst **current_insns;
1145   /* The number of instructions already in the sequence.  */
1146   int next_insn;
1147 };
1148
1149 /* Encoding entrypoint.  */
1150
1151 extern int
1152 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1153                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1154                        aarch64_operand_error *, aarch64_instr_sequence *);
1155
1156 extern const aarch64_opcode *
1157 aarch64_replace_opcode (struct aarch64_inst *,
1158                         const aarch64_opcode *);
1159
1160 /* Given the opcode enumerator OP, return the pointer to the corresponding
1161    opcode entry.  */
1162
1163 extern const aarch64_opcode *
1164 aarch64_get_opcode (enum aarch64_op);
1165
1166 /* Generate the string representation of an operand.  */
1167 extern void
1168 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1169                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1170                        char **);
1171
1172 /* Miscellaneous interface.  */
1173
1174 extern int
1175 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1176
1177 extern aarch64_opnd_qualifier_t
1178 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1179                                 const aarch64_opnd_qualifier_t, int);
1180
1181 extern int
1182 aarch64_num_of_operands (const aarch64_opcode *);
1183
1184 extern int
1185 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1186
1187 extern int
1188 aarch64_zero_register_p (const aarch64_opnd_info *);
1189
1190 extern int
1191 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1192                      aarch64_operand_error *errors);
1193
1194 /* Given an operand qualifier, return the expected data element size
1195    of a qualified operand.  */
1196 extern unsigned char
1197 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1198
1199 extern enum aarch64_operand_class
1200 aarch64_get_operand_class (enum aarch64_opnd);
1201
1202 extern const char *
1203 aarch64_get_operand_name (enum aarch64_opnd);
1204
1205 extern const char *
1206 aarch64_get_operand_desc (enum aarch64_opnd);
1207
1208 extern bfd_boolean
1209 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1210
1211 #ifdef DEBUG_AARCH64
1212 extern int debug_dump;
1213
1214 extern void
1215 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1216
1217 #define DEBUG_TRACE(M, ...)                                     \
1218   {                                                             \
1219     if (debug_dump)                                             \
1220       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1221   }
1222
1223 #define DEBUG_TRACE_IF(C, M, ...)                               \
1224   {                                                             \
1225     if (debug_dump && (C))                                      \
1226       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1227   }
1228 #else  /* !DEBUG_AARCH64 */
1229 #define DEBUG_TRACE(M, ...) ;
1230 #define DEBUG_TRACE_IF(C, M, ...) ;
1231 #endif /* DEBUG_AARCH64 */
1232
1233 extern const char *const aarch64_sve_pattern_array[32];
1234 extern const char *const aarch64_sve_prfop_array[16];
1235
1236 #ifdef __cplusplus
1237 }
1238 #endif
1239
1240 #endif /* OPCODE_AARCH64_H */