include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2020 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8           (1ULL << 0) /* All processors.  */
  41 #define AARCH64_FEATURE_V8_6         (1ULL << 1) /* ARMv8.6 processors.  */
  42 #define AARCH64_FEATURE_BFLOAT16     (1ULL << 2) /* Bfloat16 insns.  */
  43 #define AARCH64_FEATURE_V8_A         (1ULL << 3) /* Armv8-A processors.  */
  44 #define AARCH64_FEATURE_SVE2         (1ULL << 4) /* SVE2 instructions.  */
  45 #define AARCH64_FEATURE_V8_2         (1ULL << 5) /* ARMv8.2 processors.  */
  46 #define AARCH64_FEATURE_V8_3         (1ULL << 6) /* ARMv8.3 processors.  */
  47 #define AARCH64_FEATURE_SVE2_AES     (1ULL << 7)
  48 #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
  49 #define AARCH64_FEATURE_SVE2_SM4     (1ULL << 9)
  50 #define AARCH64_FEATURE_SVE2_SHA3    (1ULL << 10)
  51 #define AARCH64_FEATURE_V8_4         (1ULL << 11) /* ARMv8.4 processors.  */
  52 #define AARCH64_FEATURE_V8_R         (1ULL << 12) /* Armv8-R processors.  */
  53 #define AARCH64_FEATURE_V8_7         (1ULL << 13) /* Armv8.7 processors.  */
  54 #define AARCH64_FEATURE_FP           (1ULL << 17) /* FP instructions.  */
  55 #define AARCH64_FEATURE_SIMD         (1ULL << 18) /* SIMD instructions.  */
  56 #define AARCH64_FEATURE_CRC          (1ULL << 19) /* CRC instructions.  */
  57 #define AARCH64_FEATURE_LSE          (1ULL << 20) /* LSE instructions.  */
  58 #define AARCH64_FEATURE_PAN          (1ULL << 21) /* PAN instructions.  */
  59 #define AARCH64_FEATURE_LOR          (1ULL << 22) /* LOR instructions.  */
  60 #define AARCH64_FEATURE_RDMA         (1ULL << 23) /* v8.1 SIMD instructions.  */
  61 #define AARCH64_FEATURE_V8_1         (1ULL << 24) /* v8.1 features.  */
  62 #define AARCH64_FEATURE_F16          (1ULL << 25) /* v8.2 FP16 instructions.  */
  63 #define AARCH64_FEATURE_RAS          (1ULL << 26) /* RAS Extensions.  */
  64 #define AARCH64_FEATURE_PROFILE      (1ULL << 27) /* Statistical Profiling.  */
  65 #define AARCH64_FEATURE_SVE          (1ULL << 28) /* SVE instructions.  */
  66 #define AARCH64_FEATURE_RCPC         (1ULL << 29) /* RCPC instructions.  */
  67 #define AARCH64_FEATURE_COMPNUM      (1ULL << 30) /* Complex # instructions.  */
  68 #define AARCH64_FEATURE_DOTPROD      (1ULL << 31) /* Dot Product instructions.  */
  69 #define AARCH64_FEATURE_SM4          (1ULL << 32) /* SM3 & SM4 instructions.  */
  70 #define AARCH64_FEATURE_SHA2         (1ULL << 33) /* SHA2 instructions.  */
  71 #define AARCH64_FEATURE_SHA3         (1ULL << 34) /* SHA3 instructions.  */
  72 #define AARCH64_FEATURE_AES          (1ULL << 35) /* AES instructions.  */
  73 #define AARCH64_FEATURE_F16_FML      (1ULL << 36) /* v8.2 FP16FML ins.  */
  74 #define AARCH64_FEATURE_V8_5         (1ULL << 37) /* ARMv8.5 processors.  */
  75 #define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* Flag Manipulation insns.  */
  76 #define AARCH64_FEATURE_FRINTTS      (1ULL << 39) /* FRINT[32,64][Z,X] insns.  */
  77 #define AARCH64_FEATURE_SB           (1ULL << 40) /* SB instruction.  */
  78 #define AARCH64_FEATURE_PREDRES      (1ULL << 41) /* Execution and Data Prediction Restriction instructions.  */
  79 #define AARCH64_FEATURE_CVADP        (1ULL << 42) /* DC CVADP.  */
  80 #define AARCH64_FEATURE_RNG          (1ULL << 43) /* Random Number instructions.  */
  81 #define AARCH64_FEATURE_BTI          (1ULL << 44) /* BTI instructions.  */
  82 #define AARCH64_FEATURE_SCXTNUM      (1ULL << 45) /* SCXTNUM_ELx.  */
  83 #define AARCH64_FEATURE_ID_PFR2      (1ULL << 46) /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_SSBS         (1ULL << 47) /* SSBS mechanism enabled.  */
  85 #define AARCH64_FEATURE_MEMTAG       (1ULL << 48) /* Memory Tagging Extension.  */
  86 #define AARCH64_FEATURE_TME          (1ULL << 49) /* Transactional Memory Extension.  */
  87 #define AARCH64_FEATURE_I8MM         (1ULL << 52) /* Matrix Multiply instructions.  */
  88 #define AARCH64_FEATURE_F32MM        (1ULL << 53)
  89 #define AARCH64_FEATURE_F64MM        (1ULL << 54)
  90
  91 /* Crypto instructions are the combination of AES and SHA2.  */
  92 #define AARCH64_FEATURE_CRYPTO  (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
  93
  94 /* Architectures are the sum of the base and extensions.  */
  95 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  96                                                  AARCH64_FEATURE_V8_A \
  97                                                  | AARCH64_FEATURE_FP  \
  98                                                  | AARCH64_FEATURE_SIMD)
  99 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 100                                                  AARCH64_FEATURE_CRC    \
 101                                                  | AARCH64_FEATURE_V8_1 \
 102                                                  | AARCH64_FEATURE_LSE  \
 103                                                  | AARCH64_FEATURE_PAN  \
 104                                                  | AARCH64_FEATURE_LOR  \
 105                                                  | AARCH64_FEATURE_RDMA)
 106 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 107                                                  AARCH64_FEATURE_V8_2   \
 108                                                  | AARCH64_FEATURE_RAS)
 109 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 110                                                  AARCH64_FEATURE_V8_3   \
 111                                                  | AARCH64_FEATURE_RCPC \
 112                                                  | AARCH64_FEATURE_COMPNUM)
 113 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 114                                                  AARCH64_FEATURE_V8_4   \
 115                                                  | AARCH64_FEATURE_DOTPROD \
 116                                                  | AARCH64_FEATURE_F16_FML)
 117 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 118                                                  AARCH64_FEATURE_V8_5   \
 119                                                  | AARCH64_FEATURE_FLAGMANIP \
 120                                                  | AARCH64_FEATURE_FRINTTS \
 121                                                  | AARCH64_FEATURE_SB   \
 122                                                  | AARCH64_FEATURE_PREDRES \
 123                                                  | AARCH64_FEATURE_CVADP \
 124                                                  | AARCH64_FEATURE_BTI  \
 125                                                  | AARCH64_FEATURE_SCXTNUM \
 126                                                  | AARCH64_FEATURE_ID_PFR2 \
 127                                                  | AARCH64_FEATURE_SSBS)
 128 #define AARCH64_ARCH_V8_6       AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
 129                                                  AARCH64_FEATURE_V8_6   \
 130                                                  | AARCH64_FEATURE_BFLOAT16 \
 131                                                  | AARCH64_FEATURE_I8MM)
 132 #define AARCH64_ARCH_V8_7       AARCH64_FEATURE (AARCH64_ARCH_V8_6,     \
 133                                                  AARCH64_FEATURE_V8_7)
 134 #define AARCH64_ARCH_V8_R       (AARCH64_FEATURE (AARCH64_ARCH_V8_4,    \
 135                                                  AARCH64_FEATURE_V8_R)  \
 136                               & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
 137
 138 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 139 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 140
 141 /* CPU-specific features.  */
 142 typedef unsigned long long aarch64_feature_set;
 143
 144 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 145   ((~(CPU) & (FEAT)) == 0)
 146
 147 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 148   (((CPU) & (FEAT)) != 0)
 149
 150 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 151   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 152
 153 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 154   do                                            \
 155     {                                           \
 156       (TARG) = (F1) | (F2);                     \
 157     }                                           \
 158   while (0)
 159
 160 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 161   do                                            \
 162     {                                           \
 163       (TARG) = (F1) &~ (F2);                    \
 164     }                                           \
 165   while (0)
 166
 167 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 168
 169 enum aarch64_operand_class
 170 {
 171   AARCH64_OPND_CLASS_NIL,
 172   AARCH64_OPND_CLASS_INT_REG,
 173   AARCH64_OPND_CLASS_MODIFIED_REG,
 174   AARCH64_OPND_CLASS_FP_REG,
 175   AARCH64_OPND_CLASS_SIMD_REG,
 176   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 177   AARCH64_OPND_CLASS_SISD_REG,
 178   AARCH64_OPND_CLASS_SIMD_REGLIST,
 179   AARCH64_OPND_CLASS_SVE_REG,
 180   AARCH64_OPND_CLASS_PRED_REG,
 181   AARCH64_OPND_CLASS_ADDRESS,
 182   AARCH64_OPND_CLASS_IMMEDIATE,
 183   AARCH64_OPND_CLASS_SYSTEM,
 184   AARCH64_OPND_CLASS_COND,
 185 };
 186
 187 /* Operand code that helps both parsing and coding.
 188    Keep AARCH64_OPERANDS synced.  */
 189
 190 enum aarch64_opnd
 191 {
 192   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 193
 194   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 195   AARCH64_OPND_Rn,      /* Integer register as source.  */
 196   AARCH64_OPND_Rm,      /* Integer register as source.  */
 197   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 198   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 199   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 200   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 201   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 202   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 203
 204   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 205   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 206   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 207   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 208   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 209   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 210
 211   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 212   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 213   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 214   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 215   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 216   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 217
 218   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 219   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 220   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 221
 222   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 223   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 224   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 225   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 226   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 227   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 228   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 229   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 230   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 231   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 232                            qualifier is S_H.  */
 233   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 234   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 235   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 236                            structure to all lanes.  */
 237   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 238
 239   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 240   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 241
 242   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 243   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 244   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 245   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 246   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 247   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 248   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 249   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 250                            (no encoding).  */
 251   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 252   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 253   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 254   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 255   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 256   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 257   AARCH64_OPND_IMM,     /* Immediate.  */
 258   AARCH64_OPND_IMM_2,   /* Immediate.  */
 259   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 260   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 261   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 262   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 263   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 264   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 265   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 266   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 267   AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
 268   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 269   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 270   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 271                            each condition flag.  */
 272
 273   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 274   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 275   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 276   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 277   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 278   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 279   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 280   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 281
 282   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 283   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 284
 285   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 286   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 287   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 288   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 289   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 290
 291   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 292   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 293   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 294   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 295   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 296                                    negative or unaligned and there is
 297                                    no writeback allowed.  This operand code
 298                                    is only used to support the programmer-
 299                                    friendly feature of using LDR/STR as the
 300                                    the mnemonic name for LDUR/STUR instructions
 301                                    wherever there is no ambiguity.  */
 302   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 303   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 304                                    16) immediate.  */
 305   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 306   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 307                                    16) immediate.  */
 308   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 309   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 310   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 311
 312   AARCH64_OPND_SYSREG,          /* System register operand.  */
 313   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 314   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 315   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 316   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 317   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 318   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 319   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 320   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 321   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 322   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 323   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 324
 325   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 326   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
 327   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 328   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 329   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 330   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 331   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 332   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 333   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 334   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 335   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 336   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 337   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 338   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 339   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 340   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 341   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 342   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 343   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 344   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 345   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 346   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 347   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 348   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 349   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 350   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 351   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 352                                        Bit 14 controls S/U choice.  */
 353   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 354                                        Bit 22 controls S/U choice.  */
 355   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 356                                        Bit 14 controls S/U choice.  */
 357   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 358                                        Bit 22 controls S/U choice.  */
 359   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 360                                        Bit 14 controls S/U choice.  */
 361   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 362                                        Bit 22 controls S/U choice.  */
 363   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 364                                        Bit 14 controls S/U choice.  */
 365   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 366                                        Bit 22 controls S/U choice.  */
 367   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 368   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 369   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 370   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 371   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 372   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 373   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 374   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 375   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 376   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 377   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 378   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 379   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 380   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 381   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 382   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 383   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 384   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 385   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 386   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 387   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 388   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 389   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 390   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 391   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 392   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 393   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 394   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 395   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 396   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 397   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 398   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 399   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 400   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 401   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,    /* SVE 3 bit shift left unpred.  */
 402   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 403   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 404   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 405   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 406   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 407   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 408   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 409   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 410   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 411   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 412   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 413   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 414   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 415   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 416   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 417   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 418   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 419   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 420   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 421   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 422   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 423   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 424   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 425   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 426   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 427   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 428   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 429   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 430   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 431   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 432   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 433   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 434 };
 435
 436 /* Qualifier constrains an operand.  It either specifies a variant of an
 437    operand type or limits values available to an operand type.
 438
 439    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 440
 441 enum aarch64_opnd_qualifier
 442 {
 443   /* Indicating no further qualification on an operand.  */
 444   AARCH64_OPND_QLF_NIL,
 445
 446   /* Qualifying an operand which is a general purpose (integer) register;
 447      indicating the operand data size or a specific register.  */
 448   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 449   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 450   AARCH64_OPND_QLF_WSP, /* WSP.  */
 451   AARCH64_OPND_QLF_SP,  /* SP.  */
 452
 453   /* Qualifying an operand which is a floating-point register, a SIMD
 454      vector element or a SIMD vector element list; indicating operand data
 455      size or the size of each SIMD vector element in the case of a SIMD
 456      vector element list.
 457      These qualifiers are also used to qualify an address operand to
 458      indicate the size of data element a load/store instruction is
 459      accessing.
 460      They are also used for the immediate shift operand in e.g. SSHR.  Such
 461      a use is only for the ease of operand encoding/decoding and qualifier
 462      sequence matching; such a use should not be applied widely; use the value
 463      constraint qualifiers for immediate operands wherever possible.  */
 464   AARCH64_OPND_QLF_S_B,
 465   AARCH64_OPND_QLF_S_H,
 466   AARCH64_OPND_QLF_S_S,
 467   AARCH64_OPND_QLF_S_D,
 468   AARCH64_OPND_QLF_S_Q,
 469   /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
 470      or 2 x 2 byte are selected by the instruction.  Other than that they have
 471      no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
 472      for syntactical reasons and is an exception from normal AArch64
 473      disassembly scheme.  */
 474   AARCH64_OPND_QLF_S_4B,
 475   AARCH64_OPND_QLF_S_2H,
 476
 477   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 478      register list; indicating register shape.
 479      They are also used for the immediate shift operand in e.g. SSHR.  Such
 480      a use is only for the ease of operand encoding/decoding and qualifier
 481      sequence matching; such a use should not be applied widely; use the value
 482      constraint qualifiers for immediate operands wherever possible.  */
 483   AARCH64_OPND_QLF_V_4B,
 484   AARCH64_OPND_QLF_V_8B,
 485   AARCH64_OPND_QLF_V_16B,
 486   AARCH64_OPND_QLF_V_2H,
 487   AARCH64_OPND_QLF_V_4H,
 488   AARCH64_OPND_QLF_V_8H,
 489   AARCH64_OPND_QLF_V_2S,
 490   AARCH64_OPND_QLF_V_4S,
 491   AARCH64_OPND_QLF_V_1D,
 492   AARCH64_OPND_QLF_V_2D,
 493   AARCH64_OPND_QLF_V_1Q,
 494
 495   AARCH64_OPND_QLF_P_Z,
 496   AARCH64_OPND_QLF_P_M,
 497
 498   /* Used in scaled signed immediate that are scaled by a Tag granule
 499      like in stg, st2g, etc.   */
 500   AARCH64_OPND_QLF_imm_tag,
 501
 502   /* Constraint on value.  */
 503   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 504   AARCH64_OPND_QLF_imm_0_7,
 505   AARCH64_OPND_QLF_imm_0_15,
 506   AARCH64_OPND_QLF_imm_0_31,
 507   AARCH64_OPND_QLF_imm_0_63,
 508   AARCH64_OPND_QLF_imm_1_32,
 509   AARCH64_OPND_QLF_imm_1_64,
 510
 511   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 512      or shift-ones.  */
 513   AARCH64_OPND_QLF_LSL,
 514   AARCH64_OPND_QLF_MSL,
 515
 516   /* Special qualifier helping retrieve qualifier information during the
 517      decoding time (currently not in use).  */
 518   AARCH64_OPND_QLF_RETRIEVE,
 519 };
 520 \f
 521 /* Instruction class.  */
 522
 523 enum aarch64_insn_class
 524 {
 525   aarch64_misc,
 526   addsub_carry,
 527   addsub_ext,
 528   addsub_imm,
 529   addsub_shift,
 530   asimdall,
 531   asimddiff,
 532   asimdelem,
 533   asimdext,
 534   asimdimm,
 535   asimdins,
 536   asimdmisc,
 537   asimdperm,
 538   asimdsame,
 539   asimdshf,
 540   asimdtbl,
 541   asisddiff,
 542   asisdelem,
 543   asisdlse,
 544   asisdlsep,
 545   asisdlso,
 546   asisdlsop,
 547   asisdmisc,
 548   asisdone,
 549   asisdpair,
 550   asisdsame,
 551   asisdshf,
 552   bitfield,
 553   branch_imm,
 554   branch_reg,
 555   compbranch,
 556   condbranch,
 557   condcmp_imm,
 558   condcmp_reg,
 559   condsel,
 560   cryptoaes,
 561   cryptosha2,
 562   cryptosha3,
 563   dp_1src,
 564   dp_2src,
 565   dp_3src,
 566   exception,
 567   extract,
 568   float2fix,
 569   float2int,
 570   floatccmp,
 571   floatcmp,
 572   floatdp1,
 573   floatdp2,
 574   floatdp3,
 575   floatimm,
 576   floatsel,
 577   ldst_immpost,
 578   ldst_immpre,
 579   ldst_imm9,    /* immpost or immpre */
 580   ldst_imm10,   /* LDRAA/LDRAB */
 581   ldst_pos,
 582   ldst_regoff,
 583   ldst_unpriv,
 584   ldst_unscaled,
 585   ldstexcl,
 586   ldstnapair_offs,
 587   ldstpair_off,
 588   ldstpair_indexed,
 589   loadlit,
 590   log_imm,
 591   log_shift,
 592   lse_atomic,
 593   movewide,
 594   pcreladdr,
 595   ic_system,
 596   sve_cpy,
 597   sve_index,
 598   sve_limm,
 599   sve_misc,
 600   sve_movprfx,
 601   sve_pred_zm,
 602   sve_shift_pred,
 603   sve_shift_unpred,
 604   sve_size_bhs,
 605   sve_size_bhsd,
 606   sve_size_hsd,
 607   sve_size_hsd2,
 608   sve_size_sd,
 609   sve_size_bh,
 610   sve_size_sd2,
 611   sve_size_13,
 612   sve_shift_tsz_hsd,
 613   sve_shift_tsz_bhsd,
 614   sve_size_tsz_bhs,
 615   testbranch,
 616   cryptosm3,
 617   cryptosm4,
 618   dotproduct,
 619   bfloat16,
 620 };
 621
 622 /* Opcode enumerators.  */
 623
 624 enum aarch64_op
 625 {
 626   OP_NIL,
 627   OP_STRB_POS,
 628   OP_LDRB_POS,
 629   OP_LDRSB_POS,
 630   OP_STRH_POS,
 631   OP_LDRH_POS,
 632   OP_LDRSH_POS,
 633   OP_STR_POS,
 634   OP_LDR_POS,
 635   OP_STRF_POS,
 636   OP_LDRF_POS,
 637   OP_LDRSW_POS,
 638   OP_PRFM_POS,
 639
 640   OP_STURB,
 641   OP_LDURB,
 642   OP_LDURSB,
 643   OP_STURH,
 644   OP_LDURH,
 645   OP_LDURSH,
 646   OP_STUR,
 647   OP_LDUR,
 648   OP_STURV,
 649   OP_LDURV,
 650   OP_LDURSW,
 651   OP_PRFUM,
 652
 653   OP_LDR_LIT,
 654   OP_LDRV_LIT,
 655   OP_LDRSW_LIT,
 656   OP_PRFM_LIT,
 657
 658   OP_ADD,
 659   OP_B,
 660   OP_BL,
 661
 662   OP_MOVN,
 663   OP_MOVZ,
 664   OP_MOVK,
 665
 666   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 667   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 668   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 669
 670   OP_MOV_V,             /* MOV alias for moving vector register.  */
 671
 672   OP_ASR_IMM,
 673   OP_LSR_IMM,
 674   OP_LSL_IMM,
 675
 676   OP_BIC,
 677
 678   OP_UBFX,
 679   OP_BFXIL,
 680   OP_SBFX,
 681   OP_SBFIZ,
 682   OP_BFI,
 683   OP_BFC,               /* ARMv8.2.  */
 684   OP_UBFIZ,
 685   OP_UXTB,
 686   OP_UXTH,
 687   OP_UXTW,
 688
 689   OP_CINC,
 690   OP_CINV,
 691   OP_CNEG,
 692   OP_CSET,
 693   OP_CSETM,
 694
 695   OP_FCVT,
 696   OP_FCVTN,
 697   OP_FCVTN2,
 698   OP_FCVTL,
 699   OP_FCVTL2,
 700   OP_FCVTXN_S,          /* Scalar version.  */
 701
 702   OP_ROR_IMM,
 703
 704   OP_SXTL,
 705   OP_SXTL2,
 706   OP_UXTL,
 707   OP_UXTL2,
 708
 709   OP_MOV_P_P,
 710   OP_MOV_Z_P_Z,
 711   OP_MOV_Z_V,
 712   OP_MOV_Z_Z,
 713   OP_MOV_Z_Zi,
 714   OP_MOVM_P_P_P,
 715   OP_MOVS_P_P,
 716   OP_MOVZS_P_P_P,
 717   OP_MOVZ_P_P_P,
 718   OP_NOTS_P_P_P_Z,
 719   OP_NOT_P_P_P_Z,
 720
 721   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 722
 723   OP_TOTAL_NUM,         /* Pseudo.  */
 724 };
 725
 726 /* Error types.  */
 727 enum err_type
 728 {
 729   ERR_OK,
 730   ERR_UND,
 731   ERR_UNP,
 732   ERR_NYI,
 733   ERR_VFI,
 734   ERR_NR_ENTRIES
 735 };
 736
 737 /* Maximum number of operands an instruction can have.  */
 738 #define AARCH64_MAX_OPND_NUM 6
 739 /* Maximum number of qualifier sequences an instruction can have.  */
 740 #define AARCH64_MAX_QLF_SEQ_NUM 10
 741 /* Operand qualifier typedef; optimized for the size.  */
 742 typedef unsigned char aarch64_opnd_qualifier_t;
 743 /* Operand qualifier sequence typedef.  */
 744 typedef aarch64_opnd_qualifier_t        \
 745           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 746
 747 /* FIXME: improve the efficiency.  */
 748 static inline bfd_boolean
 749 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 750 {
 751   int i;
 752   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 753     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 754       return FALSE;
 755   return TRUE;
 756 }
 757
 758 /*  Forward declare error reporting type.  */
 759 typedef struct aarch64_operand_error aarch64_operand_error;
 760 /* Forward declare instruction sequence type.  */
 761 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 762 /* Forward declare instruction definition.  */
 763 typedef struct aarch64_inst aarch64_inst;
 764
 765 /* This structure holds information for a particular opcode.  */
 766
 767 struct aarch64_opcode
 768 {
 769   /* The name of the mnemonic.  */
 770   const char *name;
 771
 772   /* The opcode itself.  Those bits which will be filled in with
 773      operands are zeroes.  */
 774   aarch64_insn opcode;
 775
 776   /* The opcode mask.  This is used by the disassembler.  This is a
 777      mask containing ones indicating those bits which must match the
 778      opcode field, and zeroes indicating those bits which need not
 779      match (and are presumably filled in by operands).  */
 780   aarch64_insn mask;
 781
 782   /* Instruction class.  */
 783   enum aarch64_insn_class iclass;
 784
 785   /* Enumerator identifier.  */
 786   enum aarch64_op op;
 787
 788   /* Which architecture variant provides this instruction.  */
 789   const aarch64_feature_set *avariant;
 790
 791   /* An array of operand codes.  Each code is an index into the
 792      operand table.  They appear in the order which the operands must
 793      appear in assembly code, and are terminated by a zero.  */
 794   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 795
 796   /* A list of operand qualifier code sequence.  Each operand qualifier
 797      code qualifies the corresponding operand code.  Each operand
 798      qualifier sequence specifies a valid opcode variant and related
 799      constraint on operands.  */
 800   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 801
 802   /* Flags providing information about this instruction */
 803   uint64_t flags;
 804
 805   /* Extra constraints on the instruction that the verifier checks.  */
 806   uint32_t constraints;
 807
 808   /* If nonzero, this operand and operand 0 are both registers and
 809      are required to have the same register number.  */
 810   unsigned char tied_operand;
 811
 812   /* If non-NULL, a function to verify that a given instruction is valid.  */
 813   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 814                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 815                               struct aarch64_instr_sequence *);
 816 };
 817
 818 typedef struct aarch64_opcode aarch64_opcode;
 819
 820 /* Table describing all the AArch64 opcodes.  */
 821 extern aarch64_opcode aarch64_opcode_table[];
 822
 823 /* Opcode flags.  */
 824 #define F_ALIAS (1 << 0)
 825 #define F_HAS_ALIAS (1 << 1)
 826 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 827    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 828 #define F_P1 (1 << 2)
 829 #define F_P2 (2 << 2)
 830 #define F_P3 (3 << 2)
 831 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 832 #define F_COND (1 << 4)
 833 /* Instruction has the field of 'sf'.  */
 834 #define F_SF (1 << 5)
 835 /* Instruction has the field of 'size:Q'.  */
 836 #define F_SIZEQ (1 << 6)
 837 /* Floating-point instruction has the field of 'type'.  */
 838 #define F_FPTYPE (1 << 7)
 839 /* AdvSIMD scalar instruction has the field of 'size'.  */
 840 #define F_SSIZE (1 << 8)
 841 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 842 #define F_T (1 << 9)
 843 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 844 #define F_GPRSIZE_IN_Q (1 << 10)
 845 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 846 #define F_LDS_SIZE (1 << 11)
 847 /* Optional operand; assume maximum of 1 operand can be optional.  */
 848 #define F_OPD0_OPT (1 << 12)
 849 #define F_OPD1_OPT (2 << 12)
 850 #define F_OPD2_OPT (3 << 12)
 851 #define F_OPD3_OPT (4 << 12)
 852 #define F_OPD4_OPT (5 << 12)
 853 /* Default value for the optional operand when omitted from the assembly.  */
 854 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 855 /* Instruction that is an alias of another instruction needs to be
 856    encoded/decoded by converting it to/from the real form, followed by
 857    the encoding/decoding according to the rules of the real opcode.
 858    This compares to the direct coding using the alias's information.
 859    N.B. this flag requires F_ALIAS to be used together.  */
 860 #define F_CONV (1 << 20)
 861 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 862    friendly pseudo instruction available only in the assembly code (thus will
 863    not show up in the disassembly).  */
 864 #define F_PSEUDO (1 << 21)
 865 /* Instruction has miscellaneous encoding/decoding rules.  */
 866 #define F_MISC (1 << 22)
 867 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 868 #define F_N (1 << 23)
 869 /* Opcode dependent field.  */
 870 #define F_OD(X) (((X) & 0x7) << 24)
 871 /* Instruction has the field of 'sz'.  */
 872 #define F_LSE_SZ (1 << 27)
 873 /* Require an exact qualifier match, even for NIL qualifiers.  */
 874 #define F_STRICT (1ULL << 28)
 875 /* This system instruction is used to read system registers.  */
 876 #define F_SYS_READ (1ULL << 29)
 877 /* This system instruction is used to write system registers.  */
 878 #define F_SYS_WRITE (1ULL << 30)
 879 /* This instruction has an extra constraint on it that imposes a requirement on
 880    subsequent instructions.  */
 881 #define F_SCAN (1ULL << 31)
 882 /* Next bit is 32.  */
 883
 884 /* Instruction constraints.  */
 885 /* This instruction has a predication constraint on the instruction at PC+4.  */
 886 #define C_SCAN_MOVPRFX (1U << 0)
 887 /* This instruction's operation width is determined by the operand with the
 888    largest element size.  */
 889 #define C_MAX_ELEM (1U << 1)
 890 /* Next bit is 2.  */
 891
 892 static inline bfd_boolean
 893 alias_opcode_p (const aarch64_opcode *opcode)
 894 {
 895   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 896 }
 897
 898 static inline bfd_boolean
 899 opcode_has_alias (const aarch64_opcode *opcode)
 900 {
 901   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 902 }
 903
 904 /* Priority for disassembling preference.  */
 905 static inline int
 906 opcode_priority (const aarch64_opcode *opcode)
 907 {
 908   return (opcode->flags >> 2) & 0x3;
 909 }
 910
 911 static inline bfd_boolean
 912 pseudo_opcode_p (const aarch64_opcode *opcode)
 913 {
 914   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 915 }
 916
 917 static inline bfd_boolean
 918 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 919 {
 920   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 921     ? TRUE : FALSE;
 922 }
 923
 924 static inline aarch64_insn
 925 get_optional_operand_default_value (const aarch64_opcode *opcode)
 926 {
 927   return (opcode->flags >> 15) & 0x1f;
 928 }
 929
 930 static inline unsigned int
 931 get_opcode_dependent_value (const aarch64_opcode *opcode)
 932 {
 933   return (opcode->flags >> 24) & 0x7;
 934 }
 935
 936 static inline bfd_boolean
 937 opcode_has_special_coder (const aarch64_opcode *opcode)
 938 {
 939   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 940           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 941     : FALSE;
 942 }
 943 \f
 944 struct aarch64_name_value_pair
 945 {
 946   const char *  name;
 947   aarch64_insn  value;
 948 };
 949
 950 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 951 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 952 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 953 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 954
 955 #define AARCH64_MAX_SYSREG_NAME_LEN 32
 956
 957 typedef struct
 958 {
 959   const char *  name;
 960   aarch64_insn  value;
 961   uint32_t      flags;
 962
 963   /* A set of features, all of which are required for this system register to be
 964      available.  */
 965   aarch64_feature_set features;
 966 } aarch64_sys_reg;
 967
 968 extern const aarch64_sys_reg aarch64_sys_regs [];
 969 extern const aarch64_sys_reg aarch64_pstatefields [];
 970 extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
 971 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 972                                                     const aarch64_sys_reg *);
 973
 974 typedef struct
 975 {
 976   const char *name;
 977   uint32_t value;
 978   uint32_t flags ;
 979 } aarch64_sys_ins_reg;
 980
 981 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 982 extern bfd_boolean
 983 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 984                                  const char *reg_name, aarch64_insn,
 985                                  uint32_t, aarch64_feature_set);
 986
 987 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 988 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 989 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 990 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 991 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 992
 993 /* Shift/extending operator kinds.
 994    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 995 enum aarch64_modifier_kind
 996 {
 997   AARCH64_MOD_NONE,
 998   AARCH64_MOD_MSL,
 999   AARCH64_MOD_ROR,
1000   AARCH64_MOD_ASR,
1001   AARCH64_MOD_LSR,
1002   AARCH64_MOD_LSL,
1003   AARCH64_MOD_UXTB,
1004   AARCH64_MOD_UXTH,
1005   AARCH64_MOD_UXTW,
1006   AARCH64_MOD_UXTX,
1007   AARCH64_MOD_SXTB,
1008   AARCH64_MOD_SXTH,
1009   AARCH64_MOD_SXTW,
1010   AARCH64_MOD_SXTX,
1011   AARCH64_MOD_MUL,
1012   AARCH64_MOD_MUL_VL,
1013 };
1014
1015 bfd_boolean
1016 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1017
1018 enum aarch64_modifier_kind
1019 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1020 /* Condition.  */
1021
1022 typedef struct
1023 {
1024   /* A list of names with the first one as the disassembly preference;
1025      terminated by NULL if fewer than 3.  */
1026   const char *names[4];
1027   aarch64_insn value;
1028 } aarch64_cond;
1029
1030 extern const aarch64_cond aarch64_conds[16];
1031
1032 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1033 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1034 \f
1035 /* Structure representing an operand.  */
1036
1037 struct aarch64_opnd_info
1038 {
1039   enum aarch64_opnd type;
1040   aarch64_opnd_qualifier_t qualifier;
1041   int idx;
1042
1043   union
1044     {
1045       struct
1046         {
1047           unsigned regno;
1048         } reg;
1049       struct
1050         {
1051           unsigned int regno;
1052           int64_t index;
1053         } reglane;
1054       /* e.g. LVn.  */
1055       struct
1056         {
1057           unsigned first_regno : 5;
1058           unsigned num_regs : 3;
1059           /* 1 if it is a list of reg element.  */
1060           unsigned has_index : 1;
1061           /* Lane index; valid only when has_index is 1.  */
1062           int64_t index;
1063         } reglist;
1064       /* e.g. immediate or pc relative address offset.  */
1065       struct
1066         {
1067           int64_t value;
1068           unsigned is_fp : 1;
1069         } imm;
1070       /* e.g. address in STR (register offset).  */
1071       struct
1072         {
1073           unsigned base_regno;
1074           struct
1075             {
1076               union
1077                 {
1078                   int imm;
1079                   unsigned regno;
1080                 };
1081               unsigned is_reg;
1082             } offset;
1083           unsigned pcrel : 1;           /* PC-relative.  */
1084           unsigned writeback : 1;
1085           unsigned preind : 1;          /* Pre-indexed.  */
1086           unsigned postind : 1;         /* Post-indexed.  */
1087         } addr;
1088
1089       struct
1090         {
1091           /* The encoding of the system register.  */
1092           aarch64_insn value;
1093
1094           /* The system register flags.  */
1095           uint32_t flags;
1096         } sysreg;
1097
1098       const aarch64_cond *cond;
1099       /* The encoding of the PSTATE field.  */
1100       aarch64_insn pstatefield;
1101       const aarch64_sys_ins_reg *sysins_op;
1102       const struct aarch64_name_value_pair *barrier;
1103       const struct aarch64_name_value_pair *hint_option;
1104       const struct aarch64_name_value_pair *prfop;
1105     };
1106
1107   /* Operand shifter; in use when the operand is a register offset address,
1108      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1109   struct
1110     {
1111       enum aarch64_modifier_kind kind;
1112       unsigned operator_present: 1;     /* Only valid during encoding.  */
1113       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1114       unsigned amount_present: 1;
1115       int64_t amount;
1116     } shifter;
1117
1118   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1119                            to be done on it.  In some (but not all) of these
1120                            cases, we need to tell libopcodes to skip the
1121                            constraint checking and the encoding for this
1122                            operand, so that the libopcodes can pick up the
1123                            right opcode before the operand is fixed-up.  This
1124                            flag should only be used during the
1125                            assembling/encoding.  */
1126   unsigned present:1;   /* Whether this operand is present in the assembly
1127                            line; not used during the disassembly.  */
1128 };
1129
1130 typedef struct aarch64_opnd_info aarch64_opnd_info;
1131
1132 /* Structure representing an instruction.
1133
1134    It is used during both the assembling and disassembling.  The assembler
1135    fills an aarch64_inst after a successful parsing and then passes it to the
1136    encoding routine to do the encoding.  During the disassembling, the
1137    disassembler calls the decoding routine to decode a binary instruction; on a
1138    successful return, such a structure will be filled with information of the
1139    instruction; then the disassembler uses the information to print out the
1140    instruction.  */
1141
1142 struct aarch64_inst
1143 {
1144   /* The value of the binary instruction.  */
1145   aarch64_insn value;
1146
1147   /* Corresponding opcode entry.  */
1148   const aarch64_opcode *opcode;
1149
1150   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1151   const aarch64_cond *cond;
1152
1153   /* Operands information.  */
1154   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1155 };
1156
1157 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1158 #define HINT_OPD_CSYNC  0x11
1159 #define HINT_OPD_C      0x22
1160 #define HINT_OPD_J      0x24
1161 #define HINT_OPD_JC     0x26
1162 #define HINT_OPD_NULL   0x00
1163
1164 \f
1165 /* Diagnosis related declaration and interface.  */
1166
1167 /* Operand error kind enumerators.
1168
1169    AARCH64_OPDE_RECOVERABLE
1170      Less severe error found during the parsing, very possibly because that
1171      GAS has picked up a wrong instruction template for the parsing.
1172
1173    AARCH64_OPDE_SYNTAX_ERROR
1174      General syntax error; it can be either a user error, or simply because
1175      that GAS is trying a wrong instruction template.
1176
1177    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1178      Definitely a user syntax error.
1179
1180    AARCH64_OPDE_INVALID_VARIANT
1181      No syntax error, but the operands are not a valid combination, e.g.
1182      FMOV D0,S0
1183
1184    AARCH64_OPDE_UNTIED_OPERAND
1185      The asm failed to use the same register for a destination operand
1186      and a tied source operand.
1187
1188    AARCH64_OPDE_OUT_OF_RANGE
1189      Error about some immediate value out of a valid range.
1190
1191    AARCH64_OPDE_UNALIGNED
1192      Error about some immediate value not properly aligned (i.e. not being a
1193      multiple times of a certain value).
1194
1195    AARCH64_OPDE_REG_LIST
1196      Error about the register list operand having unexpected number of
1197      registers.
1198
1199    AARCH64_OPDE_OTHER_ERROR
1200      Error of the highest severity and used for any severe issue that does not
1201      fall into any of the above categories.
1202
1203    The enumerators are only interesting to GAS.  They are declared here (in
1204    libopcodes) because that some errors are detected (and then notified to GAS)
1205    by libopcodes (rather than by GAS solely).
1206
1207    The first three errors are only deteced by GAS while the
1208    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1209    only libopcodes has the information about the valid variants of each
1210    instruction.
1211
1212    The enumerators have an increasing severity.  This is helpful when there are
1213    multiple instruction templates available for a given mnemonic name (e.g.
1214    FMOV); this mechanism will help choose the most suitable template from which
1215    the generated diagnostics can most closely describe the issues, if any.  */
1216
1217 enum aarch64_operand_error_kind
1218 {
1219   AARCH64_OPDE_NIL,
1220   AARCH64_OPDE_RECOVERABLE,
1221   AARCH64_OPDE_SYNTAX_ERROR,
1222   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1223   AARCH64_OPDE_INVALID_VARIANT,
1224   AARCH64_OPDE_UNTIED_OPERAND,
1225   AARCH64_OPDE_OUT_OF_RANGE,
1226   AARCH64_OPDE_UNALIGNED,
1227   AARCH64_OPDE_REG_LIST,
1228   AARCH64_OPDE_OTHER_ERROR
1229 };
1230
1231 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1232 struct aarch64_operand_error
1233 {
1234   enum aarch64_operand_error_kind kind;
1235   int index;
1236   const char *error;
1237   int data[3];  /* Some data for extra information.  */
1238   bfd_boolean non_fatal;
1239 };
1240
1241 /* AArch64 sequence structure used to track instructions with F_SCAN
1242    dependencies for both assembler and disassembler.  */
1243 struct aarch64_instr_sequence
1244 {
1245   /* The instruction that caused this sequence to be opened.  */
1246   aarch64_inst *instr;
1247   /* The number of instructions the above instruction allows to be kept in the
1248      sequence before an automatic close is done.  */
1249   int num_insns;
1250   /* The instructions currently added to the sequence.  */
1251   aarch64_inst **current_insns;
1252   /* The number of instructions already in the sequence.  */
1253   int next_insn;
1254 };
1255
1256 /* Encoding entrypoint.  */
1257
1258 extern int
1259 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1260                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1261                        aarch64_operand_error *, aarch64_instr_sequence *);
1262
1263 extern const aarch64_opcode *
1264 aarch64_replace_opcode (struct aarch64_inst *,
1265                         const aarch64_opcode *);
1266
1267 /* Given the opcode enumerator OP, return the pointer to the corresponding
1268    opcode entry.  */
1269
1270 extern const aarch64_opcode *
1271 aarch64_get_opcode (enum aarch64_op);
1272
1273 /* Generate the string representation of an operand.  */
1274 extern void
1275 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1276                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1277                        char **,
1278                        aarch64_feature_set features);
1279
1280 /* Miscellaneous interface.  */
1281
1282 extern int
1283 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1284
1285 extern aarch64_opnd_qualifier_t
1286 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1287                                 const aarch64_opnd_qualifier_t, int);
1288
1289 extern bfd_boolean
1290 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1291
1292 extern int
1293 aarch64_num_of_operands (const aarch64_opcode *);
1294
1295 extern int
1296 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1297
1298 extern int
1299 aarch64_zero_register_p (const aarch64_opnd_info *);
1300
1301 extern enum err_type
1302 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1303                      aarch64_operand_error *);
1304
1305 extern void
1306 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1307
1308 /* Given an operand qualifier, return the expected data element size
1309    of a qualified operand.  */
1310 extern unsigned char
1311 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1312
1313 extern enum aarch64_operand_class
1314 aarch64_get_operand_class (enum aarch64_opnd);
1315
1316 extern const char *
1317 aarch64_get_operand_name (enum aarch64_opnd);
1318
1319 extern const char *
1320 aarch64_get_operand_desc (enum aarch64_opnd);
1321
1322 extern bfd_boolean
1323 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1324
1325 #ifdef DEBUG_AARCH64
1326 extern int debug_dump;
1327
1328 extern void
1329 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1330
1331 #define DEBUG_TRACE(M, ...)                                     \
1332   {                                                             \
1333     if (debug_dump)                                             \
1334       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1335   }
1336
1337 #define DEBUG_TRACE_IF(C, M, ...)                               \
1338   {                                                             \
1339     if (debug_dump && (C))                                      \
1340       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1341   }
1342 #else  /* !DEBUG_AARCH64 */
1343 #define DEBUG_TRACE(M, ...) ;
1344 #define DEBUG_TRACE_IF(C, M, ...) ;
1345 #endif /* DEBUG_AARCH64 */
1346
1347 extern const char *const aarch64_sve_pattern_array[32];
1348 extern const char *const aarch64_sve_prfop_array[16];
1349
1350 #ifdef __cplusplus
1351 }
1352 #endif
1353
1354 #endif /* OPCODE_AARCH64_H */