include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2020 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8           (1ULL << 0) /* All processors.  */
  41 #define AARCH64_FEATURE_V8_6         (1ULL << 1) /* ARMv8.6 processors.  */
  42 #define AARCH64_FEATURE_BFLOAT16     (1ULL << 2) /* Bfloat16 insns.  */
  43 #define AARCH64_FEATURE_V8_A         (1ULL << 3) /* Armv8-A processors.  */
  44 #define AARCH64_FEATURE_SVE2         (1ULL << 4) /* SVE2 instructions.  */
  45 #define AARCH64_FEATURE_V8_2         (1ULL << 5) /* ARMv8.2 processors.  */
  46 #define AARCH64_FEATURE_V8_3         (1ULL << 6) /* ARMv8.3 processors.  */
  47 #define AARCH64_FEATURE_SVE2_AES     (1ULL << 7)
  48 #define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
  49 #define AARCH64_FEATURE_SVE2_SM4     (1ULL << 9)
  50 #define AARCH64_FEATURE_SVE2_SHA3    (1ULL << 10)
  51 #define AARCH64_FEATURE_V8_4         (1ULL << 11) /* ARMv8.4 processors.  */
  52 #define AARCH64_FEATURE_V8_R         (1ULL << 12) /* Armv8-R processors.  */
  53 #define AARCH64_FEATURE_V8_7         (1ULL << 13) /* Armv8.7 processors.  */
  54 #define AARCH64_FEATURE_CSRE         (1ULL << 14) /* CSRE feature.  */
  55 #define AARCH64_FEATURE_LS64         (1ULL << 15) /* Atomic 64-byte load/store.  */
  56 #define AARCH64_FEATURE_PAC          (1ULL << 16) /* v8.3 Pointer Authentication.  */
  57 #define AARCH64_FEATURE_FP           (1ULL << 17) /* FP instructions.  */
  58 #define AARCH64_FEATURE_SIMD         (1ULL << 18) /* SIMD instructions.  */
  59 #define AARCH64_FEATURE_CRC          (1ULL << 19) /* CRC instructions.  */
  60 #define AARCH64_FEATURE_LSE          (1ULL << 20) /* LSE instructions.  */
  61 #define AARCH64_FEATURE_PAN          (1ULL << 21) /* PAN instructions.  */
  62 #define AARCH64_FEATURE_LOR          (1ULL << 22) /* LOR instructions.  */
  63 #define AARCH64_FEATURE_RDMA         (1ULL << 23) /* v8.1 SIMD instructions.  */
  64 #define AARCH64_FEATURE_V8_1         (1ULL << 24) /* v8.1 features.  */
  65 #define AARCH64_FEATURE_F16          (1ULL << 25) /* v8.2 FP16 instructions.  */
  66 #define AARCH64_FEATURE_RAS          (1ULL << 26) /* RAS Extensions.  */
  67 #define AARCH64_FEATURE_PROFILE      (1ULL << 27) /* Statistical Profiling.  */
  68 #define AARCH64_FEATURE_SVE          (1ULL << 28) /* SVE instructions.  */
  69 #define AARCH64_FEATURE_RCPC         (1ULL << 29) /* RCPC instructions.  */
  70 #define AARCH64_FEATURE_COMPNUM      (1ULL << 30) /* Complex # instructions.  */
  71 #define AARCH64_FEATURE_DOTPROD      (1ULL << 31) /* Dot Product instructions.  */
  72 #define AARCH64_FEATURE_SM4          (1ULL << 32) /* SM3 & SM4 instructions.  */
  73 #define AARCH64_FEATURE_SHA2         (1ULL << 33) /* SHA2 instructions.  */
  74 #define AARCH64_FEATURE_SHA3         (1ULL << 34) /* SHA3 instructions.  */
  75 #define AARCH64_FEATURE_AES          (1ULL << 35) /* AES instructions.  */
  76 #define AARCH64_FEATURE_F16_FML      (1ULL << 36) /* v8.2 FP16FML ins.  */
  77 #define AARCH64_FEATURE_V8_5         (1ULL << 37) /* ARMv8.5 processors.  */
  78 #define AARCH64_FEATURE_FLAGMANIP    (1ULL << 38) /* Flag Manipulation insns.  */
  79 #define AARCH64_FEATURE_FRINTTS      (1ULL << 39) /* FRINT[32,64][Z,X] insns.  */
  80 #define AARCH64_FEATURE_SB           (1ULL << 40) /* SB instruction.  */
  81 #define AARCH64_FEATURE_PREDRES      (1ULL << 41) /* Execution and Data Prediction Restriction instructions.  */
  82 #define AARCH64_FEATURE_CVADP        (1ULL << 42) /* DC CVADP.  */
  83 #define AARCH64_FEATURE_RNG          (1ULL << 43) /* Random Number instructions.  */
  84 #define AARCH64_FEATURE_BTI          (1ULL << 44) /* BTI instructions.  */
  85 #define AARCH64_FEATURE_SCXTNUM      (1ULL << 45) /* SCXTNUM_ELx.  */
  86 #define AARCH64_FEATURE_ID_PFR2      (1ULL << 46) /* ID_PFR2 instructions.  */
  87 #define AARCH64_FEATURE_SSBS         (1ULL << 47) /* SSBS mechanism enabled.  */
  88 #define AARCH64_FEATURE_MEMTAG       (1ULL << 48) /* Memory Tagging Extension.  */
  89 #define AARCH64_FEATURE_TME          (1ULL << 49) /* Transactional Memory Extension.  */
  90 #define AARCH64_FEATURE_I8MM         (1ULL << 52) /* Matrix Multiply instructions.  */
  91 #define AARCH64_FEATURE_F32MM        (1ULL << 53)
  92 #define AARCH64_FEATURE_F64MM        (1ULL << 54)
  93
  94 /* Crypto instructions are the combination of AES and SHA2.  */
  95 #define AARCH64_FEATURE_CRYPTO  (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
  96
  97 /* Architectures are the sum of the base and extensions.  */
  98 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  99                                                  AARCH64_FEATURE_V8_A \
 100                                                  | AARCH64_FEATURE_FP  \
 101                                                  | AARCH64_FEATURE_RAS \
 102                                                  | AARCH64_FEATURE_SIMD)
 103 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 104                                                  AARCH64_FEATURE_CRC    \
 105                                                  | AARCH64_FEATURE_V8_1 \
 106                                                  | AARCH64_FEATURE_LSE  \
 107                                                  | AARCH64_FEATURE_PAN  \
 108                                                  | AARCH64_FEATURE_LOR  \
 109                                                  | AARCH64_FEATURE_RDMA)
 110 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 111                                                  AARCH64_FEATURE_V8_2)
 112 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 113                                                  AARCH64_FEATURE_V8_3   \
 114                                                  | AARCH64_FEATURE_PAC  \
 115                                                  | AARCH64_FEATURE_RCPC \
 116                                                  | AARCH64_FEATURE_COMPNUM)
 117 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 118                                                  AARCH64_FEATURE_V8_4   \
 119                                                  | AARCH64_FEATURE_DOTPROD \
 120                                                  | AARCH64_FEATURE_F16_FML)
 121 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 122                                                  AARCH64_FEATURE_V8_5   \
 123                                                  | AARCH64_FEATURE_FLAGMANIP \
 124                                                  | AARCH64_FEATURE_FRINTTS \
 125                                                  | AARCH64_FEATURE_SB   \
 126                                                  | AARCH64_FEATURE_PREDRES \
 127                                                  | AARCH64_FEATURE_CVADP \
 128                                                  | AARCH64_FEATURE_BTI  \
 129                                                  | AARCH64_FEATURE_SCXTNUM \
 130                                                  | AARCH64_FEATURE_ID_PFR2 \
 131                                                  | AARCH64_FEATURE_SSBS)
 132 #define AARCH64_ARCH_V8_6       AARCH64_FEATURE (AARCH64_ARCH_V8_5,     \
 133                                                  AARCH64_FEATURE_V8_6   \
 134                                                  | AARCH64_FEATURE_BFLOAT16 \
 135                                                  | AARCH64_FEATURE_I8MM)
 136 #define AARCH64_ARCH_V8_7       AARCH64_FEATURE (AARCH64_ARCH_V8_6,     \
 137                                                  AARCH64_FEATURE_V8_7   \
 138                                                  | AARCH64_FEATURE_LS64)
 139 #define AARCH64_ARCH_V8_R       (AARCH64_FEATURE (AARCH64_ARCH_V8_4,    \
 140                                                  AARCH64_FEATURE_V8_R)  \
 141                               & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
 142
 143 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 144 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 145
 146 /* CPU-specific features.  */
 147 typedef unsigned long long aarch64_feature_set;
 148
 149 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 150   ((~(CPU) & (FEAT)) == 0)
 151
 152 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 153   (((CPU) & (FEAT)) != 0)
 154
 155 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 156   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 157
 158 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 159   do                                            \
 160     {                                           \
 161       (TARG) = (F1) | (F2);                     \
 162     }                                           \
 163   while (0)
 164
 165 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 166   do                                            \
 167     {                                           \
 168       (TARG) = (F1) &~ (F2);                    \
 169     }                                           \
 170   while (0)
 171
 172 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 173
 174 enum aarch64_operand_class
 175 {
 176   AARCH64_OPND_CLASS_NIL,
 177   AARCH64_OPND_CLASS_INT_REG,
 178   AARCH64_OPND_CLASS_MODIFIED_REG,
 179   AARCH64_OPND_CLASS_FP_REG,
 180   AARCH64_OPND_CLASS_SIMD_REG,
 181   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 182   AARCH64_OPND_CLASS_SISD_REG,
 183   AARCH64_OPND_CLASS_SIMD_REGLIST,
 184   AARCH64_OPND_CLASS_SVE_REG,
 185   AARCH64_OPND_CLASS_PRED_REG,
 186   AARCH64_OPND_CLASS_ADDRESS,
 187   AARCH64_OPND_CLASS_IMMEDIATE,
 188   AARCH64_OPND_CLASS_SYSTEM,
 189   AARCH64_OPND_CLASS_COND,
 190 };
 191
 192 /* Operand code that helps both parsing and coding.
 193    Keep AARCH64_OPERANDS synced.  */
 194
 195 enum aarch64_opnd
 196 {
 197   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 198
 199   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 200   AARCH64_OPND_Rn,      /* Integer register as source.  */
 201   AARCH64_OPND_Rm,      /* Integer register as source.  */
 202   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 203   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 204   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 205   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 206   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 207   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 208
 209   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 210   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 211   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 212   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 213   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 214   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 215
 216   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 217   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 218   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 219   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 220   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 221   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 222
 223   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 224   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 225   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 226
 227   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 228   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 229   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 230   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 231   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 232   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 233   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 234   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 235   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 236   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 237                            qualifier is S_H.  */
 238   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 239   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 240   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 241                            structure to all lanes.  */
 242   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 243
 244   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 245   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 246
 247   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 248   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 249   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 250   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 251   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 252   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 253   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 254   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 255                            (no encoding).  */
 256   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 257   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 258   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 259   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 260   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 261   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 262   AARCH64_OPND_IMM,     /* Immediate.  */
 263   AARCH64_OPND_IMM_2,   /* Immediate.  */
 264   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 265   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 266   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 267   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 268   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 269   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 270   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 271   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 272   AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
 273   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 274   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 275   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 276                            each condition flag.  */
 277
 278   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 279   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 280   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 281   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 282   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 283   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 284   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 285   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 286
 287   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 288   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 289
 290   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 291   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 292   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 293   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 294   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 295
 296   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 297   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 298   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 299   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 300   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 301                                    negative or unaligned and there is
 302                                    no writeback allowed.  This operand code
 303                                    is only used to support the programmer-
 304                                    friendly feature of using LDR/STR as the
 305                                    the mnemonic name for LDUR/STUR instructions
 306                                    wherever there is no ambiguity.  */
 307   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 308   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 309                                    16) immediate.  */
 310   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 311   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 312                                    16) immediate.  */
 313   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 314   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 315   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 316
 317   AARCH64_OPND_SYSREG,          /* System register operand.  */
 318   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 319   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 320   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 321   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 322   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 323   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 324   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 325   AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant.  */
 326   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 327   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 328   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 329   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 330
 331   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 332   AARCH64_OPND_SVE_ADDR_RI_S4x32,   /* SVE [<Xn|SP>, #<simm4>*32].  */
 333   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 334   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 335   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 336   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 337   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 338   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 339   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 340   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 341   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 342   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 343   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 344   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 345   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 346   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 347   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 348   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 349   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 350   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 351   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 352   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 353   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 354   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 355   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 356   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 357   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 358                                        Bit 14 controls S/U choice.  */
 359   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 360                                        Bit 22 controls S/U choice.  */
 361   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 362                                        Bit 14 controls S/U choice.  */
 363   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 364                                        Bit 22 controls S/U choice.  */
 365   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 366                                        Bit 14 controls S/U choice.  */
 367   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 368                                        Bit 22 controls S/U choice.  */
 369   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 370                                        Bit 14 controls S/U choice.  */
 371   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 372                                        Bit 22 controls S/U choice.  */
 373   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 374   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 375   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 376   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 377   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 378   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 379   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 380   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 381   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 382   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 383   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 384   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 385   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 386   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 387   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 388   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 389   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 390   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 391   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 392   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 393   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 394   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 395   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 396   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 397   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 398   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 399   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 400   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 401   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 402   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 403   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 404   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 405   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 406   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 407   AARCH64_OPND_SVE_SHLIMM_UNPRED_22,    /* SVE 3 bit shift left unpred.  */
 408   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 409   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 410   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 411   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 412   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 413   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 414   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 415   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 416   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 417   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 418   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 419   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 420   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 421   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 422   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 423   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 424   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 425   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 426   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 427   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 428   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 429   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 430   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 431   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 432   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 433   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 434   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 435   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 436   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 437   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 438   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 439   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 440   AARCH64_OPND_CSRE_CSR,        /* CSRE CSR instruction Rt field.  */
 441 };
 442
 443 /* Qualifier constrains an operand.  It either specifies a variant of an
 444    operand type or limits values available to an operand type.
 445
 446    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 447
 448 enum aarch64_opnd_qualifier
 449 {
 450   /* Indicating no further qualification on an operand.  */
 451   AARCH64_OPND_QLF_NIL,
 452
 453   /* Qualifying an operand which is a general purpose (integer) register;
 454      indicating the operand data size or a specific register.  */
 455   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 456   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 457   AARCH64_OPND_QLF_WSP, /* WSP.  */
 458   AARCH64_OPND_QLF_SP,  /* SP.  */
 459
 460   /* Qualifying an operand which is a floating-point register, a SIMD
 461      vector element or a SIMD vector element list; indicating operand data
 462      size or the size of each SIMD vector element in the case of a SIMD
 463      vector element list.
 464      These qualifiers are also used to qualify an address operand to
 465      indicate the size of data element a load/store instruction is
 466      accessing.
 467      They are also used for the immediate shift operand in e.g. SSHR.  Such
 468      a use is only for the ease of operand encoding/decoding and qualifier
 469      sequence matching; such a use should not be applied widely; use the value
 470      constraint qualifiers for immediate operands wherever possible.  */
 471   AARCH64_OPND_QLF_S_B,
 472   AARCH64_OPND_QLF_S_H,
 473   AARCH64_OPND_QLF_S_S,
 474   AARCH64_OPND_QLF_S_D,
 475   AARCH64_OPND_QLF_S_Q,
 476   /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
 477      or 2 x 2 byte are selected by the instruction.  Other than that they have
 478      no difference with AARCH64_OPND_QLF_S_B in encoding.  They are here purely
 479      for syntactical reasons and is an exception from normal AArch64
 480      disassembly scheme.  */
 481   AARCH64_OPND_QLF_S_4B,
 482   AARCH64_OPND_QLF_S_2H,
 483
 484   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 485      register list; indicating register shape.
 486      They are also used for the immediate shift operand in e.g. SSHR.  Such
 487      a use is only for the ease of operand encoding/decoding and qualifier
 488      sequence matching; such a use should not be applied widely; use the value
 489      constraint qualifiers for immediate operands wherever possible.  */
 490   AARCH64_OPND_QLF_V_4B,
 491   AARCH64_OPND_QLF_V_8B,
 492   AARCH64_OPND_QLF_V_16B,
 493   AARCH64_OPND_QLF_V_2H,
 494   AARCH64_OPND_QLF_V_4H,
 495   AARCH64_OPND_QLF_V_8H,
 496   AARCH64_OPND_QLF_V_2S,
 497   AARCH64_OPND_QLF_V_4S,
 498   AARCH64_OPND_QLF_V_1D,
 499   AARCH64_OPND_QLF_V_2D,
 500   AARCH64_OPND_QLF_V_1Q,
 501
 502   AARCH64_OPND_QLF_P_Z,
 503   AARCH64_OPND_QLF_P_M,
 504
 505   /* Used in scaled signed immediate that are scaled by a Tag granule
 506      like in stg, st2g, etc.   */
 507   AARCH64_OPND_QLF_imm_tag,
 508
 509   /* Constraint on value.  */
 510   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 511   AARCH64_OPND_QLF_imm_0_7,
 512   AARCH64_OPND_QLF_imm_0_15,
 513   AARCH64_OPND_QLF_imm_0_31,
 514   AARCH64_OPND_QLF_imm_0_63,
 515   AARCH64_OPND_QLF_imm_1_32,
 516   AARCH64_OPND_QLF_imm_1_64,
 517
 518   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 519      or shift-ones.  */
 520   AARCH64_OPND_QLF_LSL,
 521   AARCH64_OPND_QLF_MSL,
 522
 523   /* Special qualifier helping retrieve qualifier information during the
 524      decoding time (currently not in use).  */
 525   AARCH64_OPND_QLF_RETRIEVE,
 526 };
 527 \f
 528 /* Instruction class.  */
 529
 530 enum aarch64_insn_class
 531 {
 532   aarch64_misc,
 533   addsub_carry,
 534   addsub_ext,
 535   addsub_imm,
 536   addsub_shift,
 537   asimdall,
 538   asimddiff,
 539   asimdelem,
 540   asimdext,
 541   asimdimm,
 542   asimdins,
 543   asimdmisc,
 544   asimdperm,
 545   asimdsame,
 546   asimdshf,
 547   asimdtbl,
 548   asisddiff,
 549   asisdelem,
 550   asisdlse,
 551   asisdlsep,
 552   asisdlso,
 553   asisdlsop,
 554   asisdmisc,
 555   asisdone,
 556   asisdpair,
 557   asisdsame,
 558   asisdshf,
 559   bitfield,
 560   branch_imm,
 561   branch_reg,
 562   compbranch,
 563   condbranch,
 564   condcmp_imm,
 565   condcmp_reg,
 566   condsel,
 567   cryptoaes,
 568   cryptosha2,
 569   cryptosha3,
 570   dp_1src,
 571   dp_2src,
 572   dp_3src,
 573   exception,
 574   extract,
 575   float2fix,
 576   float2int,
 577   floatccmp,
 578   floatcmp,
 579   floatdp1,
 580   floatdp2,
 581   floatdp3,
 582   floatimm,
 583   floatsel,
 584   ldst_immpost,
 585   ldst_immpre,
 586   ldst_imm9,    /* immpost or immpre */
 587   ldst_imm10,   /* LDRAA/LDRAB */
 588   ldst_pos,
 589   ldst_regoff,
 590   ldst_unpriv,
 591   ldst_unscaled,
 592   ldstexcl,
 593   ldstnapair_offs,
 594   ldstpair_off,
 595   ldstpair_indexed,
 596   loadlit,
 597   log_imm,
 598   log_shift,
 599   lse_atomic,
 600   movewide,
 601   pcreladdr,
 602   ic_system,
 603   sve_cpy,
 604   sve_index,
 605   sve_limm,
 606   sve_misc,
 607   sve_movprfx,
 608   sve_pred_zm,
 609   sve_shift_pred,
 610   sve_shift_unpred,
 611   sve_size_bhs,
 612   sve_size_bhsd,
 613   sve_size_hsd,
 614   sve_size_hsd2,
 615   sve_size_sd,
 616   sve_size_bh,
 617   sve_size_sd2,
 618   sve_size_13,
 619   sve_shift_tsz_hsd,
 620   sve_shift_tsz_bhsd,
 621   sve_size_tsz_bhs,
 622   testbranch,
 623   cryptosm3,
 624   cryptosm4,
 625   dotproduct,
 626   bfloat16,
 627 };
 628
 629 /* Opcode enumerators.  */
 630
 631 enum aarch64_op
 632 {
 633   OP_NIL,
 634   OP_STRB_POS,
 635   OP_LDRB_POS,
 636   OP_LDRSB_POS,
 637   OP_STRH_POS,
 638   OP_LDRH_POS,
 639   OP_LDRSH_POS,
 640   OP_STR_POS,
 641   OP_LDR_POS,
 642   OP_STRF_POS,
 643   OP_LDRF_POS,
 644   OP_LDRSW_POS,
 645   OP_PRFM_POS,
 646
 647   OP_STURB,
 648   OP_LDURB,
 649   OP_LDURSB,
 650   OP_STURH,
 651   OP_LDURH,
 652   OP_LDURSH,
 653   OP_STUR,
 654   OP_LDUR,
 655   OP_STURV,
 656   OP_LDURV,
 657   OP_LDURSW,
 658   OP_PRFUM,
 659
 660   OP_LDR_LIT,
 661   OP_LDRV_LIT,
 662   OP_LDRSW_LIT,
 663   OP_PRFM_LIT,
 664
 665   OP_ADD,
 666   OP_B,
 667   OP_BL,
 668
 669   OP_MOVN,
 670   OP_MOVZ,
 671   OP_MOVK,
 672
 673   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 674   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 675   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 676
 677   OP_MOV_V,             /* MOV alias for moving vector register.  */
 678
 679   OP_ASR_IMM,
 680   OP_LSR_IMM,
 681   OP_LSL_IMM,
 682
 683   OP_BIC,
 684
 685   OP_UBFX,
 686   OP_BFXIL,
 687   OP_SBFX,
 688   OP_SBFIZ,
 689   OP_BFI,
 690   OP_BFC,               /* ARMv8.2.  */
 691   OP_UBFIZ,
 692   OP_UXTB,
 693   OP_UXTH,
 694   OP_UXTW,
 695
 696   OP_CINC,
 697   OP_CINV,
 698   OP_CNEG,
 699   OP_CSET,
 700   OP_CSETM,
 701
 702   OP_FCVT,
 703   OP_FCVTN,
 704   OP_FCVTN2,
 705   OP_FCVTL,
 706   OP_FCVTL2,
 707   OP_FCVTXN_S,          /* Scalar version.  */
 708
 709   OP_ROR_IMM,
 710
 711   OP_SXTL,
 712   OP_SXTL2,
 713   OP_UXTL,
 714   OP_UXTL2,
 715
 716   OP_MOV_P_P,
 717   OP_MOV_Z_P_Z,
 718   OP_MOV_Z_V,
 719   OP_MOV_Z_Z,
 720   OP_MOV_Z_Zi,
 721   OP_MOVM_P_P_P,
 722   OP_MOVS_P_P,
 723   OP_MOVZS_P_P_P,
 724   OP_MOVZ_P_P_P,
 725   OP_NOTS_P_P_P_Z,
 726   OP_NOT_P_P_P_Z,
 727
 728   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 729
 730   OP_TOTAL_NUM,         /* Pseudo.  */
 731 };
 732
 733 /* Error types.  */
 734 enum err_type
 735 {
 736   ERR_OK,
 737   ERR_UND,
 738   ERR_UNP,
 739   ERR_NYI,
 740   ERR_VFI,
 741   ERR_NR_ENTRIES
 742 };
 743
 744 /* Maximum number of operands an instruction can have.  */
 745 #define AARCH64_MAX_OPND_NUM 6
 746 /* Maximum number of qualifier sequences an instruction can have.  */
 747 #define AARCH64_MAX_QLF_SEQ_NUM 10
 748 /* Operand qualifier typedef; optimized for the size.  */
 749 typedef unsigned char aarch64_opnd_qualifier_t;
 750 /* Operand qualifier sequence typedef.  */
 751 typedef aarch64_opnd_qualifier_t        \
 752           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 753
 754 /* FIXME: improve the efficiency.  */
 755 static inline bfd_boolean
 756 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 757 {
 758   int i;
 759   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 760     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 761       return FALSE;
 762   return TRUE;
 763 }
 764
 765 /*  Forward declare error reporting type.  */
 766 typedef struct aarch64_operand_error aarch64_operand_error;
 767 /* Forward declare instruction sequence type.  */
 768 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 769 /* Forward declare instruction definition.  */
 770 typedef struct aarch64_inst aarch64_inst;
 771
 772 /* This structure holds information for a particular opcode.  */
 773
 774 struct aarch64_opcode
 775 {
 776   /* The name of the mnemonic.  */
 777   const char *name;
 778
 779   /* The opcode itself.  Those bits which will be filled in with
 780      operands are zeroes.  */
 781   aarch64_insn opcode;
 782
 783   /* The opcode mask.  This is used by the disassembler.  This is a
 784      mask containing ones indicating those bits which must match the
 785      opcode field, and zeroes indicating those bits which need not
 786      match (and are presumably filled in by operands).  */
 787   aarch64_insn mask;
 788
 789   /* Instruction class.  */
 790   enum aarch64_insn_class iclass;
 791
 792   /* Enumerator identifier.  */
 793   enum aarch64_op op;
 794
 795   /* Which architecture variant provides this instruction.  */
 796   const aarch64_feature_set *avariant;
 797
 798   /* An array of operand codes.  Each code is an index into the
 799      operand table.  They appear in the order which the operands must
 800      appear in assembly code, and are terminated by a zero.  */
 801   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 802
 803   /* A list of operand qualifier code sequence.  Each operand qualifier
 804      code qualifies the corresponding operand code.  Each operand
 805      qualifier sequence specifies a valid opcode variant and related
 806      constraint on operands.  */
 807   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 808
 809   /* Flags providing information about this instruction */
 810   uint64_t flags;
 811
 812   /* Extra constraints on the instruction that the verifier checks.  */
 813   uint32_t constraints;
 814
 815   /* If nonzero, this operand and operand 0 are both registers and
 816      are required to have the same register number.  */
 817   unsigned char tied_operand;
 818
 819   /* If non-NULL, a function to verify that a given instruction is valid.  */
 820   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 821                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 822                               struct aarch64_instr_sequence *);
 823 };
 824
 825 typedef struct aarch64_opcode aarch64_opcode;
 826
 827 /* Table describing all the AArch64 opcodes.  */
 828 extern aarch64_opcode aarch64_opcode_table[];
 829
 830 /* Opcode flags.  */
 831 #define F_ALIAS (1 << 0)
 832 #define F_HAS_ALIAS (1 << 1)
 833 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 834    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 835 #define F_P1 (1 << 2)
 836 #define F_P2 (2 << 2)
 837 #define F_P3 (3 << 2)
 838 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 839 #define F_COND (1 << 4)
 840 /* Instruction has the field of 'sf'.  */
 841 #define F_SF (1 << 5)
 842 /* Instruction has the field of 'size:Q'.  */
 843 #define F_SIZEQ (1 << 6)
 844 /* Floating-point instruction has the field of 'type'.  */
 845 #define F_FPTYPE (1 << 7)
 846 /* AdvSIMD scalar instruction has the field of 'size'.  */
 847 #define F_SSIZE (1 << 8)
 848 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 849 #define F_T (1 << 9)
 850 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 851 #define F_GPRSIZE_IN_Q (1 << 10)
 852 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 853 #define F_LDS_SIZE (1 << 11)
 854 /* Optional operand; assume maximum of 1 operand can be optional.  */
 855 #define F_OPD0_OPT (1 << 12)
 856 #define F_OPD1_OPT (2 << 12)
 857 #define F_OPD2_OPT (3 << 12)
 858 #define F_OPD3_OPT (4 << 12)
 859 #define F_OPD4_OPT (5 << 12)
 860 /* Default value for the optional operand when omitted from the assembly.  */
 861 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 862 /* Instruction that is an alias of another instruction needs to be
 863    encoded/decoded by converting it to/from the real form, followed by
 864    the encoding/decoding according to the rules of the real opcode.
 865    This compares to the direct coding using the alias's information.
 866    N.B. this flag requires F_ALIAS to be used together.  */
 867 #define F_CONV (1 << 20)
 868 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 869    friendly pseudo instruction available only in the assembly code (thus will
 870    not show up in the disassembly).  */
 871 #define F_PSEUDO (1 << 21)
 872 /* Instruction has miscellaneous encoding/decoding rules.  */
 873 #define F_MISC (1 << 22)
 874 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 875 #define F_N (1 << 23)
 876 /* Opcode dependent field.  */
 877 #define F_OD(X) (((X) & 0x7) << 24)
 878 /* Instruction has the field of 'sz'.  */
 879 #define F_LSE_SZ (1 << 27)
 880 /* Require an exact qualifier match, even for NIL qualifiers.  */
 881 #define F_STRICT (1ULL << 28)
 882 /* This system instruction is used to read system registers.  */
 883 #define F_SYS_READ (1ULL << 29)
 884 /* This system instruction is used to write system registers.  */
 885 #define F_SYS_WRITE (1ULL << 30)
 886 /* This instruction has an extra constraint on it that imposes a requirement on
 887    subsequent instructions.  */
 888 #define F_SCAN (1ULL << 31)
 889 /* Next bit is 32.  */
 890
 891 /* Instruction constraints.  */
 892 /* This instruction has a predication constraint on the instruction at PC+4.  */
 893 #define C_SCAN_MOVPRFX (1U << 0)
 894 /* This instruction's operation width is determined by the operand with the
 895    largest element size.  */
 896 #define C_MAX_ELEM (1U << 1)
 897 /* Next bit is 2.  */
 898
 899 static inline bfd_boolean
 900 alias_opcode_p (const aarch64_opcode *opcode)
 901 {
 902   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 903 }
 904
 905 static inline bfd_boolean
 906 opcode_has_alias (const aarch64_opcode *opcode)
 907 {
 908   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 909 }
 910
 911 /* Priority for disassembling preference.  */
 912 static inline int
 913 opcode_priority (const aarch64_opcode *opcode)
 914 {
 915   return (opcode->flags >> 2) & 0x3;
 916 }
 917
 918 static inline bfd_boolean
 919 pseudo_opcode_p (const aarch64_opcode *opcode)
 920 {
 921   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 922 }
 923
 924 static inline bfd_boolean
 925 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 926 {
 927   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 928     ? TRUE : FALSE;
 929 }
 930
 931 static inline aarch64_insn
 932 get_optional_operand_default_value (const aarch64_opcode *opcode)
 933 {
 934   return (opcode->flags >> 15) & 0x1f;
 935 }
 936
 937 static inline unsigned int
 938 get_opcode_dependent_value (const aarch64_opcode *opcode)
 939 {
 940   return (opcode->flags >> 24) & 0x7;
 941 }
 942
 943 static inline bfd_boolean
 944 opcode_has_special_coder (const aarch64_opcode *opcode)
 945 {
 946   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 947           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 948     : FALSE;
 949 }
 950 \f
 951 struct aarch64_name_value_pair
 952 {
 953   const char *  name;
 954   aarch64_insn  value;
 955 };
 956
 957 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 958 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 959 extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
 960 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 961 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 962
 963 #define AARCH64_MAX_SYSREG_NAME_LEN 32
 964
 965 typedef struct
 966 {
 967   const char *  name;
 968   aarch64_insn  value;
 969   uint32_t      flags;
 970
 971   /* A set of features, all of which are required for this system register to be
 972      available.  */
 973   aarch64_feature_set features;
 974 } aarch64_sys_reg;
 975
 976 extern const aarch64_sys_reg aarch64_sys_regs [];
 977 extern const aarch64_sys_reg aarch64_pstatefields [];
 978 extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
 979 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 980                                                     const aarch64_sys_reg *);
 981
 982 typedef struct
 983 {
 984   const char *name;
 985   uint32_t value;
 986   uint32_t flags ;
 987 } aarch64_sys_ins_reg;
 988
 989 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 990 extern bfd_boolean
 991 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 992                                  const char *reg_name, aarch64_insn,
 993                                  uint32_t, aarch64_feature_set);
 994
 995 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 996 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 997 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 998 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 999 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
1000
1001 /* Shift/extending operator kinds.
1002    N.B. order is important; keep aarch64_operand_modifiers synced.  */
1003 enum aarch64_modifier_kind
1004 {
1005   AARCH64_MOD_NONE,
1006   AARCH64_MOD_MSL,
1007   AARCH64_MOD_ROR,
1008   AARCH64_MOD_ASR,
1009   AARCH64_MOD_LSR,
1010   AARCH64_MOD_LSL,
1011   AARCH64_MOD_UXTB,
1012   AARCH64_MOD_UXTH,
1013   AARCH64_MOD_UXTW,
1014   AARCH64_MOD_UXTX,
1015   AARCH64_MOD_SXTB,
1016   AARCH64_MOD_SXTH,
1017   AARCH64_MOD_SXTW,
1018   AARCH64_MOD_SXTX,
1019   AARCH64_MOD_MUL,
1020   AARCH64_MOD_MUL_VL,
1021 };
1022
1023 bfd_boolean
1024 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1025
1026 enum aarch64_modifier_kind
1027 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1028 /* Condition.  */
1029
1030 typedef struct
1031 {
1032   /* A list of names with the first one as the disassembly preference;
1033      terminated by NULL if fewer than 3.  */
1034   const char *names[4];
1035   aarch64_insn value;
1036 } aarch64_cond;
1037
1038 extern const aarch64_cond aarch64_conds[16];
1039
1040 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1041 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1042 \f
1043 /* Structure representing an operand.  */
1044
1045 struct aarch64_opnd_info
1046 {
1047   enum aarch64_opnd type;
1048   aarch64_opnd_qualifier_t qualifier;
1049   int idx;
1050
1051   union
1052     {
1053       struct
1054         {
1055           unsigned regno;
1056         } reg;
1057       struct
1058         {
1059           unsigned int regno;
1060           int64_t index;
1061         } reglane;
1062       /* e.g. LVn.  */
1063       struct
1064         {
1065           unsigned first_regno : 5;
1066           unsigned num_regs : 3;
1067           /* 1 if it is a list of reg element.  */
1068           unsigned has_index : 1;
1069           /* Lane index; valid only when has_index is 1.  */
1070           int64_t index;
1071         } reglist;
1072       /* e.g. immediate or pc relative address offset.  */
1073       struct
1074         {
1075           int64_t value;
1076           unsigned is_fp : 1;
1077         } imm;
1078       /* e.g. address in STR (register offset).  */
1079       struct
1080         {
1081           unsigned base_regno;
1082           struct
1083             {
1084               union
1085                 {
1086                   int imm;
1087                   unsigned regno;
1088                 };
1089               unsigned is_reg;
1090             } offset;
1091           unsigned pcrel : 1;           /* PC-relative.  */
1092           unsigned writeback : 1;
1093           unsigned preind : 1;          /* Pre-indexed.  */
1094           unsigned postind : 1;         /* Post-indexed.  */
1095         } addr;
1096
1097       struct
1098         {
1099           /* The encoding of the system register.  */
1100           aarch64_insn value;
1101
1102           /* The system register flags.  */
1103           uint32_t flags;
1104         } sysreg;
1105
1106       const aarch64_cond *cond;
1107       /* The encoding of the PSTATE field.  */
1108       aarch64_insn pstatefield;
1109       const aarch64_sys_ins_reg *sysins_op;
1110       const struct aarch64_name_value_pair *barrier;
1111       const struct aarch64_name_value_pair *hint_option;
1112       const struct aarch64_name_value_pair *prfop;
1113     };
1114
1115   /* Operand shifter; in use when the operand is a register offset address,
1116      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1117   struct
1118     {
1119       enum aarch64_modifier_kind kind;
1120       unsigned operator_present: 1;     /* Only valid during encoding.  */
1121       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1122       unsigned amount_present: 1;
1123       int64_t amount;
1124     } shifter;
1125
1126   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1127                            to be done on it.  In some (but not all) of these
1128                            cases, we need to tell libopcodes to skip the
1129                            constraint checking and the encoding for this
1130                            operand, so that the libopcodes can pick up the
1131                            right opcode before the operand is fixed-up.  This
1132                            flag should only be used during the
1133                            assembling/encoding.  */
1134   unsigned present:1;   /* Whether this operand is present in the assembly
1135                            line; not used during the disassembly.  */
1136 };
1137
1138 typedef struct aarch64_opnd_info aarch64_opnd_info;
1139
1140 /* Structure representing an instruction.
1141
1142    It is used during both the assembling and disassembling.  The assembler
1143    fills an aarch64_inst after a successful parsing and then passes it to the
1144    encoding routine to do the encoding.  During the disassembling, the
1145    disassembler calls the decoding routine to decode a binary instruction; on a
1146    successful return, such a structure will be filled with information of the
1147    instruction; then the disassembler uses the information to print out the
1148    instruction.  */
1149
1150 struct aarch64_inst
1151 {
1152   /* The value of the binary instruction.  */
1153   aarch64_insn value;
1154
1155   /* Corresponding opcode entry.  */
1156   const aarch64_opcode *opcode;
1157
1158   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1159   const aarch64_cond *cond;
1160
1161   /* Operands information.  */
1162   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1163 };
1164
1165 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1166 #define HINT_OPD_CSYNC  0x11
1167 #define HINT_OPD_C      0x22
1168 #define HINT_OPD_J      0x24
1169 #define HINT_OPD_JC     0x26
1170 #define HINT_OPD_NULL   0x00
1171
1172 \f
1173 /* Diagnosis related declaration and interface.  */
1174
1175 /* Operand error kind enumerators.
1176
1177    AARCH64_OPDE_RECOVERABLE
1178      Less severe error found during the parsing, very possibly because that
1179      GAS has picked up a wrong instruction template for the parsing.
1180
1181    AARCH64_OPDE_SYNTAX_ERROR
1182      General syntax error; it can be either a user error, or simply because
1183      that GAS is trying a wrong instruction template.
1184
1185    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1186      Definitely a user syntax error.
1187
1188    AARCH64_OPDE_INVALID_VARIANT
1189      No syntax error, but the operands are not a valid combination, e.g.
1190      FMOV D0,S0
1191
1192    AARCH64_OPDE_UNTIED_OPERAND
1193      The asm failed to use the same register for a destination operand
1194      and a tied source operand.
1195
1196    AARCH64_OPDE_OUT_OF_RANGE
1197      Error about some immediate value out of a valid range.
1198
1199    AARCH64_OPDE_UNALIGNED
1200      Error about some immediate value not properly aligned (i.e. not being a
1201      multiple times of a certain value).
1202
1203    AARCH64_OPDE_REG_LIST
1204      Error about the register list operand having unexpected number of
1205      registers.
1206
1207    AARCH64_OPDE_OTHER_ERROR
1208      Error of the highest severity and used for any severe issue that does not
1209      fall into any of the above categories.
1210
1211    The enumerators are only interesting to GAS.  They are declared here (in
1212    libopcodes) because that some errors are detected (and then notified to GAS)
1213    by libopcodes (rather than by GAS solely).
1214
1215    The first three errors are only deteced by GAS while the
1216    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1217    only libopcodes has the information about the valid variants of each
1218    instruction.
1219
1220    The enumerators have an increasing severity.  This is helpful when there are
1221    multiple instruction templates available for a given mnemonic name (e.g.
1222    FMOV); this mechanism will help choose the most suitable template from which
1223    the generated diagnostics can most closely describe the issues, if any.  */
1224
1225 enum aarch64_operand_error_kind
1226 {
1227   AARCH64_OPDE_NIL,
1228   AARCH64_OPDE_RECOVERABLE,
1229   AARCH64_OPDE_SYNTAX_ERROR,
1230   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1231   AARCH64_OPDE_INVALID_VARIANT,
1232   AARCH64_OPDE_UNTIED_OPERAND,
1233   AARCH64_OPDE_OUT_OF_RANGE,
1234   AARCH64_OPDE_UNALIGNED,
1235   AARCH64_OPDE_REG_LIST,
1236   AARCH64_OPDE_OTHER_ERROR
1237 };
1238
1239 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1240 struct aarch64_operand_error
1241 {
1242   enum aarch64_operand_error_kind kind;
1243   int index;
1244   const char *error;
1245   int data[3];  /* Some data for extra information.  */
1246   bfd_boolean non_fatal;
1247 };
1248
1249 /* AArch64 sequence structure used to track instructions with F_SCAN
1250    dependencies for both assembler and disassembler.  */
1251 struct aarch64_instr_sequence
1252 {
1253   /* The instruction that caused this sequence to be opened.  */
1254   aarch64_inst *instr;
1255   /* The number of instructions the above instruction allows to be kept in the
1256      sequence before an automatic close is done.  */
1257   int num_insns;
1258   /* The instructions currently added to the sequence.  */
1259   aarch64_inst **current_insns;
1260   /* The number of instructions already in the sequence.  */
1261   int next_insn;
1262 };
1263
1264 /* Encoding entrypoint.  */
1265
1266 extern int
1267 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1268                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1269                        aarch64_operand_error *, aarch64_instr_sequence *);
1270
1271 extern const aarch64_opcode *
1272 aarch64_replace_opcode (struct aarch64_inst *,
1273                         const aarch64_opcode *);
1274
1275 /* Given the opcode enumerator OP, return the pointer to the corresponding
1276    opcode entry.  */
1277
1278 extern const aarch64_opcode *
1279 aarch64_get_opcode (enum aarch64_op);
1280
1281 /* Generate the string representation of an operand.  */
1282 extern void
1283 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1284                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1285                        char **,
1286                        aarch64_feature_set features);
1287
1288 /* Miscellaneous interface.  */
1289
1290 extern int
1291 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1292
1293 extern aarch64_opnd_qualifier_t
1294 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1295                                 const aarch64_opnd_qualifier_t, int);
1296
1297 extern bfd_boolean
1298 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1299
1300 extern int
1301 aarch64_num_of_operands (const aarch64_opcode *);
1302
1303 extern int
1304 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1305
1306 extern int
1307 aarch64_zero_register_p (const aarch64_opnd_info *);
1308
1309 extern enum err_type
1310 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1311                      aarch64_operand_error *);
1312
1313 extern void
1314 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1315
1316 /* Given an operand qualifier, return the expected data element size
1317    of a qualified operand.  */
1318 extern unsigned char
1319 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1320
1321 extern enum aarch64_operand_class
1322 aarch64_get_operand_class (enum aarch64_opnd);
1323
1324 extern const char *
1325 aarch64_get_operand_name (enum aarch64_opnd);
1326
1327 extern const char *
1328 aarch64_get_operand_desc (enum aarch64_opnd);
1329
1330 extern bfd_boolean
1331 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1332
1333 #ifdef DEBUG_AARCH64
1334 extern int debug_dump;
1335
1336 extern void
1337 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1338
1339 #define DEBUG_TRACE(M, ...)                                     \
1340   {                                                             \
1341     if (debug_dump)                                             \
1342       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1343   }
1344
1345 #define DEBUG_TRACE_IF(C, M, ...)                               \
1346   {                                                             \
1347     if (debug_dump && (C))                                      \
1348       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1349   }
1350 #else  /* !DEBUG_AARCH64 */
1351 #define DEBUG_TRACE(M, ...) ;
1352 #define DEBUG_TRACE_IF(C, M, ...) ;
1353 #endif /* DEBUG_AARCH64 */
1354
1355 extern const char *const aarch64_sve_pattern_array[32];
1356 extern const char *const aarch64_sve_prfop_array[16];
1357
1358 #ifdef __cplusplus
1359 }
1360 #endif
1361
1362 #endif /* OPCODE_AARCH64_H */