include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 204                            each condition flag.  */
 205
 206   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 207   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 208   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 209   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 210   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 211
 212   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 213   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 214
 215   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 216   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 217   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 218   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 219   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 220
 221   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 222   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 223   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 224   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 226                                    negative or unaligned and there is
 227                                    no writeback allowed.  This operand code
 228                                    is only used to support the programmer-
 229                                    friendly feature of using LDR/STR as the
 230                                    the mnemonic name for LDUR/STUR instructions
 231                                    wherever there is no ambiguity.  */
 232   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 233   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 234   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 235
 236   AARCH64_OPND_SYSREG,          /* System register operand.  */
 237   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 238   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 239   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 240   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 241   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 242   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 243   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 244   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 245   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 246
 247   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 248   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 249   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 250   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 251   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 252   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 253   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 254   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 255   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 256   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 257   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 258   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 259   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 260   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 261   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 262   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 263   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 264   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 265 };
 266
 267 /* Qualifier constrains an operand.  It either specifies a variant of an
 268    operand type or limits values available to an operand type.
 269
 270    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 271
 272 enum aarch64_opnd_qualifier
 273 {
 274   /* Indicating no further qualification on an operand.  */
 275   AARCH64_OPND_QLF_NIL,
 276
 277   /* Qualifying an operand which is a general purpose (integer) register;
 278      indicating the operand data size or a specific register.  */
 279   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 280   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 281   AARCH64_OPND_QLF_WSP, /* WSP.  */
 282   AARCH64_OPND_QLF_SP,  /* SP.  */
 283
 284   /* Qualifying an operand which is a floating-point register, a SIMD
 285      vector element or a SIMD vector element list; indicating operand data
 286      size or the size of each SIMD vector element in the case of a SIMD
 287      vector element list.
 288      These qualifiers are also used to qualify an address operand to
 289      indicate the size of data element a load/store instruction is
 290      accessing.
 291      They are also used for the immediate shift operand in e.g. SSHR.  Such
 292      a use is only for the ease of operand encoding/decoding and qualifier
 293      sequence matching; such a use should not be applied widely; use the value
 294      constraint qualifiers for immediate operands wherever possible.  */
 295   AARCH64_OPND_QLF_S_B,
 296   AARCH64_OPND_QLF_S_H,
 297   AARCH64_OPND_QLF_S_S,
 298   AARCH64_OPND_QLF_S_D,
 299   AARCH64_OPND_QLF_S_Q,
 300
 301   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 302      register list; indicating register shape.
 303      They are also used for the immediate shift operand in e.g. SSHR.  Such
 304      a use is only for the ease of operand encoding/decoding and qualifier
 305      sequence matching; such a use should not be applied widely; use the value
 306      constraint qualifiers for immediate operands wherever possible.  */
 307   AARCH64_OPND_QLF_V_8B,
 308   AARCH64_OPND_QLF_V_16B,
 309   AARCH64_OPND_QLF_V_2H,
 310   AARCH64_OPND_QLF_V_4H,
 311   AARCH64_OPND_QLF_V_8H,
 312   AARCH64_OPND_QLF_V_2S,
 313   AARCH64_OPND_QLF_V_4S,
 314   AARCH64_OPND_QLF_V_1D,
 315   AARCH64_OPND_QLF_V_2D,
 316   AARCH64_OPND_QLF_V_1Q,
 317
 318   AARCH64_OPND_QLF_P_Z,
 319   AARCH64_OPND_QLF_P_M,
 320
 321   /* Constraint on value.  */
 322   AARCH64_OPND_QLF_imm_0_7,
 323   AARCH64_OPND_QLF_imm_0_15,
 324   AARCH64_OPND_QLF_imm_0_31,
 325   AARCH64_OPND_QLF_imm_0_63,
 326   AARCH64_OPND_QLF_imm_1_32,
 327   AARCH64_OPND_QLF_imm_1_64,
 328
 329   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 330      or shift-ones.  */
 331   AARCH64_OPND_QLF_LSL,
 332   AARCH64_OPND_QLF_MSL,
 333
 334   /* Special qualifier helping retrieve qualifier information during the
 335      decoding time (currently not in use).  */
 336   AARCH64_OPND_QLF_RETRIEVE,
 337 };
 338 \f
 339 /* Instruction class.  */
 340
 341 enum aarch64_insn_class
 342 {
 343   addsub_carry,
 344   addsub_ext,
 345   addsub_imm,
 346   addsub_shift,
 347   asimdall,
 348   asimddiff,
 349   asimdelem,
 350   asimdext,
 351   asimdimm,
 352   asimdins,
 353   asimdmisc,
 354   asimdperm,
 355   asimdsame,
 356   asimdshf,
 357   asimdtbl,
 358   asisddiff,
 359   asisdelem,
 360   asisdlse,
 361   asisdlsep,
 362   asisdlso,
 363   asisdlsop,
 364   asisdmisc,
 365   asisdone,
 366   asisdpair,
 367   asisdsame,
 368   asisdshf,
 369   bitfield,
 370   branch_imm,
 371   branch_reg,
 372   compbranch,
 373   condbranch,
 374   condcmp_imm,
 375   condcmp_reg,
 376   condsel,
 377   cryptoaes,
 378   cryptosha2,
 379   cryptosha3,
 380   dp_1src,
 381   dp_2src,
 382   dp_3src,
 383   exception,
 384   extract,
 385   float2fix,
 386   float2int,
 387   floatccmp,
 388   floatcmp,
 389   floatdp1,
 390   floatdp2,
 391   floatdp3,
 392   floatimm,
 393   floatsel,
 394   ldst_immpost,
 395   ldst_immpre,
 396   ldst_imm9,    /* immpost or immpre */
 397   ldst_pos,
 398   ldst_regoff,
 399   ldst_unpriv,
 400   ldst_unscaled,
 401   ldstexcl,
 402   ldstnapair_offs,
 403   ldstpair_off,
 404   ldstpair_indexed,
 405   loadlit,
 406   log_imm,
 407   log_shift,
 408   lse_atomic,
 409   movewide,
 410   pcreladdr,
 411   ic_system,
 412   testbranch,
 413 };
 414
 415 /* Opcode enumerators.  */
 416
 417 enum aarch64_op
 418 {
 419   OP_NIL,
 420   OP_STRB_POS,
 421   OP_LDRB_POS,
 422   OP_LDRSB_POS,
 423   OP_STRH_POS,
 424   OP_LDRH_POS,
 425   OP_LDRSH_POS,
 426   OP_STR_POS,
 427   OP_LDR_POS,
 428   OP_STRF_POS,
 429   OP_LDRF_POS,
 430   OP_LDRSW_POS,
 431   OP_PRFM_POS,
 432
 433   OP_STURB,
 434   OP_LDURB,
 435   OP_LDURSB,
 436   OP_STURH,
 437   OP_LDURH,
 438   OP_LDURSH,
 439   OP_STUR,
 440   OP_LDUR,
 441   OP_STURV,
 442   OP_LDURV,
 443   OP_LDURSW,
 444   OP_PRFUM,
 445
 446   OP_LDR_LIT,
 447   OP_LDRV_LIT,
 448   OP_LDRSW_LIT,
 449   OP_PRFM_LIT,
 450
 451   OP_ADD,
 452   OP_B,
 453   OP_BL,
 454
 455   OP_MOVN,
 456   OP_MOVZ,
 457   OP_MOVK,
 458
 459   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 460   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 461   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 462
 463   OP_MOV_V,             /* MOV alias for moving vector register.  */
 464
 465   OP_ASR_IMM,
 466   OP_LSR_IMM,
 467   OP_LSL_IMM,
 468
 469   OP_BIC,
 470
 471   OP_UBFX,
 472   OP_BFXIL,
 473   OP_SBFX,
 474   OP_SBFIZ,
 475   OP_BFI,
 476   OP_BFC,               /* ARMv8.2.  */
 477   OP_UBFIZ,
 478   OP_UXTB,
 479   OP_UXTH,
 480   OP_UXTW,
 481
 482   OP_CINC,
 483   OP_CINV,
 484   OP_CNEG,
 485   OP_CSET,
 486   OP_CSETM,
 487
 488   OP_FCVT,
 489   OP_FCVTN,
 490   OP_FCVTN2,
 491   OP_FCVTL,
 492   OP_FCVTL2,
 493   OP_FCVTXN_S,          /* Scalar version.  */
 494
 495   OP_ROR_IMM,
 496
 497   OP_SXTL,
 498   OP_SXTL2,
 499   OP_UXTL,
 500   OP_UXTL2,
 501
 502   OP_TOTAL_NUM,         /* Pseudo.  */
 503 };
 504
 505 /* Maximum number of operands an instruction can have.  */
 506 #define AARCH64_MAX_OPND_NUM 6
 507 /* Maximum number of qualifier sequences an instruction can have.  */
 508 #define AARCH64_MAX_QLF_SEQ_NUM 10
 509 /* Operand qualifier typedef; optimized for the size.  */
 510 typedef unsigned char aarch64_opnd_qualifier_t;
 511 /* Operand qualifier sequence typedef.  */
 512 typedef aarch64_opnd_qualifier_t        \
 513           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 514
 515 /* FIXME: improve the efficiency.  */
 516 static inline bfd_boolean
 517 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 518 {
 519   int i;
 520   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 521     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 522       return FALSE;
 523   return TRUE;
 524 }
 525
 526 /* This structure holds information for a particular opcode.  */
 527
 528 struct aarch64_opcode
 529 {
 530   /* The name of the mnemonic.  */
 531   const char *name;
 532
 533   /* The opcode itself.  Those bits which will be filled in with
 534      operands are zeroes.  */
 535   aarch64_insn opcode;
 536
 537   /* The opcode mask.  This is used by the disassembler.  This is a
 538      mask containing ones indicating those bits which must match the
 539      opcode field, and zeroes indicating those bits which need not
 540      match (and are presumably filled in by operands).  */
 541   aarch64_insn mask;
 542
 543   /* Instruction class.  */
 544   enum aarch64_insn_class iclass;
 545
 546   /* Enumerator identifier.  */
 547   enum aarch64_op op;
 548
 549   /* Which architecture variant provides this instruction.  */
 550   const aarch64_feature_set *avariant;
 551
 552   /* An array of operand codes.  Each code is an index into the
 553      operand table.  They appear in the order which the operands must
 554      appear in assembly code, and are terminated by a zero.  */
 555   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 556
 557   /* A list of operand qualifier code sequence.  Each operand qualifier
 558      code qualifies the corresponding operand code.  Each operand
 559      qualifier sequence specifies a valid opcode variant and related
 560      constraint on operands.  */
 561   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 562
 563   /* Flags providing information about this instruction */
 564   uint32_t flags;
 565
 566   /* If nonzero, this operand and operand 0 are both registers and
 567      are required to have the same register number.  */
 568   unsigned char tied_operand;
 569
 570   /* If non-NULL, a function to verify that a given instruction is valid.  */
 571   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 572 };
 573
 574 typedef struct aarch64_opcode aarch64_opcode;
 575
 576 /* Table describing all the AArch64 opcodes.  */
 577 extern aarch64_opcode aarch64_opcode_table[];
 578
 579 /* Opcode flags.  */
 580 #define F_ALIAS (1 << 0)
 581 #define F_HAS_ALIAS (1 << 1)
 582 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 583    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 584 #define F_P1 (1 << 2)
 585 #define F_P2 (2 << 2)
 586 #define F_P3 (3 << 2)
 587 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 588 #define F_COND (1 << 4)
 589 /* Instruction has the field of 'sf'.  */
 590 #define F_SF (1 << 5)
 591 /* Instruction has the field of 'size:Q'.  */
 592 #define F_SIZEQ (1 << 6)
 593 /* Floating-point instruction has the field of 'type'.  */
 594 #define F_FPTYPE (1 << 7)
 595 /* AdvSIMD scalar instruction has the field of 'size'.  */
 596 #define F_SSIZE (1 << 8)
 597 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 598 #define F_T (1 << 9)
 599 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 600 #define F_GPRSIZE_IN_Q (1 << 10)
 601 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 602 #define F_LDS_SIZE (1 << 11)
 603 /* Optional operand; assume maximum of 1 operand can be optional.  */
 604 #define F_OPD0_OPT (1 << 12)
 605 #define F_OPD1_OPT (2 << 12)
 606 #define F_OPD2_OPT (3 << 12)
 607 #define F_OPD3_OPT (4 << 12)
 608 #define F_OPD4_OPT (5 << 12)
 609 /* Default value for the optional operand when omitted from the assembly.  */
 610 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 611 /* Instruction that is an alias of another instruction needs to be
 612    encoded/decoded by converting it to/from the real form, followed by
 613    the encoding/decoding according to the rules of the real opcode.
 614    This compares to the direct coding using the alias's information.
 615    N.B. this flag requires F_ALIAS to be used together.  */
 616 #define F_CONV (1 << 20)
 617 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 618    friendly pseudo instruction available only in the assembly code (thus will
 619    not show up in the disassembly).  */
 620 #define F_PSEUDO (1 << 21)
 621 /* Instruction has miscellaneous encoding/decoding rules.  */
 622 #define F_MISC (1 << 22)
 623 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 624 #define F_N (1 << 23)
 625 /* Opcode dependent field.  */
 626 #define F_OD(X) (((X) & 0x7) << 24)
 627 /* Instruction has the field of 'sz'.  */
 628 #define F_LSE_SZ (1 << 27)
 629 /* Require an exact qualifier match, even for NIL qualifiers.  */
 630 #define F_STRICT (1ULL << 28)
 631 /* Next bit is 29.  */
 632
 633 static inline bfd_boolean
 634 alias_opcode_p (const aarch64_opcode *opcode)
 635 {
 636   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 637 }
 638
 639 static inline bfd_boolean
 640 opcode_has_alias (const aarch64_opcode *opcode)
 641 {
 642   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 643 }
 644
 645 /* Priority for disassembling preference.  */
 646 static inline int
 647 opcode_priority (const aarch64_opcode *opcode)
 648 {
 649   return (opcode->flags >> 2) & 0x3;
 650 }
 651
 652 static inline bfd_boolean
 653 pseudo_opcode_p (const aarch64_opcode *opcode)
 654 {
 655   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 656 }
 657
 658 static inline bfd_boolean
 659 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 660 {
 661   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 662     ? TRUE : FALSE;
 663 }
 664
 665 static inline aarch64_insn
 666 get_optional_operand_default_value (const aarch64_opcode *opcode)
 667 {
 668   return (opcode->flags >> 15) & 0x1f;
 669 }
 670
 671 static inline unsigned int
 672 get_opcode_dependent_value (const aarch64_opcode *opcode)
 673 {
 674   return (opcode->flags >> 24) & 0x7;
 675 }
 676
 677 static inline bfd_boolean
 678 opcode_has_special_coder (const aarch64_opcode *opcode)
 679 {
 680   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 681           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 682     : FALSE;
 683 }
 684 \f
 685 struct aarch64_name_value_pair
 686 {
 687   const char *  name;
 688   aarch64_insn  value;
 689 };
 690
 691 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 692 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 693 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 694 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 695
 696 typedef struct
 697 {
 698   const char *  name;
 699   aarch64_insn  value;
 700   uint32_t      flags;
 701 } aarch64_sys_reg;
 702
 703 extern const aarch64_sys_reg aarch64_sys_regs [];
 704 extern const aarch64_sys_reg aarch64_pstatefields [];
 705 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 706 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 707                                                 const aarch64_sys_reg *);
 708 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 709                                                     const aarch64_sys_reg *);
 710
 711 typedef struct
 712 {
 713   const char *name;
 714   uint32_t value;
 715   uint32_t flags ;
 716 } aarch64_sys_ins_reg;
 717
 718 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 719 extern bfd_boolean
 720 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 721                                  const aarch64_sys_ins_reg *);
 722
 723 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 724 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 725 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 726 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 727
 728 /* Shift/extending operator kinds.
 729    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 730 enum aarch64_modifier_kind
 731 {
 732   AARCH64_MOD_NONE,
 733   AARCH64_MOD_MSL,
 734   AARCH64_MOD_ROR,
 735   AARCH64_MOD_ASR,
 736   AARCH64_MOD_LSR,
 737   AARCH64_MOD_LSL,
 738   AARCH64_MOD_UXTB,
 739   AARCH64_MOD_UXTH,
 740   AARCH64_MOD_UXTW,
 741   AARCH64_MOD_UXTX,
 742   AARCH64_MOD_SXTB,
 743   AARCH64_MOD_SXTH,
 744   AARCH64_MOD_SXTW,
 745   AARCH64_MOD_SXTX,
 746 };
 747
 748 bfd_boolean
 749 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 750
 751 enum aarch64_modifier_kind
 752 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 753 /* Condition.  */
 754
 755 typedef struct
 756 {
 757   /* A list of names with the first one as the disassembly preference;
 758      terminated by NULL if fewer than 3.  */
 759   const char *names[3];
 760   aarch64_insn value;
 761 } aarch64_cond;
 762
 763 extern const aarch64_cond aarch64_conds[16];
 764
 765 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 766 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 767 \f
 768 /* Structure representing an operand.  */
 769
 770 struct aarch64_opnd_info
 771 {
 772   enum aarch64_opnd type;
 773   aarch64_opnd_qualifier_t qualifier;
 774   int idx;
 775
 776   union
 777     {
 778       struct
 779         {
 780           unsigned regno;
 781         } reg;
 782       struct
 783         {
 784           unsigned int regno;
 785           int64_t index;
 786         } reglane;
 787       /* e.g. LVn.  */
 788       struct
 789         {
 790           unsigned first_regno : 5;
 791           unsigned num_regs : 3;
 792           /* 1 if it is a list of reg element.  */
 793           unsigned has_index : 1;
 794           /* Lane index; valid only when has_index is 1.  */
 795           int64_t index;
 796         } reglist;
 797       /* e.g. immediate or pc relative address offset.  */
 798       struct
 799         {
 800           int64_t value;
 801           unsigned is_fp : 1;
 802         } imm;
 803       /* e.g. address in STR (register offset).  */
 804       struct
 805         {
 806           unsigned base_regno;
 807           struct
 808             {
 809               union
 810                 {
 811                   int imm;
 812                   unsigned regno;
 813                 };
 814               unsigned is_reg;
 815             } offset;
 816           unsigned pcrel : 1;           /* PC-relative.  */
 817           unsigned writeback : 1;
 818           unsigned preind : 1;          /* Pre-indexed.  */
 819           unsigned postind : 1;         /* Post-indexed.  */
 820         } addr;
 821       const aarch64_cond *cond;
 822       /* The encoding of the system register.  */
 823       aarch64_insn sysreg;
 824       /* The encoding of the PSTATE field.  */
 825       aarch64_insn pstatefield;
 826       const aarch64_sys_ins_reg *sysins_op;
 827       const struct aarch64_name_value_pair *barrier;
 828       const struct aarch64_name_value_pair *hint_option;
 829       const struct aarch64_name_value_pair *prfop;
 830     };
 831
 832   /* Operand shifter; in use when the operand is a register offset address,
 833      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 834   struct
 835     {
 836       enum aarch64_modifier_kind kind;
 837       int amount;
 838       unsigned operator_present: 1;     /* Only valid during encoding.  */
 839       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 840       unsigned amount_present: 1;
 841     } shifter;
 842
 843   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 844                            to be done on it.  In some (but not all) of these
 845                            cases, we need to tell libopcodes to skip the
 846                            constraint checking and the encoding for this
 847                            operand, so that the libopcodes can pick up the
 848                            right opcode before the operand is fixed-up.  This
 849                            flag should only be used during the
 850                            assembling/encoding.  */
 851   unsigned present:1;   /* Whether this operand is present in the assembly
 852                            line; not used during the disassembly.  */
 853 };
 854
 855 typedef struct aarch64_opnd_info aarch64_opnd_info;
 856
 857 /* Structure representing an instruction.
 858
 859    It is used during both the assembling and disassembling.  The assembler
 860    fills an aarch64_inst after a successful parsing and then passes it to the
 861    encoding routine to do the encoding.  During the disassembling, the
 862    disassembler calls the decoding routine to decode a binary instruction; on a
 863    successful return, such a structure will be filled with information of the
 864    instruction; then the disassembler uses the information to print out the
 865    instruction.  */
 866
 867 struct aarch64_inst
 868 {
 869   /* The value of the binary instruction.  */
 870   aarch64_insn value;
 871
 872   /* Corresponding opcode entry.  */
 873   const aarch64_opcode *opcode;
 874
 875   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 876   const aarch64_cond *cond;
 877
 878   /* Operands information.  */
 879   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 880 };
 881
 882 typedef struct aarch64_inst aarch64_inst;
 883 \f
 884 /* Diagnosis related declaration and interface.  */
 885
 886 /* Operand error kind enumerators.
 887
 888    AARCH64_OPDE_RECOVERABLE
 889      Less severe error found during the parsing, very possibly because that
 890      GAS has picked up a wrong instruction template for the parsing.
 891
 892    AARCH64_OPDE_SYNTAX_ERROR
 893      General syntax error; it can be either a user error, or simply because
 894      that GAS is trying a wrong instruction template.
 895
 896    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 897      Definitely a user syntax error.
 898
 899    AARCH64_OPDE_INVALID_VARIANT
 900      No syntax error, but the operands are not a valid combination, e.g.
 901      FMOV D0,S0
 902
 903    AARCH64_OPDE_UNTIED_OPERAND
 904      The asm failed to use the same register for a destination operand
 905      and a tied source operand.
 906
 907    AARCH64_OPDE_OUT_OF_RANGE
 908      Error about some immediate value out of a valid range.
 909
 910    AARCH64_OPDE_UNALIGNED
 911      Error about some immediate value not properly aligned (i.e. not being a
 912      multiple times of a certain value).
 913
 914    AARCH64_OPDE_REG_LIST
 915      Error about the register list operand having unexpected number of
 916      registers.
 917
 918    AARCH64_OPDE_OTHER_ERROR
 919      Error of the highest severity and used for any severe issue that does not
 920      fall into any of the above categories.
 921
 922    The enumerators are only interesting to GAS.  They are declared here (in
 923    libopcodes) because that some errors are detected (and then notified to GAS)
 924    by libopcodes (rather than by GAS solely).
 925
 926    The first three errors are only deteced by GAS while the
 927    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 928    only libopcodes has the information about the valid variants of each
 929    instruction.
 930
 931    The enumerators have an increasing severity.  This is helpful when there are
 932    multiple instruction templates available for a given mnemonic name (e.g.
 933    FMOV); this mechanism will help choose the most suitable template from which
 934    the generated diagnostics can most closely describe the issues, if any.  */
 935
 936 enum aarch64_operand_error_kind
 937 {
 938   AARCH64_OPDE_NIL,
 939   AARCH64_OPDE_RECOVERABLE,
 940   AARCH64_OPDE_SYNTAX_ERROR,
 941   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
 942   AARCH64_OPDE_INVALID_VARIANT,
 943   AARCH64_OPDE_UNTIED_OPERAND,
 944   AARCH64_OPDE_OUT_OF_RANGE,
 945   AARCH64_OPDE_UNALIGNED,
 946   AARCH64_OPDE_REG_LIST,
 947   AARCH64_OPDE_OTHER_ERROR
 948 };
 949
 950 /* N.B. GAS assumes that this structure work well with shallow copy.  */
 951 struct aarch64_operand_error
 952 {
 953   enum aarch64_operand_error_kind kind;
 954   int index;
 955   const char *error;
 956   int data[3];  /* Some data for extra information.  */
 957 };
 958
 959 typedef struct aarch64_operand_error aarch64_operand_error;
 960
 961 /* Encoding entrypoint.  */
 962
 963 extern int
 964 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
 965                        aarch64_insn *, aarch64_opnd_qualifier_t *,
 966                        aarch64_operand_error *);
 967
 968 extern const aarch64_opcode *
 969 aarch64_replace_opcode (struct aarch64_inst *,
 970                         const aarch64_opcode *);
 971
 972 /* Given the opcode enumerator OP, return the pointer to the corresponding
 973    opcode entry.  */
 974
 975 extern const aarch64_opcode *
 976 aarch64_get_opcode (enum aarch64_op);
 977
 978 /* Generate the string representation of an operand.  */
 979 extern void
 980 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
 981                        const aarch64_opnd_info *, int, int *, bfd_vma *);
 982
 983 /* Miscellaneous interface.  */
 984
 985 extern int
 986 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
 987
 988 extern aarch64_opnd_qualifier_t
 989 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
 990                                 const aarch64_opnd_qualifier_t, int);
 991
 992 extern int
 993 aarch64_num_of_operands (const aarch64_opcode *);
 994
 995 extern int
 996 aarch64_stack_pointer_p (const aarch64_opnd_info *);
 997
 998 extern int
 999 aarch64_zero_register_p (const aarch64_opnd_info *);
1000
1001 extern int
1002 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1003
1004 /* Given an operand qualifier, return the expected data element size
1005    of a qualified operand.  */
1006 extern unsigned char
1007 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1008
1009 extern enum aarch64_operand_class
1010 aarch64_get_operand_class (enum aarch64_opnd);
1011
1012 extern const char *
1013 aarch64_get_operand_name (enum aarch64_opnd);
1014
1015 extern const char *
1016 aarch64_get_operand_desc (enum aarch64_opnd);
1017
1018 #ifdef DEBUG_AARCH64
1019 extern int debug_dump;
1020
1021 extern void
1022 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1023
1024 #define DEBUG_TRACE(M, ...)                                     \
1025   {                                                             \
1026     if (debug_dump)                                             \
1027       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1028   }
1029
1030 #define DEBUG_TRACE_IF(C, M, ...)                               \
1031   {                                                             \
1032     if (debug_dump && (C))                                      \
1033       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1034   }
1035 #else  /* !DEBUG_AARCH64 */
1036 #define DEBUG_TRACE(M, ...) ;
1037 #define DEBUG_TRACE_IF(C, M, ...) ;
1038 #endif /* DEBUG_AARCH64 */
1039
1040 #ifdef __cplusplus
1041 }
1042 #endif
1043
1044 #endif /* OPCODE_AARCH64_H */