include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2016 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  41 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  42 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  43 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  44 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  45 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  46 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  47 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  48 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  49 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  50 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  51 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  52 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  53 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  54
  55 /* Architectures are the sum of the base and extensions.  */
  56 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  57                                                  AARCH64_FEATURE_FP  \
  58                                                  | AARCH64_FEATURE_SIMD)
  59 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  60                                                  AARCH64_FEATURE_FP  \
  61                                                  | AARCH64_FEATURE_SIMD \
  62                                                  | AARCH64_FEATURE_CRC  \
  63                                                  | AARCH64_FEATURE_V8_1 \
  64                                                  | AARCH64_FEATURE_LSE  \
  65                                                  | AARCH64_FEATURE_PAN  \
  66                                                  | AARCH64_FEATURE_LOR  \
  67                                                  | AARCH64_FEATURE_RDMA)
  68 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_FEATURE_V8,    \
  69                                                  AARCH64_FEATURE_V8_2   \
  70                                                  | AARCH64_FEATURE_F16  \
  71                                                  | AARCH64_FEATURE_RAS  \
  72                                                  | AARCH64_FEATURE_FP   \
  73                                                  | AARCH64_FEATURE_SIMD \
  74                                                  | AARCH64_FEATURE_CRC  \
  75                                                  | AARCH64_FEATURE_V8_1 \
  76                                                  | AARCH64_FEATURE_LSE  \
  77                                                  | AARCH64_FEATURE_PAN  \
  78                                                  | AARCH64_FEATURE_LOR  \
  79                                                  | AARCH64_FEATURE_RDMA)
  80
  81 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
  82 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
  83
  84 /* CPU-specific features.  */
  85 typedef unsigned long aarch64_feature_set;
  86
  87 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
  88   ((~(CPU) & (FEAT)) == 0)
  89
  90 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
  91   (((CPU) & (FEAT)) != 0)
  92
  93 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
  94   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
  95
  96 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
  97   do                                            \
  98     {                                           \
  99       (TARG) = (F1) | (F2);                     \
 100     }                                           \
 101   while (0)
 102
 103 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 104   do                                            \
 105     {                                           \
 106       (TARG) = (F1) &~ (F2);                    \
 107     }                                           \
 108   while (0)
 109
 110 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 111
 112 enum aarch64_operand_class
 113 {
 114   AARCH64_OPND_CLASS_NIL,
 115   AARCH64_OPND_CLASS_INT_REG,
 116   AARCH64_OPND_CLASS_MODIFIED_REG,
 117   AARCH64_OPND_CLASS_FP_REG,
 118   AARCH64_OPND_CLASS_SIMD_REG,
 119   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 120   AARCH64_OPND_CLASS_SISD_REG,
 121   AARCH64_OPND_CLASS_SIMD_REGLIST,
 122   AARCH64_OPND_CLASS_CP_REG,
 123   AARCH64_OPND_CLASS_SVE_REG,
 124   AARCH64_OPND_CLASS_PRED_REG,
 125   AARCH64_OPND_CLASS_ADDRESS,
 126   AARCH64_OPND_CLASS_IMMEDIATE,
 127   AARCH64_OPND_CLASS_SYSTEM,
 128   AARCH64_OPND_CLASS_COND,
 129 };
 130
 131 /* Operand code that helps both parsing and coding.
 132    Keep AARCH64_OPERANDS synced.  */
 133
 134 enum aarch64_opnd
 135 {
 136   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 137
 138   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 139   AARCH64_OPND_Rn,      /* Integer register as source.  */
 140   AARCH64_OPND_Rm,      /* Integer register as source.  */
 141   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 142   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 143   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 144   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 145   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 146
 147   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 148   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 149   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 150   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 151   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 152
 153   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 154   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 155   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 156   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 157   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 158   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 159
 160   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 161   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 162   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 163
 164   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 165   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 166   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 167   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 168   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 169   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 170   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 171   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 172   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 173   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 174   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 175                            structure to all lanes.  */
 176   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 177
 178   AARCH64_OPND_Cn,      /* Co-processor register in CRn field.  */
 179   AARCH64_OPND_Cm,      /* Co-processor register in CRm field.  */
 180
 181   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 182   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 183   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 184   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 185   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 186   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 187   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 188                            (no encoding).  */
 189   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 190   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 191   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 192   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 193   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 194   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 195   AARCH64_OPND_IMM,     /* Immediate.  */
 196   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 197   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 198   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 199   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 200   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 201   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 202   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 203   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 204   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 205                            each condition flag.  */
 206
 207   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 208   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 209   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 210   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 211   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 212
 213   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 214   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 215
 216   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 217   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 218   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 219   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 220   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 221
 222   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 223   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 224   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 225   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 226   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 227                                    negative or unaligned and there is
 228                                    no writeback allowed.  This operand code
 229                                    is only used to support the programmer-
 230                                    friendly feature of using LDR/STR as the
 231                                    the mnemonic name for LDUR/STUR instructions
 232                                    wherever there is no ambiguity.  */
 233   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 234   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 235   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 236
 237   AARCH64_OPND_SYSREG,          /* System register operand.  */
 238   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 239   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 240   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 241   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 242   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 243   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 244   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 245   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 246   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 247
 248   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 249   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 250   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 251   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 252   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 253   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 254   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 255   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 256   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 257   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 258   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 259   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 260   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 261   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 262   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 263   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 264   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 265   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 266   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 267   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 268   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 269   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 270   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 271                                        Bit 14 controls S/U choice.  */
 272   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 273                                        Bit 22 controls S/U choice.  */
 274   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 275                                        Bit 14 controls S/U choice.  */
 276   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 277                                        Bit 22 controls S/U choice.  */
 278   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 279                                        Bit 14 controls S/U choice.  */
 280   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 281                                        Bit 22 controls S/U choice.  */
 282   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 283                                        Bit 14 controls S/U choice.  */
 284   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 285                                        Bit 22 controls S/U choice.  */
 286   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 287   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 288   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 289   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 290   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 291   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 292   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 293   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 294   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 295   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 296   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 297   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 298   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 299   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 300   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 301   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 302   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 303   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 304   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 305   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 306   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 307   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 308   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 309   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 310   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 311   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 312   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 313   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 314   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 315   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 316   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 317   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 318   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 319   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 320   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 321   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 322   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 323   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 324   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 325   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 326   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 327   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 328   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 329   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 330   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 331 };
 332
 333 /* Qualifier constrains an operand.  It either specifies a variant of an
 334    operand type or limits values available to an operand type.
 335
 336    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 337
 338 enum aarch64_opnd_qualifier
 339 {
 340   /* Indicating no further qualification on an operand.  */
 341   AARCH64_OPND_QLF_NIL,
 342
 343   /* Qualifying an operand which is a general purpose (integer) register;
 344      indicating the operand data size or a specific register.  */
 345   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 346   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 347   AARCH64_OPND_QLF_WSP, /* WSP.  */
 348   AARCH64_OPND_QLF_SP,  /* SP.  */
 349
 350   /* Qualifying an operand which is a floating-point register, a SIMD
 351      vector element or a SIMD vector element list; indicating operand data
 352      size or the size of each SIMD vector element in the case of a SIMD
 353      vector element list.
 354      These qualifiers are also used to qualify an address operand to
 355      indicate the size of data element a load/store instruction is
 356      accessing.
 357      They are also used for the immediate shift operand in e.g. SSHR.  Such
 358      a use is only for the ease of operand encoding/decoding and qualifier
 359      sequence matching; such a use should not be applied widely; use the value
 360      constraint qualifiers for immediate operands wherever possible.  */
 361   AARCH64_OPND_QLF_S_B,
 362   AARCH64_OPND_QLF_S_H,
 363   AARCH64_OPND_QLF_S_S,
 364   AARCH64_OPND_QLF_S_D,
 365   AARCH64_OPND_QLF_S_Q,
 366
 367   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 368      register list; indicating register shape.
 369      They are also used for the immediate shift operand in e.g. SSHR.  Such
 370      a use is only for the ease of operand encoding/decoding and qualifier
 371      sequence matching; such a use should not be applied widely; use the value
 372      constraint qualifiers for immediate operands wherever possible.  */
 373   AARCH64_OPND_QLF_V_8B,
 374   AARCH64_OPND_QLF_V_16B,
 375   AARCH64_OPND_QLF_V_2H,
 376   AARCH64_OPND_QLF_V_4H,
 377   AARCH64_OPND_QLF_V_8H,
 378   AARCH64_OPND_QLF_V_2S,
 379   AARCH64_OPND_QLF_V_4S,
 380   AARCH64_OPND_QLF_V_1D,
 381   AARCH64_OPND_QLF_V_2D,
 382   AARCH64_OPND_QLF_V_1Q,
 383
 384   AARCH64_OPND_QLF_P_Z,
 385   AARCH64_OPND_QLF_P_M,
 386
 387   /* Constraint on value.  */
 388   AARCH64_OPND_QLF_imm_0_7,
 389   AARCH64_OPND_QLF_imm_0_15,
 390   AARCH64_OPND_QLF_imm_0_31,
 391   AARCH64_OPND_QLF_imm_0_63,
 392   AARCH64_OPND_QLF_imm_1_32,
 393   AARCH64_OPND_QLF_imm_1_64,
 394
 395   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 396      or shift-ones.  */
 397   AARCH64_OPND_QLF_LSL,
 398   AARCH64_OPND_QLF_MSL,
 399
 400   /* Special qualifier helping retrieve qualifier information during the
 401      decoding time (currently not in use).  */
 402   AARCH64_OPND_QLF_RETRIEVE,
 403 };
 404 \f
 405 /* Instruction class.  */
 406
 407 enum aarch64_insn_class
 408 {
 409   addsub_carry,
 410   addsub_ext,
 411   addsub_imm,
 412   addsub_shift,
 413   asimdall,
 414   asimddiff,
 415   asimdelem,
 416   asimdext,
 417   asimdimm,
 418   asimdins,
 419   asimdmisc,
 420   asimdperm,
 421   asimdsame,
 422   asimdshf,
 423   asimdtbl,
 424   asisddiff,
 425   asisdelem,
 426   asisdlse,
 427   asisdlsep,
 428   asisdlso,
 429   asisdlsop,
 430   asisdmisc,
 431   asisdone,
 432   asisdpair,
 433   asisdsame,
 434   asisdshf,
 435   bitfield,
 436   branch_imm,
 437   branch_reg,
 438   compbranch,
 439   condbranch,
 440   condcmp_imm,
 441   condcmp_reg,
 442   condsel,
 443   cryptoaes,
 444   cryptosha2,
 445   cryptosha3,
 446   dp_1src,
 447   dp_2src,
 448   dp_3src,
 449   exception,
 450   extract,
 451   float2fix,
 452   float2int,
 453   floatccmp,
 454   floatcmp,
 455   floatdp1,
 456   floatdp2,
 457   floatdp3,
 458   floatimm,
 459   floatsel,
 460   ldst_immpost,
 461   ldst_immpre,
 462   ldst_imm9,    /* immpost or immpre */
 463   ldst_pos,
 464   ldst_regoff,
 465   ldst_unpriv,
 466   ldst_unscaled,
 467   ldstexcl,
 468   ldstnapair_offs,
 469   ldstpair_off,
 470   ldstpair_indexed,
 471   loadlit,
 472   log_imm,
 473   log_shift,
 474   lse_atomic,
 475   movewide,
 476   pcreladdr,
 477   ic_system,
 478   testbranch,
 479 };
 480
 481 /* Opcode enumerators.  */
 482
 483 enum aarch64_op
 484 {
 485   OP_NIL,
 486   OP_STRB_POS,
 487   OP_LDRB_POS,
 488   OP_LDRSB_POS,
 489   OP_STRH_POS,
 490   OP_LDRH_POS,
 491   OP_LDRSH_POS,
 492   OP_STR_POS,
 493   OP_LDR_POS,
 494   OP_STRF_POS,
 495   OP_LDRF_POS,
 496   OP_LDRSW_POS,
 497   OP_PRFM_POS,
 498
 499   OP_STURB,
 500   OP_LDURB,
 501   OP_LDURSB,
 502   OP_STURH,
 503   OP_LDURH,
 504   OP_LDURSH,
 505   OP_STUR,
 506   OP_LDUR,
 507   OP_STURV,
 508   OP_LDURV,
 509   OP_LDURSW,
 510   OP_PRFUM,
 511
 512   OP_LDR_LIT,
 513   OP_LDRV_LIT,
 514   OP_LDRSW_LIT,
 515   OP_PRFM_LIT,
 516
 517   OP_ADD,
 518   OP_B,
 519   OP_BL,
 520
 521   OP_MOVN,
 522   OP_MOVZ,
 523   OP_MOVK,
 524
 525   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 526   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 527   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 528
 529   OP_MOV_V,             /* MOV alias for moving vector register.  */
 530
 531   OP_ASR_IMM,
 532   OP_LSR_IMM,
 533   OP_LSL_IMM,
 534
 535   OP_BIC,
 536
 537   OP_UBFX,
 538   OP_BFXIL,
 539   OP_SBFX,
 540   OP_SBFIZ,
 541   OP_BFI,
 542   OP_BFC,               /* ARMv8.2.  */
 543   OP_UBFIZ,
 544   OP_UXTB,
 545   OP_UXTH,
 546   OP_UXTW,
 547
 548   OP_CINC,
 549   OP_CINV,
 550   OP_CNEG,
 551   OP_CSET,
 552   OP_CSETM,
 553
 554   OP_FCVT,
 555   OP_FCVTN,
 556   OP_FCVTN2,
 557   OP_FCVTL,
 558   OP_FCVTL2,
 559   OP_FCVTXN_S,          /* Scalar version.  */
 560
 561   OP_ROR_IMM,
 562
 563   OP_SXTL,
 564   OP_SXTL2,
 565   OP_UXTL,
 566   OP_UXTL2,
 567
 568   OP_TOTAL_NUM,         /* Pseudo.  */
 569 };
 570
 571 /* Maximum number of operands an instruction can have.  */
 572 #define AARCH64_MAX_OPND_NUM 6
 573 /* Maximum number of qualifier sequences an instruction can have.  */
 574 #define AARCH64_MAX_QLF_SEQ_NUM 10
 575 /* Operand qualifier typedef; optimized for the size.  */
 576 typedef unsigned char aarch64_opnd_qualifier_t;
 577 /* Operand qualifier sequence typedef.  */
 578 typedef aarch64_opnd_qualifier_t        \
 579           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 580
 581 /* FIXME: improve the efficiency.  */
 582 static inline bfd_boolean
 583 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 584 {
 585   int i;
 586   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 587     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 588       return FALSE;
 589   return TRUE;
 590 }
 591
 592 /* This structure holds information for a particular opcode.  */
 593
 594 struct aarch64_opcode
 595 {
 596   /* The name of the mnemonic.  */
 597   const char *name;
 598
 599   /* The opcode itself.  Those bits which will be filled in with
 600      operands are zeroes.  */
 601   aarch64_insn opcode;
 602
 603   /* The opcode mask.  This is used by the disassembler.  This is a
 604      mask containing ones indicating those bits which must match the
 605      opcode field, and zeroes indicating those bits which need not
 606      match (and are presumably filled in by operands).  */
 607   aarch64_insn mask;
 608
 609   /* Instruction class.  */
 610   enum aarch64_insn_class iclass;
 611
 612   /* Enumerator identifier.  */
 613   enum aarch64_op op;
 614
 615   /* Which architecture variant provides this instruction.  */
 616   const aarch64_feature_set *avariant;
 617
 618   /* An array of operand codes.  Each code is an index into the
 619      operand table.  They appear in the order which the operands must
 620      appear in assembly code, and are terminated by a zero.  */
 621   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 622
 623   /* A list of operand qualifier code sequence.  Each operand qualifier
 624      code qualifies the corresponding operand code.  Each operand
 625      qualifier sequence specifies a valid opcode variant and related
 626      constraint on operands.  */
 627   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 628
 629   /* Flags providing information about this instruction */
 630   uint32_t flags;
 631
 632   /* If nonzero, this operand and operand 0 are both registers and
 633      are required to have the same register number.  */
 634   unsigned char tied_operand;
 635
 636   /* If non-NULL, a function to verify that a given instruction is valid.  */
 637   bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
 638 };
 639
 640 typedef struct aarch64_opcode aarch64_opcode;
 641
 642 /* Table describing all the AArch64 opcodes.  */
 643 extern aarch64_opcode aarch64_opcode_table[];
 644
 645 /* Opcode flags.  */
 646 #define F_ALIAS (1 << 0)
 647 #define F_HAS_ALIAS (1 << 1)
 648 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 649    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 650 #define F_P1 (1 << 2)
 651 #define F_P2 (2 << 2)
 652 #define F_P3 (3 << 2)
 653 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 654 #define F_COND (1 << 4)
 655 /* Instruction has the field of 'sf'.  */
 656 #define F_SF (1 << 5)
 657 /* Instruction has the field of 'size:Q'.  */
 658 #define F_SIZEQ (1 << 6)
 659 /* Floating-point instruction has the field of 'type'.  */
 660 #define F_FPTYPE (1 << 7)
 661 /* AdvSIMD scalar instruction has the field of 'size'.  */
 662 #define F_SSIZE (1 << 8)
 663 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 664 #define F_T (1 << 9)
 665 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 666 #define F_GPRSIZE_IN_Q (1 << 10)
 667 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 668 #define F_LDS_SIZE (1 << 11)
 669 /* Optional operand; assume maximum of 1 operand can be optional.  */
 670 #define F_OPD0_OPT (1 << 12)
 671 #define F_OPD1_OPT (2 << 12)
 672 #define F_OPD2_OPT (3 << 12)
 673 #define F_OPD3_OPT (4 << 12)
 674 #define F_OPD4_OPT (5 << 12)
 675 /* Default value for the optional operand when omitted from the assembly.  */
 676 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 677 /* Instruction that is an alias of another instruction needs to be
 678    encoded/decoded by converting it to/from the real form, followed by
 679    the encoding/decoding according to the rules of the real opcode.
 680    This compares to the direct coding using the alias's information.
 681    N.B. this flag requires F_ALIAS to be used together.  */
 682 #define F_CONV (1 << 20)
 683 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 684    friendly pseudo instruction available only in the assembly code (thus will
 685    not show up in the disassembly).  */
 686 #define F_PSEUDO (1 << 21)
 687 /* Instruction has miscellaneous encoding/decoding rules.  */
 688 #define F_MISC (1 << 22)
 689 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 690 #define F_N (1 << 23)
 691 /* Opcode dependent field.  */
 692 #define F_OD(X) (((X) & 0x7) << 24)
 693 /* Instruction has the field of 'sz'.  */
 694 #define F_LSE_SZ (1 << 27)
 695 /* Require an exact qualifier match, even for NIL qualifiers.  */
 696 #define F_STRICT (1ULL << 28)
 697 /* Next bit is 29.  */
 698
 699 static inline bfd_boolean
 700 alias_opcode_p (const aarch64_opcode *opcode)
 701 {
 702   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 703 }
 704
 705 static inline bfd_boolean
 706 opcode_has_alias (const aarch64_opcode *opcode)
 707 {
 708   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 709 }
 710
 711 /* Priority for disassembling preference.  */
 712 static inline int
 713 opcode_priority (const aarch64_opcode *opcode)
 714 {
 715   return (opcode->flags >> 2) & 0x3;
 716 }
 717
 718 static inline bfd_boolean
 719 pseudo_opcode_p (const aarch64_opcode *opcode)
 720 {
 721   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 722 }
 723
 724 static inline bfd_boolean
 725 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 726 {
 727   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 728     ? TRUE : FALSE;
 729 }
 730
 731 static inline aarch64_insn
 732 get_optional_operand_default_value (const aarch64_opcode *opcode)
 733 {
 734   return (opcode->flags >> 15) & 0x1f;
 735 }
 736
 737 static inline unsigned int
 738 get_opcode_dependent_value (const aarch64_opcode *opcode)
 739 {
 740   return (opcode->flags >> 24) & 0x7;
 741 }
 742
 743 static inline bfd_boolean
 744 opcode_has_special_coder (const aarch64_opcode *opcode)
 745 {
 746   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 747           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 748     : FALSE;
 749 }
 750 \f
 751 struct aarch64_name_value_pair
 752 {
 753   const char *  name;
 754   aarch64_insn  value;
 755 };
 756
 757 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 758 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 759 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 760 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 761
 762 typedef struct
 763 {
 764   const char *  name;
 765   aarch64_insn  value;
 766   uint32_t      flags;
 767 } aarch64_sys_reg;
 768
 769 extern const aarch64_sys_reg aarch64_sys_regs [];
 770 extern const aarch64_sys_reg aarch64_pstatefields [];
 771 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 772 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 773                                                 const aarch64_sys_reg *);
 774 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 775                                                     const aarch64_sys_reg *);
 776
 777 typedef struct
 778 {
 779   const char *name;
 780   uint32_t value;
 781   uint32_t flags ;
 782 } aarch64_sys_ins_reg;
 783
 784 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 785 extern bfd_boolean
 786 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 787                                  const aarch64_sys_ins_reg *);
 788
 789 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 790 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 791 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 792 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 793
 794 /* Shift/extending operator kinds.
 795    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 796 enum aarch64_modifier_kind
 797 {
 798   AARCH64_MOD_NONE,
 799   AARCH64_MOD_MSL,
 800   AARCH64_MOD_ROR,
 801   AARCH64_MOD_ASR,
 802   AARCH64_MOD_LSR,
 803   AARCH64_MOD_LSL,
 804   AARCH64_MOD_UXTB,
 805   AARCH64_MOD_UXTH,
 806   AARCH64_MOD_UXTW,
 807   AARCH64_MOD_UXTX,
 808   AARCH64_MOD_SXTB,
 809   AARCH64_MOD_SXTH,
 810   AARCH64_MOD_SXTW,
 811   AARCH64_MOD_SXTX,
 812   AARCH64_MOD_MUL,
 813   AARCH64_MOD_MUL_VL,
 814 };
 815
 816 bfd_boolean
 817 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 818
 819 enum aarch64_modifier_kind
 820 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 821 /* Condition.  */
 822
 823 typedef struct
 824 {
 825   /* A list of names with the first one as the disassembly preference;
 826      terminated by NULL if fewer than 3.  */
 827   const char *names[3];
 828   aarch64_insn value;
 829 } aarch64_cond;
 830
 831 extern const aarch64_cond aarch64_conds[16];
 832
 833 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 834 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 835 \f
 836 /* Structure representing an operand.  */
 837
 838 struct aarch64_opnd_info
 839 {
 840   enum aarch64_opnd type;
 841   aarch64_opnd_qualifier_t qualifier;
 842   int idx;
 843
 844   union
 845     {
 846       struct
 847         {
 848           unsigned regno;
 849         } reg;
 850       struct
 851         {
 852           unsigned int regno;
 853           int64_t index;
 854         } reglane;
 855       /* e.g. LVn.  */
 856       struct
 857         {
 858           unsigned first_regno : 5;
 859           unsigned num_regs : 3;
 860           /* 1 if it is a list of reg element.  */
 861           unsigned has_index : 1;
 862           /* Lane index; valid only when has_index is 1.  */
 863           int64_t index;
 864         } reglist;
 865       /* e.g. immediate or pc relative address offset.  */
 866       struct
 867         {
 868           int64_t value;
 869           unsigned is_fp : 1;
 870         } imm;
 871       /* e.g. address in STR (register offset).  */
 872       struct
 873         {
 874           unsigned base_regno;
 875           struct
 876             {
 877               union
 878                 {
 879                   int imm;
 880                   unsigned regno;
 881                 };
 882               unsigned is_reg;
 883             } offset;
 884           unsigned pcrel : 1;           /* PC-relative.  */
 885           unsigned writeback : 1;
 886           unsigned preind : 1;          /* Pre-indexed.  */
 887           unsigned postind : 1;         /* Post-indexed.  */
 888         } addr;
 889       const aarch64_cond *cond;
 890       /* The encoding of the system register.  */
 891       aarch64_insn sysreg;
 892       /* The encoding of the PSTATE field.  */
 893       aarch64_insn pstatefield;
 894       const aarch64_sys_ins_reg *sysins_op;
 895       const struct aarch64_name_value_pair *barrier;
 896       const struct aarch64_name_value_pair *hint_option;
 897       const struct aarch64_name_value_pair *prfop;
 898     };
 899
 900   /* Operand shifter; in use when the operand is a register offset address,
 901      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
 902   struct
 903     {
 904       enum aarch64_modifier_kind kind;
 905       unsigned operator_present: 1;     /* Only valid during encoding.  */
 906       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
 907       unsigned amount_present: 1;
 908       int64_t amount;
 909     } shifter;
 910
 911   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
 912                            to be done on it.  In some (but not all) of these
 913                            cases, we need to tell libopcodes to skip the
 914                            constraint checking and the encoding for this
 915                            operand, so that the libopcodes can pick up the
 916                            right opcode before the operand is fixed-up.  This
 917                            flag should only be used during the
 918                            assembling/encoding.  */
 919   unsigned present:1;   /* Whether this operand is present in the assembly
 920                            line; not used during the disassembly.  */
 921 };
 922
 923 typedef struct aarch64_opnd_info aarch64_opnd_info;
 924
 925 /* Structure representing an instruction.
 926
 927    It is used during both the assembling and disassembling.  The assembler
 928    fills an aarch64_inst after a successful parsing and then passes it to the
 929    encoding routine to do the encoding.  During the disassembling, the
 930    disassembler calls the decoding routine to decode a binary instruction; on a
 931    successful return, such a structure will be filled with information of the
 932    instruction; then the disassembler uses the information to print out the
 933    instruction.  */
 934
 935 struct aarch64_inst
 936 {
 937   /* The value of the binary instruction.  */
 938   aarch64_insn value;
 939
 940   /* Corresponding opcode entry.  */
 941   const aarch64_opcode *opcode;
 942
 943   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
 944   const aarch64_cond *cond;
 945
 946   /* Operands information.  */
 947   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
 948 };
 949
 950 typedef struct aarch64_inst aarch64_inst;
 951 \f
 952 /* Diagnosis related declaration and interface.  */
 953
 954 /* Operand error kind enumerators.
 955
 956    AARCH64_OPDE_RECOVERABLE
 957      Less severe error found during the parsing, very possibly because that
 958      GAS has picked up a wrong instruction template for the parsing.
 959
 960    AARCH64_OPDE_SYNTAX_ERROR
 961      General syntax error; it can be either a user error, or simply because
 962      that GAS is trying a wrong instruction template.
 963
 964    AARCH64_OPDE_FATAL_SYNTAX_ERROR
 965      Definitely a user syntax error.
 966
 967    AARCH64_OPDE_INVALID_VARIANT
 968      No syntax error, but the operands are not a valid combination, e.g.
 969      FMOV D0,S0
 970
 971    AARCH64_OPDE_UNTIED_OPERAND
 972      The asm failed to use the same register for a destination operand
 973      and a tied source operand.
 974
 975    AARCH64_OPDE_OUT_OF_RANGE
 976      Error about some immediate value out of a valid range.
 977
 978    AARCH64_OPDE_UNALIGNED
 979      Error about some immediate value not properly aligned (i.e. not being a
 980      multiple times of a certain value).
 981
 982    AARCH64_OPDE_REG_LIST
 983      Error about the register list operand having unexpected number of
 984      registers.
 985
 986    AARCH64_OPDE_OTHER_ERROR
 987      Error of the highest severity and used for any severe issue that does not
 988      fall into any of the above categories.
 989
 990    The enumerators are only interesting to GAS.  They are declared here (in
 991    libopcodes) because that some errors are detected (and then notified to GAS)
 992    by libopcodes (rather than by GAS solely).
 993
 994    The first three errors are only deteced by GAS while the
 995    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
 996    only libopcodes has the information about the valid variants of each
 997    instruction.
 998
 999    The enumerators have an increasing severity.  This is helpful when there are
1000    multiple instruction templates available for a given mnemonic name (e.g.
1001    FMOV); this mechanism will help choose the most suitable template from which
1002    the generated diagnostics can most closely describe the issues, if any.  */
1003
1004 enum aarch64_operand_error_kind
1005 {
1006   AARCH64_OPDE_NIL,
1007   AARCH64_OPDE_RECOVERABLE,
1008   AARCH64_OPDE_SYNTAX_ERROR,
1009   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1010   AARCH64_OPDE_INVALID_VARIANT,
1011   AARCH64_OPDE_UNTIED_OPERAND,
1012   AARCH64_OPDE_OUT_OF_RANGE,
1013   AARCH64_OPDE_UNALIGNED,
1014   AARCH64_OPDE_REG_LIST,
1015   AARCH64_OPDE_OTHER_ERROR
1016 };
1017
1018 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1019 struct aarch64_operand_error
1020 {
1021   enum aarch64_operand_error_kind kind;
1022   int index;
1023   const char *error;
1024   int data[3];  /* Some data for extra information.  */
1025 };
1026
1027 typedef struct aarch64_operand_error aarch64_operand_error;
1028
1029 /* Encoding entrypoint.  */
1030
1031 extern int
1032 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1033                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1034                        aarch64_operand_error *);
1035
1036 extern const aarch64_opcode *
1037 aarch64_replace_opcode (struct aarch64_inst *,
1038                         const aarch64_opcode *);
1039
1040 /* Given the opcode enumerator OP, return the pointer to the corresponding
1041    opcode entry.  */
1042
1043 extern const aarch64_opcode *
1044 aarch64_get_opcode (enum aarch64_op);
1045
1046 /* Generate the string representation of an operand.  */
1047 extern void
1048 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1049                        const aarch64_opnd_info *, int, int *, bfd_vma *);
1050
1051 /* Miscellaneous interface.  */
1052
1053 extern int
1054 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1055
1056 extern aarch64_opnd_qualifier_t
1057 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1058                                 const aarch64_opnd_qualifier_t, int);
1059
1060 extern int
1061 aarch64_num_of_operands (const aarch64_opcode *);
1062
1063 extern int
1064 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1065
1066 extern int
1067 aarch64_zero_register_p (const aarch64_opnd_info *);
1068
1069 extern int
1070 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
1071
1072 /* Given an operand qualifier, return the expected data element size
1073    of a qualified operand.  */
1074 extern unsigned char
1075 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1076
1077 extern enum aarch64_operand_class
1078 aarch64_get_operand_class (enum aarch64_opnd);
1079
1080 extern const char *
1081 aarch64_get_operand_name (enum aarch64_opnd);
1082
1083 extern const char *
1084 aarch64_get_operand_desc (enum aarch64_opnd);
1085
1086 extern bfd_boolean
1087 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1088
1089 #ifdef DEBUG_AARCH64
1090 extern int debug_dump;
1091
1092 extern void
1093 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1094
1095 #define DEBUG_TRACE(M, ...)                                     \
1096   {                                                             \
1097     if (debug_dump)                                             \
1098       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1099   }
1100
1101 #define DEBUG_TRACE_IF(C, M, ...)                               \
1102   {                                                             \
1103     if (debug_dump && (C))                                      \
1104       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1105   }
1106 #else  /* !DEBUG_AARCH64 */
1107 #define DEBUG_TRACE(M, ...) ;
1108 #define DEBUG_TRACE_IF(C, M, ...) ;
1109 #endif /* DEBUG_AARCH64 */
1110
1111 extern const char *const aarch64_sve_pattern_array[32];
1112 extern const char *const aarch64_sve_prfop_array[16];
1113
1114 #ifdef __cplusplus
1115 }
1116 #endif
1117
1118 #endif /* OPCODE_AARCH64_H */