include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2019 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81 /* SCXTNUM_ELx.  */
  82 #define AARCH64_FEATURE_SCXTNUM         0x200000000000ULL
  83 /* ID_PFR2 instructions.  */
  84 #define AARCH64_FEATURE_ID_PFR2         0x400000000000ULL
  85 /* SSBS mechanism enabled.  */
  86 #define AARCH64_FEATURE_SSBS            0x800000000000ULL
  87 /* Memory Tagging Extension.  */
  88 #define AARCH64_FEATURE_MEMTAG          0x1000000000000ULL
  89 /* Transactional Memory Extension.  */
  90 #define AARCH64_FEATURE_TME             0x2000000000000ULL
  91
  92 /* SVE2 instructions.  */
  93 #define AARCH64_FEATURE_SVE2            0x000000010
  94 #define AARCH64_FEATURE_SVE2_AES                0x000000080
  95 #define AARCH64_FEATURE_SVE2_BITPERM    0x000000100
  96 #define AARCH64_FEATURE_SVE2_SM4                0x000000200
  97 #define AARCH64_FEATURE_SVE2_SHA3       0x000000400
  98
  99 /* Architectures are the sum of the base and extensions.  */
 100 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
 101                                                  AARCH64_FEATURE_FP  \
 102                                                  | AARCH64_FEATURE_SIMD)
 103 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
 104                                                  AARCH64_FEATURE_CRC    \
 105                                                  | AARCH64_FEATURE_V8_1 \
 106                                                  | AARCH64_FEATURE_LSE  \
 107                                                  | AARCH64_FEATURE_PAN  \
 108                                                  | AARCH64_FEATURE_LOR  \
 109                                                  | AARCH64_FEATURE_RDMA)
 110 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
 111                                                  AARCH64_FEATURE_V8_2   \
 112                                                  | AARCH64_FEATURE_RAS)
 113 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
 114                                                  AARCH64_FEATURE_V8_3   \
 115                                                  | AARCH64_FEATURE_RCPC \
 116                                                  | AARCH64_FEATURE_COMPNUM)
 117 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 118                                                  AARCH64_FEATURE_V8_4   \
 119                                                  | AARCH64_FEATURE_DOTPROD \
 120                                                  | AARCH64_FEATURE_F16_FML)
 121 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 122                                                  AARCH64_FEATURE_V8_5   \
 123                                                  | AARCH64_FEATURE_FLAGMANIP \
 124                                                  | AARCH64_FEATURE_FRINTTS \
 125                                                  | AARCH64_FEATURE_SB   \
 126                                                  | AARCH64_FEATURE_PREDRES \
 127                                                  | AARCH64_FEATURE_CVADP \
 128                                                  | AARCH64_FEATURE_BTI  \
 129                                                  | AARCH64_FEATURE_SCXTNUM \
 130                                                  | AARCH64_FEATURE_ID_PFR2 \
 131                                                  | AARCH64_FEATURE_SSBS)
 132
 133
 134 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 135 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 136
 137 /* CPU-specific features.  */
 138 typedef unsigned long long aarch64_feature_set;
 139
 140 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 141   ((~(CPU) & (FEAT)) == 0)
 142
 143 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 144   (((CPU) & (FEAT)) != 0)
 145
 146 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 147   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 148
 149 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 150   do                                            \
 151     {                                           \
 152       (TARG) = (F1) | (F2);                     \
 153     }                                           \
 154   while (0)
 155
 156 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 157   do                                            \
 158     {                                           \
 159       (TARG) = (F1) &~ (F2);                    \
 160     }                                           \
 161   while (0)
 162
 163 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 164
 165 enum aarch64_operand_class
 166 {
 167   AARCH64_OPND_CLASS_NIL,
 168   AARCH64_OPND_CLASS_INT_REG,
 169   AARCH64_OPND_CLASS_MODIFIED_REG,
 170   AARCH64_OPND_CLASS_FP_REG,
 171   AARCH64_OPND_CLASS_SIMD_REG,
 172   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 173   AARCH64_OPND_CLASS_SISD_REG,
 174   AARCH64_OPND_CLASS_SIMD_REGLIST,
 175   AARCH64_OPND_CLASS_SVE_REG,
 176   AARCH64_OPND_CLASS_PRED_REG,
 177   AARCH64_OPND_CLASS_ADDRESS,
 178   AARCH64_OPND_CLASS_IMMEDIATE,
 179   AARCH64_OPND_CLASS_SYSTEM,
 180   AARCH64_OPND_CLASS_COND,
 181 };
 182
 183 /* Operand code that helps both parsing and coding.
 184    Keep AARCH64_OPERANDS synced.  */
 185
 186 enum aarch64_opnd
 187 {
 188   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 189
 190   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 191   AARCH64_OPND_Rn,      /* Integer register as source.  */
 192   AARCH64_OPND_Rm,      /* Integer register as source.  */
 193   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 194   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 195   AARCH64_OPND_Rt_SP,   /* Integer Rt or SP used in STG instructions.  */
 196   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 197   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 198   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 199
 200   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 201   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 202   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 203   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 204   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 205   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 206
 207   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 208   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 209   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 210   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 211   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 212   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 213
 214   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 215   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 216   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 217
 218   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 219   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 220   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 221   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 222   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 223   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 224   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 225   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 226   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 227   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 228                            qualifier is S_H.  */
 229   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 230   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 231   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 232                            structure to all lanes.  */
 233   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 234
 235   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 236   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 237
 238   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 239   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 240   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 241   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 242   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 243   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 244   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 245   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 246                            (no encoding).  */
 247   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 248   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 249   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 250   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 251   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 252   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 253   AARCH64_OPND_IMM,     /* Immediate.  */
 254   AARCH64_OPND_IMM_2,   /* Immediate.  */
 255   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 256   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 257   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 258   AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg.  */
 259   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 260   AARCH64_OPND_UIMM10,  /* Unsigned 10-bit immediate in addg/subg.  */
 261   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 262   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 263   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 264   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 265   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 266                            each condition flag.  */
 267
 268   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 269   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 270   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 271   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 272   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 273   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 274   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 275   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 276
 277   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 278   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 279
 280   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 281   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 282   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 283   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 284   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 285
 286   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 287   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 288   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 289   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 290   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 291                                    negative or unaligned and there is
 292                                    no writeback allowed.  This operand code
 293                                    is only used to support the programmer-
 294                                    friendly feature of using LDR/STR as the
 295                                    the mnemonic name for LDUR/STUR instructions
 296                                    wherever there is no ambiguity.  */
 297   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 298   AARCH64_OPND_ADDR_SIMM11,     /* Address with a signed 11-bit (multiple of
 299                                    16) immediate.  */
 300   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 301   AARCH64_OPND_ADDR_SIMM13,     /* Address with a signed 13-bit (multiple of
 302                                    16) immediate.  */
 303   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 304   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 305   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 306
 307   AARCH64_OPND_SYSREG,          /* System register operand.  */
 308   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 309   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 310   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 311   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 312   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 313   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 314   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 315   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 316   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 317   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 318   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 319
 320   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 321   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 322   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 323   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 324   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 325   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 326   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 327   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 328   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 329   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 330   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 331   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 332   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 333   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 334   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 335   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 336   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 337   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 338   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 339   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 340   AARCH64_OPND_SVE_ADDR_ZX,         /* SVE [Zn.<T>{, <Xm>}].  */
 341   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 342   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 343   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 344   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 345   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 346                                        Bit 14 controls S/U choice.  */
 347   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 348                                        Bit 22 controls S/U choice.  */
 349   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 350                                        Bit 14 controls S/U choice.  */
 351   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 352                                        Bit 22 controls S/U choice.  */
 353   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 354                                        Bit 14 controls S/U choice.  */
 355   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 356                                        Bit 22 controls S/U choice.  */
 357   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 358                                        Bit 14 controls S/U choice.  */
 359   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 360                                        Bit 22 controls S/U choice.  */
 361   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 362   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 363   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 364   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 365   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 366   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 367   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 368   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 369   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 370   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 371   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 372   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 373   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 374   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 375   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 376   AARCH64_OPND_SVE_IMM_ROT3,    /* SVE cadd 1-bit rotate (90 or 270).  */
 377   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 378   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 379   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 380   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 381   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 382   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 383   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 384   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 385   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 386   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 387   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 388   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 389   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 390   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 391   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 392   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 393   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 394   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 395   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 396   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 397   AARCH64_OPND_SVE_SHRIMM_UNPRED_22,    /* SVE 3 bit shift right unpred.  */
 398   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 399   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 400   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 401   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 402   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 403   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 404   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 405   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 406   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 407   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 408   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 409   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 410   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 411   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 412   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 413   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 414   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 415   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 416   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 417   AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11.  */
 418   AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11.  */
 419   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 420   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 421   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 422   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 423   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 424   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 425   AARCH64_OPND_TME_UIMM16,      /* TME unsigned 16-bit immediate.  */
 426   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 427 };
 428
 429 /* Qualifier constrains an operand.  It either specifies a variant of an
 430    operand type or limits values available to an operand type.
 431
 432    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 433
 434 enum aarch64_opnd_qualifier
 435 {
 436   /* Indicating no further qualification on an operand.  */
 437   AARCH64_OPND_QLF_NIL,
 438
 439   /* Qualifying an operand which is a general purpose (integer) register;
 440      indicating the operand data size or a specific register.  */
 441   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 442   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 443   AARCH64_OPND_QLF_WSP, /* WSP.  */
 444   AARCH64_OPND_QLF_SP,  /* SP.  */
 445
 446   /* Qualifying an operand which is a floating-point register, a SIMD
 447      vector element or a SIMD vector element list; indicating operand data
 448      size or the size of each SIMD vector element in the case of a SIMD
 449      vector element list.
 450      These qualifiers are also used to qualify an address operand to
 451      indicate the size of data element a load/store instruction is
 452      accessing.
 453      They are also used for the immediate shift operand in e.g. SSHR.  Such
 454      a use is only for the ease of operand encoding/decoding and qualifier
 455      sequence matching; such a use should not be applied widely; use the value
 456      constraint qualifiers for immediate operands wherever possible.  */
 457   AARCH64_OPND_QLF_S_B,
 458   AARCH64_OPND_QLF_S_H,
 459   AARCH64_OPND_QLF_S_S,
 460   AARCH64_OPND_QLF_S_D,
 461   AARCH64_OPND_QLF_S_Q,
 462   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 463      are selected by the instruction.  Other than that it has no difference
 464      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 465      reasons and is an exception from normal AArch64 disassembly scheme.  */
 466   AARCH64_OPND_QLF_S_4B,
 467
 468   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 469      register list; indicating register shape.
 470      They are also used for the immediate shift operand in e.g. SSHR.  Such
 471      a use is only for the ease of operand encoding/decoding and qualifier
 472      sequence matching; such a use should not be applied widely; use the value
 473      constraint qualifiers for immediate operands wherever possible.  */
 474   AARCH64_OPND_QLF_V_4B,
 475   AARCH64_OPND_QLF_V_8B,
 476   AARCH64_OPND_QLF_V_16B,
 477   AARCH64_OPND_QLF_V_2H,
 478   AARCH64_OPND_QLF_V_4H,
 479   AARCH64_OPND_QLF_V_8H,
 480   AARCH64_OPND_QLF_V_2S,
 481   AARCH64_OPND_QLF_V_4S,
 482   AARCH64_OPND_QLF_V_1D,
 483   AARCH64_OPND_QLF_V_2D,
 484   AARCH64_OPND_QLF_V_1Q,
 485
 486   AARCH64_OPND_QLF_P_Z,
 487   AARCH64_OPND_QLF_P_M,
 488
 489   /* Used in scaled signed immediate that are scaled by a Tag granule
 490      like in stg, st2g, etc.   */
 491   AARCH64_OPND_QLF_imm_tag,
 492
 493   /* Constraint on value.  */
 494   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 495   AARCH64_OPND_QLF_imm_0_7,
 496   AARCH64_OPND_QLF_imm_0_15,
 497   AARCH64_OPND_QLF_imm_0_31,
 498   AARCH64_OPND_QLF_imm_0_63,
 499   AARCH64_OPND_QLF_imm_1_32,
 500   AARCH64_OPND_QLF_imm_1_64,
 501
 502   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 503      or shift-ones.  */
 504   AARCH64_OPND_QLF_LSL,
 505   AARCH64_OPND_QLF_MSL,
 506
 507   /* Special qualifier helping retrieve qualifier information during the
 508      decoding time (currently not in use).  */
 509   AARCH64_OPND_QLF_RETRIEVE,
 510 };
 511 \f
 512 /* Instruction class.  */
 513
 514 enum aarch64_insn_class
 515 {
 516   addsub_carry,
 517   addsub_ext,
 518   addsub_imm,
 519   addsub_shift,
 520   asimdall,
 521   asimddiff,
 522   asimdelem,
 523   asimdext,
 524   asimdimm,
 525   asimdins,
 526   asimdmisc,
 527   asimdperm,
 528   asimdsame,
 529   asimdshf,
 530   asimdtbl,
 531   asisddiff,
 532   asisdelem,
 533   asisdlse,
 534   asisdlsep,
 535   asisdlso,
 536   asisdlsop,
 537   asisdmisc,
 538   asisdone,
 539   asisdpair,
 540   asisdsame,
 541   asisdshf,
 542   bitfield,
 543   branch_imm,
 544   branch_reg,
 545   compbranch,
 546   condbranch,
 547   condcmp_imm,
 548   condcmp_reg,
 549   condsel,
 550   cryptoaes,
 551   cryptosha2,
 552   cryptosha3,
 553   dp_1src,
 554   dp_2src,
 555   dp_3src,
 556   exception,
 557   extract,
 558   float2fix,
 559   float2int,
 560   floatccmp,
 561   floatcmp,
 562   floatdp1,
 563   floatdp2,
 564   floatdp3,
 565   floatimm,
 566   floatsel,
 567   ldst_immpost,
 568   ldst_immpre,
 569   ldst_imm9,    /* immpost or immpre */
 570   ldst_imm10,   /* LDRAA/LDRAB */
 571   ldst_pos,
 572   ldst_regoff,
 573   ldst_unpriv,
 574   ldst_unscaled,
 575   ldstexcl,
 576   ldstnapair_offs,
 577   ldstpair_off,
 578   ldstpair_indexed,
 579   loadlit,
 580   log_imm,
 581   log_shift,
 582   lse_atomic,
 583   movewide,
 584   pcreladdr,
 585   ic_system,
 586   sve_cpy,
 587   sve_index,
 588   sve_limm,
 589   sve_misc,
 590   sve_movprfx,
 591   sve_pred_zm,
 592   sve_shift_pred,
 593   sve_shift_unpred,
 594   sve_size_bhs,
 595   sve_size_bhsd,
 596   sve_size_hsd,
 597   sve_size_hsd2,
 598   sve_size_sd,
 599   sve_size_bh,
 600   sve_size_sd2,
 601   sve_size_013,
 602   sve_shift_tsz_hsd,
 603   sve_shift_tsz_bhsd,
 604   sve_size_tsz_bhs,
 605   testbranch,
 606   cryptosm3,
 607   cryptosm4,
 608   dotproduct,
 609 };
 610
 611 /* Opcode enumerators.  */
 612
 613 enum aarch64_op
 614 {
 615   OP_NIL,
 616   OP_STRB_POS,
 617   OP_LDRB_POS,
 618   OP_LDRSB_POS,
 619   OP_STRH_POS,
 620   OP_LDRH_POS,
 621   OP_LDRSH_POS,
 622   OP_STR_POS,
 623   OP_LDR_POS,
 624   OP_STRF_POS,
 625   OP_LDRF_POS,
 626   OP_LDRSW_POS,
 627   OP_PRFM_POS,
 628
 629   OP_STURB,
 630   OP_LDURB,
 631   OP_LDURSB,
 632   OP_STURH,
 633   OP_LDURH,
 634   OP_LDURSH,
 635   OP_STUR,
 636   OP_LDUR,
 637   OP_STURV,
 638   OP_LDURV,
 639   OP_LDURSW,
 640   OP_PRFUM,
 641
 642   OP_LDR_LIT,
 643   OP_LDRV_LIT,
 644   OP_LDRSW_LIT,
 645   OP_PRFM_LIT,
 646
 647   OP_ADD,
 648   OP_B,
 649   OP_BL,
 650
 651   OP_MOVN,
 652   OP_MOVZ,
 653   OP_MOVK,
 654
 655   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 656   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 657   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 658
 659   OP_MOV_V,             /* MOV alias for moving vector register.  */
 660
 661   OP_ASR_IMM,
 662   OP_LSR_IMM,
 663   OP_LSL_IMM,
 664
 665   OP_BIC,
 666
 667   OP_UBFX,
 668   OP_BFXIL,
 669   OP_SBFX,
 670   OP_SBFIZ,
 671   OP_BFI,
 672   OP_BFC,               /* ARMv8.2.  */
 673   OP_UBFIZ,
 674   OP_UXTB,
 675   OP_UXTH,
 676   OP_UXTW,
 677
 678   OP_CINC,
 679   OP_CINV,
 680   OP_CNEG,
 681   OP_CSET,
 682   OP_CSETM,
 683
 684   OP_FCVT,
 685   OP_FCVTN,
 686   OP_FCVTN2,
 687   OP_FCVTL,
 688   OP_FCVTL2,
 689   OP_FCVTXN_S,          /* Scalar version.  */
 690
 691   OP_ROR_IMM,
 692
 693   OP_SXTL,
 694   OP_SXTL2,
 695   OP_UXTL,
 696   OP_UXTL2,
 697
 698   OP_MOV_P_P,
 699   OP_MOV_Z_P_Z,
 700   OP_MOV_Z_V,
 701   OP_MOV_Z_Z,
 702   OP_MOV_Z_Zi,
 703   OP_MOVM_P_P_P,
 704   OP_MOVS_P_P,
 705   OP_MOVZS_P_P_P,
 706   OP_MOVZ_P_P_P,
 707   OP_NOTS_P_P_P_Z,
 708   OP_NOT_P_P_P_Z,
 709
 710   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 711
 712   OP_TOTAL_NUM,         /* Pseudo.  */
 713 };
 714
 715 /* Error types.  */
 716 enum err_type
 717 {
 718   ERR_OK,
 719   ERR_UND,
 720   ERR_UNP,
 721   ERR_NYI,
 722   ERR_VFI,
 723   ERR_NR_ENTRIES
 724 };
 725
 726 /* Maximum number of operands an instruction can have.  */
 727 #define AARCH64_MAX_OPND_NUM 6
 728 /* Maximum number of qualifier sequences an instruction can have.  */
 729 #define AARCH64_MAX_QLF_SEQ_NUM 10
 730 /* Operand qualifier typedef; optimized for the size.  */
 731 typedef unsigned char aarch64_opnd_qualifier_t;
 732 /* Operand qualifier sequence typedef.  */
 733 typedef aarch64_opnd_qualifier_t        \
 734           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 735
 736 /* FIXME: improve the efficiency.  */
 737 static inline bfd_boolean
 738 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 739 {
 740   int i;
 741   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 742     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 743       return FALSE;
 744   return TRUE;
 745 }
 746
 747 /*  Forward declare error reporting type.  */
 748 typedef struct aarch64_operand_error aarch64_operand_error;
 749 /* Forward declare instruction sequence type.  */
 750 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 751 /* Forward declare instruction definition.  */
 752 typedef struct aarch64_inst aarch64_inst;
 753
 754 /* This structure holds information for a particular opcode.  */
 755
 756 struct aarch64_opcode
 757 {
 758   /* The name of the mnemonic.  */
 759   const char *name;
 760
 761   /* The opcode itself.  Those bits which will be filled in with
 762      operands are zeroes.  */
 763   aarch64_insn opcode;
 764
 765   /* The opcode mask.  This is used by the disassembler.  This is a
 766      mask containing ones indicating those bits which must match the
 767      opcode field, and zeroes indicating those bits which need not
 768      match (and are presumably filled in by operands).  */
 769   aarch64_insn mask;
 770
 771   /* Instruction class.  */
 772   enum aarch64_insn_class iclass;
 773
 774   /* Enumerator identifier.  */
 775   enum aarch64_op op;
 776
 777   /* Which architecture variant provides this instruction.  */
 778   const aarch64_feature_set *avariant;
 779
 780   /* An array of operand codes.  Each code is an index into the
 781      operand table.  They appear in the order which the operands must
 782      appear in assembly code, and are terminated by a zero.  */
 783   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 784
 785   /* A list of operand qualifier code sequence.  Each operand qualifier
 786      code qualifies the corresponding operand code.  Each operand
 787      qualifier sequence specifies a valid opcode variant and related
 788      constraint on operands.  */
 789   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 790
 791   /* Flags providing information about this instruction */
 792   uint64_t flags;
 793
 794   /* Extra constraints on the instruction that the verifier checks.  */
 795   uint32_t constraints;
 796
 797   /* If nonzero, this operand and operand 0 are both registers and
 798      are required to have the same register number.  */
 799   unsigned char tied_operand;
 800
 801   /* If non-NULL, a function to verify that a given instruction is valid.  */
 802   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 803                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 804                               struct aarch64_instr_sequence *);
 805 };
 806
 807 typedef struct aarch64_opcode aarch64_opcode;
 808
 809 /* Table describing all the AArch64 opcodes.  */
 810 extern aarch64_opcode aarch64_opcode_table[];
 811
 812 /* Opcode flags.  */
 813 #define F_ALIAS (1 << 0)
 814 #define F_HAS_ALIAS (1 << 1)
 815 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 816    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 817 #define F_P1 (1 << 2)
 818 #define F_P2 (2 << 2)
 819 #define F_P3 (3 << 2)
 820 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 821 #define F_COND (1 << 4)
 822 /* Instruction has the field of 'sf'.  */
 823 #define F_SF (1 << 5)
 824 /* Instruction has the field of 'size:Q'.  */
 825 #define F_SIZEQ (1 << 6)
 826 /* Floating-point instruction has the field of 'type'.  */
 827 #define F_FPTYPE (1 << 7)
 828 /* AdvSIMD scalar instruction has the field of 'size'.  */
 829 #define F_SSIZE (1 << 8)
 830 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 831 #define F_T (1 << 9)
 832 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 833 #define F_GPRSIZE_IN_Q (1 << 10)
 834 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 835 #define F_LDS_SIZE (1 << 11)
 836 /* Optional operand; assume maximum of 1 operand can be optional.  */
 837 #define F_OPD0_OPT (1 << 12)
 838 #define F_OPD1_OPT (2 << 12)
 839 #define F_OPD2_OPT (3 << 12)
 840 #define F_OPD3_OPT (4 << 12)
 841 #define F_OPD4_OPT (5 << 12)
 842 /* Default value for the optional operand when omitted from the assembly.  */
 843 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 844 /* Instruction that is an alias of another instruction needs to be
 845    encoded/decoded by converting it to/from the real form, followed by
 846    the encoding/decoding according to the rules of the real opcode.
 847    This compares to the direct coding using the alias's information.
 848    N.B. this flag requires F_ALIAS to be used together.  */
 849 #define F_CONV (1 << 20)
 850 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 851    friendly pseudo instruction available only in the assembly code (thus will
 852    not show up in the disassembly).  */
 853 #define F_PSEUDO (1 << 21)
 854 /* Instruction has miscellaneous encoding/decoding rules.  */
 855 #define F_MISC (1 << 22)
 856 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 857 #define F_N (1 << 23)
 858 /* Opcode dependent field.  */
 859 #define F_OD(X) (((X) & 0x7) << 24)
 860 /* Instruction has the field of 'sz'.  */
 861 #define F_LSE_SZ (1 << 27)
 862 /* Require an exact qualifier match, even for NIL qualifiers.  */
 863 #define F_STRICT (1ULL << 28)
 864 /* This system instruction is used to read system registers.  */
 865 #define F_SYS_READ (1ULL << 29)
 866 /* This system instruction is used to write system registers.  */
 867 #define F_SYS_WRITE (1ULL << 30)
 868 /* This instruction has an extra constraint on it that imposes a requirement on
 869    subsequent instructions.  */
 870 #define F_SCAN (1ULL << 31)
 871 /* Next bit is 32.  */
 872
 873 /* Instruction constraints.  */
 874 /* This instruction has a predication constraint on the instruction at PC+4.  */
 875 #define C_SCAN_MOVPRFX (1U << 0)
 876 /* This instruction's operation width is determined by the operand with the
 877    largest element size.  */
 878 #define C_MAX_ELEM (1U << 1)
 879 /* Next bit is 2.  */
 880
 881 static inline bfd_boolean
 882 alias_opcode_p (const aarch64_opcode *opcode)
 883 {
 884   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 885 }
 886
 887 static inline bfd_boolean
 888 opcode_has_alias (const aarch64_opcode *opcode)
 889 {
 890   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 891 }
 892
 893 /* Priority for disassembling preference.  */
 894 static inline int
 895 opcode_priority (const aarch64_opcode *opcode)
 896 {
 897   return (opcode->flags >> 2) & 0x3;
 898 }
 899
 900 static inline bfd_boolean
 901 pseudo_opcode_p (const aarch64_opcode *opcode)
 902 {
 903   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 904 }
 905
 906 static inline bfd_boolean
 907 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 908 {
 909   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 910     ? TRUE : FALSE;
 911 }
 912
 913 static inline aarch64_insn
 914 get_optional_operand_default_value (const aarch64_opcode *opcode)
 915 {
 916   return (opcode->flags >> 15) & 0x1f;
 917 }
 918
 919 static inline unsigned int
 920 get_opcode_dependent_value (const aarch64_opcode *opcode)
 921 {
 922   return (opcode->flags >> 24) & 0x7;
 923 }
 924
 925 static inline bfd_boolean
 926 opcode_has_special_coder (const aarch64_opcode *opcode)
 927 {
 928   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 929           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 930     : FALSE;
 931 }
 932 \f
 933 struct aarch64_name_value_pair
 934 {
 935   const char *  name;
 936   aarch64_insn  value;
 937 };
 938
 939 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 940 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 941 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 942 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 943
 944 typedef struct
 945 {
 946   const char *  name;
 947   aarch64_insn  value;
 948   uint32_t      flags;
 949 } aarch64_sys_reg;
 950
 951 extern const aarch64_sys_reg aarch64_sys_regs [];
 952 extern const aarch64_sys_reg aarch64_pstatefields [];
 953 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 954 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 955                                                 const aarch64_sys_reg *);
 956 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 957                                                     const aarch64_sys_reg *);
 958
 959 typedef struct
 960 {
 961   const char *name;
 962   uint32_t value;
 963   uint32_t flags ;
 964 } aarch64_sys_ins_reg;
 965
 966 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 967 extern bfd_boolean
 968 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 969                                  const aarch64_sys_ins_reg *);
 970
 971 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 972 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 973 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 974 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 975 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 976
 977 /* Shift/extending operator kinds.
 978    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 979 enum aarch64_modifier_kind
 980 {
 981   AARCH64_MOD_NONE,
 982   AARCH64_MOD_MSL,
 983   AARCH64_MOD_ROR,
 984   AARCH64_MOD_ASR,
 985   AARCH64_MOD_LSR,
 986   AARCH64_MOD_LSL,
 987   AARCH64_MOD_UXTB,
 988   AARCH64_MOD_UXTH,
 989   AARCH64_MOD_UXTW,
 990   AARCH64_MOD_UXTX,
 991   AARCH64_MOD_SXTB,
 992   AARCH64_MOD_SXTH,
 993   AARCH64_MOD_SXTW,
 994   AARCH64_MOD_SXTX,
 995   AARCH64_MOD_MUL,
 996   AARCH64_MOD_MUL_VL,
 997 };
 998
 999 bfd_boolean
1000 aarch64_extend_operator_p (enum aarch64_modifier_kind);
1001
1002 enum aarch64_modifier_kind
1003 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1004 /* Condition.  */
1005
1006 typedef struct
1007 {
1008   /* A list of names with the first one as the disassembly preference;
1009      terminated by NULL if fewer than 3.  */
1010   const char *names[4];
1011   aarch64_insn value;
1012 } aarch64_cond;
1013
1014 extern const aarch64_cond aarch64_conds[16];
1015
1016 const aarch64_cond* get_cond_from_value (aarch64_insn value);
1017 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1018 \f
1019 /* Structure representing an operand.  */
1020
1021 struct aarch64_opnd_info
1022 {
1023   enum aarch64_opnd type;
1024   aarch64_opnd_qualifier_t qualifier;
1025   int idx;
1026
1027   union
1028     {
1029       struct
1030         {
1031           unsigned regno;
1032         } reg;
1033       struct
1034         {
1035           unsigned int regno;
1036           int64_t index;
1037         } reglane;
1038       /* e.g. LVn.  */
1039       struct
1040         {
1041           unsigned first_regno : 5;
1042           unsigned num_regs : 3;
1043           /* 1 if it is a list of reg element.  */
1044           unsigned has_index : 1;
1045           /* Lane index; valid only when has_index is 1.  */
1046           int64_t index;
1047         } reglist;
1048       /* e.g. immediate or pc relative address offset.  */
1049       struct
1050         {
1051           int64_t value;
1052           unsigned is_fp : 1;
1053         } imm;
1054       /* e.g. address in STR (register offset).  */
1055       struct
1056         {
1057           unsigned base_regno;
1058           struct
1059             {
1060               union
1061                 {
1062                   int imm;
1063                   unsigned regno;
1064                 };
1065               unsigned is_reg;
1066             } offset;
1067           unsigned pcrel : 1;           /* PC-relative.  */
1068           unsigned writeback : 1;
1069           unsigned preind : 1;          /* Pre-indexed.  */
1070           unsigned postind : 1;         /* Post-indexed.  */
1071         } addr;
1072
1073       struct
1074         {
1075           /* The encoding of the system register.  */
1076           aarch64_insn value;
1077
1078           /* The system register flags.  */
1079           uint32_t flags;
1080         } sysreg;
1081
1082       const aarch64_cond *cond;
1083       /* The encoding of the PSTATE field.  */
1084       aarch64_insn pstatefield;
1085       const aarch64_sys_ins_reg *sysins_op;
1086       const struct aarch64_name_value_pair *barrier;
1087       const struct aarch64_name_value_pair *hint_option;
1088       const struct aarch64_name_value_pair *prfop;
1089     };
1090
1091   /* Operand shifter; in use when the operand is a register offset address,
1092      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1093   struct
1094     {
1095       enum aarch64_modifier_kind kind;
1096       unsigned operator_present: 1;     /* Only valid during encoding.  */
1097       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1098       unsigned amount_present: 1;
1099       int64_t amount;
1100     } shifter;
1101
1102   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1103                            to be done on it.  In some (but not all) of these
1104                            cases, we need to tell libopcodes to skip the
1105                            constraint checking and the encoding for this
1106                            operand, so that the libopcodes can pick up the
1107                            right opcode before the operand is fixed-up.  This
1108                            flag should only be used during the
1109                            assembling/encoding.  */
1110   unsigned present:1;   /* Whether this operand is present in the assembly
1111                            line; not used during the disassembly.  */
1112 };
1113
1114 typedef struct aarch64_opnd_info aarch64_opnd_info;
1115
1116 /* Structure representing an instruction.
1117
1118    It is used during both the assembling and disassembling.  The assembler
1119    fills an aarch64_inst after a successful parsing and then passes it to the
1120    encoding routine to do the encoding.  During the disassembling, the
1121    disassembler calls the decoding routine to decode a binary instruction; on a
1122    successful return, such a structure will be filled with information of the
1123    instruction; then the disassembler uses the information to print out the
1124    instruction.  */
1125
1126 struct aarch64_inst
1127 {
1128   /* The value of the binary instruction.  */
1129   aarch64_insn value;
1130
1131   /* Corresponding opcode entry.  */
1132   const aarch64_opcode *opcode;
1133
1134   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1135   const aarch64_cond *cond;
1136
1137   /* Operands information.  */
1138   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1139 };
1140
1141 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1142 #define HINT_OPD_CSYNC  0x11
1143 #define HINT_OPD_C      0x22
1144 #define HINT_OPD_J      0x24
1145 #define HINT_OPD_JC     0x26
1146 #define HINT_OPD_NULL   0x00
1147
1148 \f
1149 /* Diagnosis related declaration and interface.  */
1150
1151 /* Operand error kind enumerators.
1152
1153    AARCH64_OPDE_RECOVERABLE
1154      Less severe error found during the parsing, very possibly because that
1155      GAS has picked up a wrong instruction template for the parsing.
1156
1157    AARCH64_OPDE_SYNTAX_ERROR
1158      General syntax error; it can be either a user error, or simply because
1159      that GAS is trying a wrong instruction template.
1160
1161    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1162      Definitely a user syntax error.
1163
1164    AARCH64_OPDE_INVALID_VARIANT
1165      No syntax error, but the operands are not a valid combination, e.g.
1166      FMOV D0,S0
1167
1168    AARCH64_OPDE_UNTIED_OPERAND
1169      The asm failed to use the same register for a destination operand
1170      and a tied source operand.
1171
1172    AARCH64_OPDE_OUT_OF_RANGE
1173      Error about some immediate value out of a valid range.
1174
1175    AARCH64_OPDE_UNALIGNED
1176      Error about some immediate value not properly aligned (i.e. not being a
1177      multiple times of a certain value).
1178
1179    AARCH64_OPDE_REG_LIST
1180      Error about the register list operand having unexpected number of
1181      registers.
1182
1183    AARCH64_OPDE_OTHER_ERROR
1184      Error of the highest severity and used for any severe issue that does not
1185      fall into any of the above categories.
1186
1187    The enumerators are only interesting to GAS.  They are declared here (in
1188    libopcodes) because that some errors are detected (and then notified to GAS)
1189    by libopcodes (rather than by GAS solely).
1190
1191    The first three errors are only deteced by GAS while the
1192    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1193    only libopcodes has the information about the valid variants of each
1194    instruction.
1195
1196    The enumerators have an increasing severity.  This is helpful when there are
1197    multiple instruction templates available for a given mnemonic name (e.g.
1198    FMOV); this mechanism will help choose the most suitable template from which
1199    the generated diagnostics can most closely describe the issues, if any.  */
1200
1201 enum aarch64_operand_error_kind
1202 {
1203   AARCH64_OPDE_NIL,
1204   AARCH64_OPDE_RECOVERABLE,
1205   AARCH64_OPDE_SYNTAX_ERROR,
1206   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1207   AARCH64_OPDE_INVALID_VARIANT,
1208   AARCH64_OPDE_UNTIED_OPERAND,
1209   AARCH64_OPDE_OUT_OF_RANGE,
1210   AARCH64_OPDE_UNALIGNED,
1211   AARCH64_OPDE_REG_LIST,
1212   AARCH64_OPDE_OTHER_ERROR
1213 };
1214
1215 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1216 struct aarch64_operand_error
1217 {
1218   enum aarch64_operand_error_kind kind;
1219   int index;
1220   const char *error;
1221   int data[3];  /* Some data for extra information.  */
1222   bfd_boolean non_fatal;
1223 };
1224
1225 /* AArch64 sequence structure used to track instructions with F_SCAN
1226    dependencies for both assembler and disassembler.  */
1227 struct aarch64_instr_sequence
1228 {
1229   /* The instruction that caused this sequence to be opened.  */
1230   aarch64_inst *instr;
1231   /* The number of instructions the above instruction allows to be kept in the
1232      sequence before an automatic close is done.  */
1233   int num_insns;
1234   /* The instructions currently added to the sequence.  */
1235   aarch64_inst **current_insns;
1236   /* The number of instructions already in the sequence.  */
1237   int next_insn;
1238 };
1239
1240 /* Encoding entrypoint.  */
1241
1242 extern int
1243 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1244                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1245                        aarch64_operand_error *, aarch64_instr_sequence *);
1246
1247 extern const aarch64_opcode *
1248 aarch64_replace_opcode (struct aarch64_inst *,
1249                         const aarch64_opcode *);
1250
1251 /* Given the opcode enumerator OP, return the pointer to the corresponding
1252    opcode entry.  */
1253
1254 extern const aarch64_opcode *
1255 aarch64_get_opcode (enum aarch64_op);
1256
1257 /* Generate the string representation of an operand.  */
1258 extern void
1259 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1260                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1261                        char **);
1262
1263 /* Miscellaneous interface.  */
1264
1265 extern int
1266 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1267
1268 extern aarch64_opnd_qualifier_t
1269 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1270                                 const aarch64_opnd_qualifier_t, int);
1271
1272 extern bfd_boolean
1273 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1274
1275 extern int
1276 aarch64_num_of_operands (const aarch64_opcode *);
1277
1278 extern int
1279 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1280
1281 extern int
1282 aarch64_zero_register_p (const aarch64_opnd_info *);
1283
1284 extern enum err_type
1285 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1286                      aarch64_operand_error *);
1287
1288 extern void
1289 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1290
1291 /* Given an operand qualifier, return the expected data element size
1292    of a qualified operand.  */
1293 extern unsigned char
1294 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1295
1296 extern enum aarch64_operand_class
1297 aarch64_get_operand_class (enum aarch64_opnd);
1298
1299 extern const char *
1300 aarch64_get_operand_name (enum aarch64_opnd);
1301
1302 extern const char *
1303 aarch64_get_operand_desc (enum aarch64_opnd);
1304
1305 extern bfd_boolean
1306 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1307
1308 #ifdef DEBUG_AARCH64
1309 extern int debug_dump;
1310
1311 extern void
1312 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1313
1314 #define DEBUG_TRACE(M, ...)                                     \
1315   {                                                             \
1316     if (debug_dump)                                             \
1317       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1318   }
1319
1320 #define DEBUG_TRACE_IF(C, M, ...)                               \
1321   {                                                             \
1322     if (debug_dump && (C))                                      \
1323       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1324   }
1325 #else  /* !DEBUG_AARCH64 */
1326 #define DEBUG_TRACE(M, ...) ;
1327 #define DEBUG_TRACE_IF(C, M, ...) ;
1328 #endif /* DEBUG_AARCH64 */
1329
1330 extern const char *const aarch64_sve_pattern_array[32];
1331 extern const char *const aarch64_sve_prfop_array[16];
1332
1333 #ifdef __cplusplus
1334 }
1335 #endif
1336
1337 #endif /* OPCODE_AARCH64_H */