include/opcode/aarch64.h

   1 /* AArch64 assembler/disassembler support.
   2
   3    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GNU Binutils.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the license, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; see the file COPYING3. If not,
  20    see <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef OPCODE_AARCH64_H
  23 #define OPCODE_AARCH64_H
  24
  25 #include "bfd.h"
  26 #include "bfd_stdint.h"
  27 #include <assert.h>
  28 #include <stdlib.h>
  29
  30 #ifdef __cplusplus
  31 extern "C" {
  32 #endif
  33
  34 /* The offset for pc-relative addressing is currently defined to be 0.  */
  35 #define AARCH64_PCREL_OFFSET            0
  36
  37 typedef uint32_t aarch64_insn;
  38
  39 /* The following bitmasks control CPU features.  */
  40 #define AARCH64_FEATURE_SHA2    0x200000000ULL  /* SHA2 instructions.  */
  41 #define AARCH64_FEATURE_AES     0x800000000ULL  /* AES instructions.  */
  42 #define AARCH64_FEATURE_V8_4    0x000000800ULL  /* ARMv8.4 processors.  */
  43 #define AARCH64_FEATURE_SM4     0x100000000ULL  /* SM3 & SM4 instructions.  */
  44 #define AARCH64_FEATURE_SHA3    0x400000000ULL  /* SHA3 instructions.  */
  45 #define AARCH64_FEATURE_V8      0x00000001      /* All processors.  */
  46 #define AARCH64_FEATURE_V8_2    0x00000020      /* ARMv8.2 processors.  */
  47 #define AARCH64_FEATURE_V8_3    0x00000040      /* ARMv8.3 processors.  */
  48 #define AARCH64_FEATURE_CRYPTO  0x00010000      /* Crypto instructions.  */
  49 #define AARCH64_FEATURE_FP      0x00020000      /* FP instructions.  */
  50 #define AARCH64_FEATURE_SIMD    0x00040000      /* SIMD instructions.  */
  51 #define AARCH64_FEATURE_CRC     0x00080000      /* CRC instructions.  */
  52 #define AARCH64_FEATURE_LSE     0x00100000      /* LSE instructions.  */
  53 #define AARCH64_FEATURE_PAN     0x00200000      /* PAN instructions.  */
  54 #define AARCH64_FEATURE_LOR     0x00400000      /* LOR instructions.  */
  55 #define AARCH64_FEATURE_RDMA    0x00800000      /* v8.1 SIMD instructions.  */
  56 #define AARCH64_FEATURE_V8_1    0x01000000      /* v8.1 features.  */
  57 #define AARCH64_FEATURE_F16     0x02000000      /* v8.2 FP16 instructions.  */
  58 #define AARCH64_FEATURE_RAS     0x04000000      /* RAS Extensions.  */
  59 #define AARCH64_FEATURE_PROFILE 0x08000000      /* Statistical Profiling.  */
  60 #define AARCH64_FEATURE_SVE     0x10000000      /* SVE instructions.  */
  61 #define AARCH64_FEATURE_RCPC    0x20000000      /* RCPC instructions.  */
  62 #define AARCH64_FEATURE_COMPNUM 0x40000000      /* Complex # instructions.  */
  63 #define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
  64 #define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins.  */
  65 #define AARCH64_FEATURE_V8_5    0x2000000000ULL /* ARMv8.5 processors.  */
  66
  67 /* Flag Manipulation insns.  */
  68 #define AARCH64_FEATURE_FLAGMANIP       0x4000000000ULL
  69 /* FRINT[32,64][Z,X] insns.  */
  70 #define AARCH64_FEATURE_FRINTTS         0x8000000000ULL
  71 /* SB instruction.  */
  72 #define AARCH64_FEATURE_SB              0x10000000000ULL
  73 /* Execution and Data Prediction Restriction instructions.  */
  74 #define AARCH64_FEATURE_PREDRES         0x20000000000ULL
  75 /* DC CVADP.  */
  76 #define AARCH64_FEATURE_CVADP           0x40000000000ULL
  77 /* Random Number instructions.  */
  78 #define AARCH64_FEATURE_RNG             0x80000000000ULL
  79 /* BTI instructions.  */
  80 #define AARCH64_FEATURE_BTI             0x100000000000ULL
  81
  82 /* Architectures are the sum of the base and extensions.  */
  83 #define AARCH64_ARCH_V8         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
  84                                                  AARCH64_FEATURE_FP  \
  85                                                  | AARCH64_FEATURE_SIMD)
  86 #define AARCH64_ARCH_V8_1       AARCH64_FEATURE (AARCH64_ARCH_V8, \
  87                                                  AARCH64_FEATURE_CRC    \
  88                                                  | AARCH64_FEATURE_V8_1 \
  89                                                  | AARCH64_FEATURE_LSE  \
  90                                                  | AARCH64_FEATURE_PAN  \
  91                                                  | AARCH64_FEATURE_LOR  \
  92                                                  | AARCH64_FEATURE_RDMA)
  93 #define AARCH64_ARCH_V8_2       AARCH64_FEATURE (AARCH64_ARCH_V8_1,     \
  94                                                  AARCH64_FEATURE_V8_2   \
  95                                                  | AARCH64_FEATURE_RAS)
  96 #define AARCH64_ARCH_V8_3       AARCH64_FEATURE (AARCH64_ARCH_V8_2,     \
  97                                                  AARCH64_FEATURE_V8_3   \
  98                                                  | AARCH64_FEATURE_RCPC \
  99                                                  | AARCH64_FEATURE_COMPNUM)
 100 #define AARCH64_ARCH_V8_4       AARCH64_FEATURE (AARCH64_ARCH_V8_3,     \
 101                                                  AARCH64_FEATURE_V8_4   \
 102                                                  | AARCH64_FEATURE_DOTPROD \
 103                                                  | AARCH64_FEATURE_F16_FML)
 104 #define AARCH64_ARCH_V8_5       AARCH64_FEATURE (AARCH64_ARCH_V8_4,     \
 105                                                  AARCH64_FEATURE_V8_5   \
 106                                                  | AARCH64_FEATURE_FLAGMANIP \
 107                                                  | AARCH64_FEATURE_FRINTTS \
 108                                                  | AARCH64_FEATURE_SB   \
 109                                                  | AARCH64_FEATURE_PREDRES \
 110                                                  | AARCH64_FEATURE_CVADP \
 111                                                  | AARCH64_FEATURE_BTI)
 112
 113
 114 #define AARCH64_ARCH_NONE       AARCH64_FEATURE (0, 0)
 115 #define AARCH64_ANY             AARCH64_FEATURE (-1, 0) /* Any basic core.  */
 116
 117 /* CPU-specific features.  */
 118 typedef unsigned long long aarch64_feature_set;
 119
 120 #define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT)  \
 121   ((~(CPU) & (FEAT)) == 0)
 122
 123 #define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT)  \
 124   (((CPU) & (FEAT)) != 0)
 125
 126 #define AARCH64_CPU_HAS_FEATURE(CPU,FEAT)       \
 127   AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
 128
 129 #define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2)  \
 130   do                                            \
 131     {                                           \
 132       (TARG) = (F1) | (F2);                     \
 133     }                                           \
 134   while (0)
 135
 136 #define AARCH64_CLEAR_FEATURE(TARG,F1,F2)       \
 137   do                                            \
 138     {                                           \
 139       (TARG) = (F1) &~ (F2);                    \
 140     }                                           \
 141   while (0)
 142
 143 #define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
 144
 145 enum aarch64_operand_class
 146 {
 147   AARCH64_OPND_CLASS_NIL,
 148   AARCH64_OPND_CLASS_INT_REG,
 149   AARCH64_OPND_CLASS_MODIFIED_REG,
 150   AARCH64_OPND_CLASS_FP_REG,
 151   AARCH64_OPND_CLASS_SIMD_REG,
 152   AARCH64_OPND_CLASS_SIMD_ELEMENT,
 153   AARCH64_OPND_CLASS_SISD_REG,
 154   AARCH64_OPND_CLASS_SIMD_REGLIST,
 155   AARCH64_OPND_CLASS_SVE_REG,
 156   AARCH64_OPND_CLASS_PRED_REG,
 157   AARCH64_OPND_CLASS_ADDRESS,
 158   AARCH64_OPND_CLASS_IMMEDIATE,
 159   AARCH64_OPND_CLASS_SYSTEM,
 160   AARCH64_OPND_CLASS_COND,
 161 };
 162
 163 /* Operand code that helps both parsing and coding.
 164    Keep AARCH64_OPERANDS synced.  */
 165
 166 enum aarch64_opnd
 167 {
 168   AARCH64_OPND_NIL,     /* no operand---MUST BE FIRST!*/
 169
 170   AARCH64_OPND_Rd,      /* Integer register as destination.  */
 171   AARCH64_OPND_Rn,      /* Integer register as source.  */
 172   AARCH64_OPND_Rm,      /* Integer register as source.  */
 173   AARCH64_OPND_Rt,      /* Integer register used in ld/st instructions.  */
 174   AARCH64_OPND_Rt2,     /* Integer register used in ld/st pair instructions.  */
 175   AARCH64_OPND_Rs,      /* Integer register used in ld/st exclusive.  */
 176   AARCH64_OPND_Ra,      /* Integer register used in ddp_3src instructions.  */
 177   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
 178
 179   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
 180   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
 181   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
 182   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
 183   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
 184   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
 185
 186   AARCH64_OPND_Fd,      /* Floating-point Fd.  */
 187   AARCH64_OPND_Fn,      /* Floating-point Fn.  */
 188   AARCH64_OPND_Fm,      /* Floating-point Fm.  */
 189   AARCH64_OPND_Fa,      /* Floating-point Fa.  */
 190   AARCH64_OPND_Ft,      /* Floating-point Ft.  */
 191   AARCH64_OPND_Ft2,     /* Floating-point Ft2.  */
 192
 193   AARCH64_OPND_Sd,      /* AdvSIMD Scalar Sd.  */
 194   AARCH64_OPND_Sn,      /* AdvSIMD Scalar Sn.  */
 195   AARCH64_OPND_Sm,      /* AdvSIMD Scalar Sm.  */
 196
 197   AARCH64_OPND_Va,      /* AdvSIMD Vector Va.  */
 198   AARCH64_OPND_Vd,      /* AdvSIMD Vector Vd.  */
 199   AARCH64_OPND_Vn,      /* AdvSIMD Vector Vn.  */
 200   AARCH64_OPND_Vm,      /* AdvSIMD Vector Vm.  */
 201   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
 202   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
 203   AARCH64_OPND_Ed,      /* AdvSIMD Vector Element Vd.  */
 204   AARCH64_OPND_En,      /* AdvSIMD Vector Element Vn.  */
 205   AARCH64_OPND_Em,      /* AdvSIMD Vector Element Vm.  */
 206   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
 207                            qualifier is S_H.  */
 208   AARCH64_OPND_LVn,     /* AdvSIMD Vector register list used in e.g. TBL.  */
 209   AARCH64_OPND_LVt,     /* AdvSIMD Vector register list used in ld/st.  */
 210   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
 211                            structure to all lanes.  */
 212   AARCH64_OPND_LEt,     /* AdvSIMD Vector Element list.  */
 213
 214   AARCH64_OPND_CRn,     /* Co-processor register in CRn field.  */
 215   AARCH64_OPND_CRm,     /* Co-processor register in CRm field.  */
 216
 217   AARCH64_OPND_IDX,     /* AdvSIMD EXT index operand.  */
 218   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
 219   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
 220   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
 221   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
 222   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
 223   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
 224   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
 225                            (no encoding).  */
 226   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
 227   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
 228   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
 229   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
 230   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
 231   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
 232   AARCH64_OPND_IMM,     /* Immediate.  */
 233   AARCH64_OPND_IMM_2,   /* Immediate.  */
 234   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
 235   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
 236   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
 237   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
 238   AARCH64_OPND_BIT_NUM, /* Immediate.  */
 239   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
 240   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
 241   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
 242   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
 243                            each condition flag.  */
 244
 245   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
 246   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
 247   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
 248   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
 249   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
 250   AARCH64_OPND_IMM_ROT1,        /* Immediate rotate operand for FCMLA.  */
 251   AARCH64_OPND_IMM_ROT2,        /* Immediate rotate operand for indexed FCMLA.  */
 252   AARCH64_OPND_IMM_ROT3,        /* Immediate rotate operand for FCADD.  */
 253
 254   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
 255   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
 256
 257   AARCH64_OPND_ADDR_ADRP,       /* Memory address for ADRP */
 258   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
 259   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
 260   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
 261   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
 262
 263   AARCH64_OPND_ADDR_SIMPLE,     /* Address of ld/st exclusive.  */
 264   AARCH64_OPND_ADDR_REGOFF,     /* Address of register offset.  */
 265   AARCH64_OPND_ADDR_SIMM7,      /* Address of signed 7-bit immediate.  */
 266   AARCH64_OPND_ADDR_SIMM9,      /* Address of signed 9-bit immediate.  */
 267   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
 268                                    negative or unaligned and there is
 269                                    no writeback allowed.  This operand code
 270                                    is only used to support the programmer-
 271                                    friendly feature of using LDR/STR as the
 272                                    the mnemonic name for LDUR/STUR instructions
 273                                    wherever there is no ambiguity.  */
 274   AARCH64_OPND_ADDR_SIMM10,     /* Address of signed 10-bit immediate.  */
 275   AARCH64_OPND_ADDR_UIMM12,     /* Address of unsigned 12-bit immediate.  */
 276   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
 277   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
 278   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
 279
 280   AARCH64_OPND_SYSREG,          /* System register operand.  */
 281   AARCH64_OPND_PSTATEFIELD,     /* PSTATE field name operand.  */
 282   AARCH64_OPND_SYSREG_AT,       /* System register <at_op> operand.  */
 283   AARCH64_OPND_SYSREG_DC,       /* System register <dc_op> operand.  */
 284   AARCH64_OPND_SYSREG_IC,       /* System register <ic_op> operand.  */
 285   AARCH64_OPND_SYSREG_TLBI,     /* System register <tlbi_op> operand.  */
 286   AARCH64_OPND_SYSREG_SR,       /* System register RCTX operand.  */
 287   AARCH64_OPND_BARRIER,         /* Barrier operand.  */
 288   AARCH64_OPND_BARRIER_ISB,     /* Barrier operand for ISB.  */
 289   AARCH64_OPND_PRFOP,           /* Prefetch operation.  */
 290   AARCH64_OPND_BARRIER_PSB,     /* Barrier operand for PSB.  */
 291   AARCH64_OPND_BTI_TARGET,      /* BTI {<target>}.  */
 292
 293   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
 294   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
 295   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
 296   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
 297   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
 298   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
 299   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
 300   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
 301   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
 302   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
 303   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
 304   AARCH64_OPND_SVE_ADDR_R,          /* SVE [<Xn|SP>].  */
 305   AARCH64_OPND_SVE_ADDR_RR,         /* SVE [<Xn|SP>, <Xm|XZR>].  */
 306   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
 307   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
 308   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
 309   AARCH64_OPND_SVE_ADDR_RX,         /* SVE [<Xn|SP>, <Xm>].  */
 310   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
 311   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
 312   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
 313   AARCH64_OPND_SVE_ADDR_RZ,         /* SVE [<Xn|SP>, Zm.D].  */
 314   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
 315   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
 316   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
 317   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 318                                        Bit 14 controls S/U choice.  */
 319   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
 320                                        Bit 22 controls S/U choice.  */
 321   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 322                                        Bit 14 controls S/U choice.  */
 323   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
 324                                        Bit 22 controls S/U choice.  */
 325   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 326                                        Bit 14 controls S/U choice.  */
 327   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
 328                                        Bit 22 controls S/U choice.  */
 329   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 330                                        Bit 14 controls S/U choice.  */
 331   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
 332                                        Bit 22 controls S/U choice.  */
 333   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
 334   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
 335   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
 336   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
 337   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
 338   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
 339   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
 340   AARCH64_OPND_SVE_AIMM,        /* SVE unsigned arithmetic immediate.  */
 341   AARCH64_OPND_SVE_ASIMM,       /* SVE signed arithmetic immediate.  */
 342   AARCH64_OPND_SVE_FPIMM8,      /* SVE 8-bit floating-point immediate.  */
 343   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
 344   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
 345   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
 346   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
 347   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
 348   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
 349   AARCH64_OPND_SVE_LIMM,        /* SVE logical immediate.  */
 350   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
 351   AARCH64_OPND_SVE_PATTERN,     /* SVE vector pattern enumeration.  */
 352   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
 353   AARCH64_OPND_SVE_PRFOP,       /* SVE prefetch operation.  */
 354   AARCH64_OPND_SVE_Pd,          /* SVE p0-p15 in Pd.  */
 355   AARCH64_OPND_SVE_Pg3,         /* SVE p0-p7 in Pg.  */
 356   AARCH64_OPND_SVE_Pg4_5,       /* SVE p0-p15 in Pg, bits [8,5].  */
 357   AARCH64_OPND_SVE_Pg4_10,      /* SVE p0-p15 in Pg, bits [13,10].  */
 358   AARCH64_OPND_SVE_Pg4_16,      /* SVE p0-p15 in Pg, bits [19,16].  */
 359   AARCH64_OPND_SVE_Pm,          /* SVE p0-p15 in Pm.  */
 360   AARCH64_OPND_SVE_Pn,          /* SVE p0-p15 in Pn.  */
 361   AARCH64_OPND_SVE_Pt,          /* SVE p0-p15 in Pt.  */
 362   AARCH64_OPND_SVE_Rm,          /* Integer Rm or ZR, alt. SVE position.  */
 363   AARCH64_OPND_SVE_Rn_SP,       /* Integer Rn or SP, alt. SVE position.  */
 364   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
 365   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
 366   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
 367   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
 368   AARCH64_OPND_SVE_SIMM5,       /* SVE signed 5-bit immediate.  */
 369   AARCH64_OPND_SVE_SIMM5B,      /* SVE secondary signed 5-bit immediate.  */
 370   AARCH64_OPND_SVE_SIMM6,       /* SVE signed 6-bit immediate.  */
 371   AARCH64_OPND_SVE_SIMM8,       /* SVE signed 8-bit immediate.  */
 372   AARCH64_OPND_SVE_UIMM3,       /* SVE unsigned 3-bit immediate.  */
 373   AARCH64_OPND_SVE_UIMM7,       /* SVE unsigned 7-bit immediate.  */
 374   AARCH64_OPND_SVE_UIMM8,       /* SVE unsigned 8-bit immediate.  */
 375   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
 376   AARCH64_OPND_SVE_VZn,         /* Scalar SIMD&FP register in Zn field.  */
 377   AARCH64_OPND_SVE_Vd,          /* Scalar SIMD&FP register in Vd.  */
 378   AARCH64_OPND_SVE_Vm,          /* Scalar SIMD&FP register in Vm.  */
 379   AARCH64_OPND_SVE_Vn,          /* Scalar SIMD&FP register in Vn.  */
 380   AARCH64_OPND_SVE_Za_5,        /* SVE vector register in Za, bits [9,5].  */
 381   AARCH64_OPND_SVE_Za_16,       /* SVE vector register in Za, bits [20,16].  */
 382   AARCH64_OPND_SVE_Zd,          /* SVE vector register in Zd.  */
 383   AARCH64_OPND_SVE_Zm_5,        /* SVE vector register in Zm, bits [9,5].  */
 384   AARCH64_OPND_SVE_Zm_16,       /* SVE vector register in Zm, bits [20,16].  */
 385   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
 386   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
 387   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
 388   AARCH64_OPND_SVE_Zn,          /* SVE vector register in Zn.  */
 389   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
 390   AARCH64_OPND_SVE_ZnxN,        /* SVE vector register list in Zn.  */
 391   AARCH64_OPND_SVE_Zt,          /* SVE vector register in Zt.  */
 392   AARCH64_OPND_SVE_ZtxN,        /* SVE vector register list in Zt.  */
 393   AARCH64_OPND_SM3_IMM2,        /* SM3 encodes lane in bits [13, 14].  */
 394 };
 395
 396 /* Qualifier constrains an operand.  It either specifies a variant of an
 397    operand type or limits values available to an operand type.
 398
 399    N.B. Order is important; keep aarch64_opnd_qualifiers synced.  */
 400
 401 enum aarch64_opnd_qualifier
 402 {
 403   /* Indicating no further qualification on an operand.  */
 404   AARCH64_OPND_QLF_NIL,
 405
 406   /* Qualifying an operand which is a general purpose (integer) register;
 407      indicating the operand data size or a specific register.  */
 408   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
 409   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
 410   AARCH64_OPND_QLF_WSP, /* WSP.  */
 411   AARCH64_OPND_QLF_SP,  /* SP.  */
 412
 413   /* Qualifying an operand which is a floating-point register, a SIMD
 414      vector element or a SIMD vector element list; indicating operand data
 415      size or the size of each SIMD vector element in the case of a SIMD
 416      vector element list.
 417      These qualifiers are also used to qualify an address operand to
 418      indicate the size of data element a load/store instruction is
 419      accessing.
 420      They are also used for the immediate shift operand in e.g. SSHR.  Such
 421      a use is only for the ease of operand encoding/decoding and qualifier
 422      sequence matching; such a use should not be applied widely; use the value
 423      constraint qualifiers for immediate operands wherever possible.  */
 424   AARCH64_OPND_QLF_S_B,
 425   AARCH64_OPND_QLF_S_H,
 426   AARCH64_OPND_QLF_S_S,
 427   AARCH64_OPND_QLF_S_D,
 428   AARCH64_OPND_QLF_S_Q,
 429   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
 430      are selected by the instruction.  Other than that it has no difference
 431      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
 432      reasons and is an exception from normal AArch64 disassembly scheme.  */
 433   AARCH64_OPND_QLF_S_4B,
 434
 435   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
 436      register list; indicating register shape.
 437      They are also used for the immediate shift operand in e.g. SSHR.  Such
 438      a use is only for the ease of operand encoding/decoding and qualifier
 439      sequence matching; such a use should not be applied widely; use the value
 440      constraint qualifiers for immediate operands wherever possible.  */
 441   AARCH64_OPND_QLF_V_4B,
 442   AARCH64_OPND_QLF_V_8B,
 443   AARCH64_OPND_QLF_V_16B,
 444   AARCH64_OPND_QLF_V_2H,
 445   AARCH64_OPND_QLF_V_4H,
 446   AARCH64_OPND_QLF_V_8H,
 447   AARCH64_OPND_QLF_V_2S,
 448   AARCH64_OPND_QLF_V_4S,
 449   AARCH64_OPND_QLF_V_1D,
 450   AARCH64_OPND_QLF_V_2D,
 451   AARCH64_OPND_QLF_V_1Q,
 452
 453   AARCH64_OPND_QLF_P_Z,
 454   AARCH64_OPND_QLF_P_M,
 455
 456   /* Constraint on value.  */
 457   AARCH64_OPND_QLF_CR,          /* CRn, CRm. */
 458   AARCH64_OPND_QLF_imm_0_7,
 459   AARCH64_OPND_QLF_imm_0_15,
 460   AARCH64_OPND_QLF_imm_0_31,
 461   AARCH64_OPND_QLF_imm_0_63,
 462   AARCH64_OPND_QLF_imm_1_32,
 463   AARCH64_OPND_QLF_imm_1_64,
 464
 465   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
 466      or shift-ones.  */
 467   AARCH64_OPND_QLF_LSL,
 468   AARCH64_OPND_QLF_MSL,
 469
 470   /* Special qualifier helping retrieve qualifier information during the
 471      decoding time (currently not in use).  */
 472   AARCH64_OPND_QLF_RETRIEVE,
 473 };
 474 \f
 475 /* Instruction class.  */
 476
 477 enum aarch64_insn_class
 478 {
 479   addsub_carry,
 480   addsub_ext,
 481   addsub_imm,
 482   addsub_shift,
 483   asimdall,
 484   asimddiff,
 485   asimdelem,
 486   asimdext,
 487   asimdimm,
 488   asimdins,
 489   asimdmisc,
 490   asimdperm,
 491   asimdsame,
 492   asimdshf,
 493   asimdtbl,
 494   asisddiff,
 495   asisdelem,
 496   asisdlse,
 497   asisdlsep,
 498   asisdlso,
 499   asisdlsop,
 500   asisdmisc,
 501   asisdone,
 502   asisdpair,
 503   asisdsame,
 504   asisdshf,
 505   bitfield,
 506   branch_imm,
 507   branch_reg,
 508   compbranch,
 509   condbranch,
 510   condcmp_imm,
 511   condcmp_reg,
 512   condsel,
 513   cryptoaes,
 514   cryptosha2,
 515   cryptosha3,
 516   dp_1src,
 517   dp_2src,
 518   dp_3src,
 519   exception,
 520   extract,
 521   float2fix,
 522   float2int,
 523   floatccmp,
 524   floatcmp,
 525   floatdp1,
 526   floatdp2,
 527   floatdp3,
 528   floatimm,
 529   floatsel,
 530   ldst_immpost,
 531   ldst_immpre,
 532   ldst_imm9,    /* immpost or immpre */
 533   ldst_imm10,   /* LDRAA/LDRAB */
 534   ldst_pos,
 535   ldst_regoff,
 536   ldst_unpriv,
 537   ldst_unscaled,
 538   ldstexcl,
 539   ldstnapair_offs,
 540   ldstpair_off,
 541   ldstpair_indexed,
 542   loadlit,
 543   log_imm,
 544   log_shift,
 545   lse_atomic,
 546   movewide,
 547   pcreladdr,
 548   ic_system,
 549   sve_cpy,
 550   sve_index,
 551   sve_limm,
 552   sve_misc,
 553   sve_movprfx,
 554   sve_pred_zm,
 555   sve_shift_pred,
 556   sve_shift_unpred,
 557   sve_size_bhs,
 558   sve_size_bhsd,
 559   sve_size_hsd,
 560   sve_size_sd,
 561   testbranch,
 562   cryptosm3,
 563   cryptosm4,
 564   dotproduct,
 565 };
 566
 567 /* Opcode enumerators.  */
 568
 569 enum aarch64_op
 570 {
 571   OP_NIL,
 572   OP_STRB_POS,
 573   OP_LDRB_POS,
 574   OP_LDRSB_POS,
 575   OP_STRH_POS,
 576   OP_LDRH_POS,
 577   OP_LDRSH_POS,
 578   OP_STR_POS,
 579   OP_LDR_POS,
 580   OP_STRF_POS,
 581   OP_LDRF_POS,
 582   OP_LDRSW_POS,
 583   OP_PRFM_POS,
 584
 585   OP_STURB,
 586   OP_LDURB,
 587   OP_LDURSB,
 588   OP_STURH,
 589   OP_LDURH,
 590   OP_LDURSH,
 591   OP_STUR,
 592   OP_LDUR,
 593   OP_STURV,
 594   OP_LDURV,
 595   OP_LDURSW,
 596   OP_PRFUM,
 597
 598   OP_LDR_LIT,
 599   OP_LDRV_LIT,
 600   OP_LDRSW_LIT,
 601   OP_PRFM_LIT,
 602
 603   OP_ADD,
 604   OP_B,
 605   OP_BL,
 606
 607   OP_MOVN,
 608   OP_MOVZ,
 609   OP_MOVK,
 610
 611   OP_MOV_IMM_LOG,       /* MOV alias for moving bitmask immediate.  */
 612   OP_MOV_IMM_WIDE,      /* MOV alias for moving wide immediate.  */
 613   OP_MOV_IMM_WIDEN,     /* MOV alias for moving wide immediate (negated).  */
 614
 615   OP_MOV_V,             /* MOV alias for moving vector register.  */
 616
 617   OP_ASR_IMM,
 618   OP_LSR_IMM,
 619   OP_LSL_IMM,
 620
 621   OP_BIC,
 622
 623   OP_UBFX,
 624   OP_BFXIL,
 625   OP_SBFX,
 626   OP_SBFIZ,
 627   OP_BFI,
 628   OP_BFC,               /* ARMv8.2.  */
 629   OP_UBFIZ,
 630   OP_UXTB,
 631   OP_UXTH,
 632   OP_UXTW,
 633
 634   OP_CINC,
 635   OP_CINV,
 636   OP_CNEG,
 637   OP_CSET,
 638   OP_CSETM,
 639
 640   OP_FCVT,
 641   OP_FCVTN,
 642   OP_FCVTN2,
 643   OP_FCVTL,
 644   OP_FCVTL2,
 645   OP_FCVTXN_S,          /* Scalar version.  */
 646
 647   OP_ROR_IMM,
 648
 649   OP_SXTL,
 650   OP_SXTL2,
 651   OP_UXTL,
 652   OP_UXTL2,
 653
 654   OP_MOV_P_P,
 655   OP_MOV_Z_P_Z,
 656   OP_MOV_Z_V,
 657   OP_MOV_Z_Z,
 658   OP_MOV_Z_Zi,
 659   OP_MOVM_P_P_P,
 660   OP_MOVS_P_P,
 661   OP_MOVZS_P_P_P,
 662   OP_MOVZ_P_P_P,
 663   OP_NOTS_P_P_P_Z,
 664   OP_NOT_P_P_P_Z,
 665
 666   OP_FCMLA_ELEM,        /* ARMv8.3, indexed element version.  */
 667
 668   OP_TOTAL_NUM,         /* Pseudo.  */
 669 };
 670
 671 /* Error types.  */
 672 enum err_type
 673 {
 674   ERR_OK,
 675   ERR_UND,
 676   ERR_UNP,
 677   ERR_NYI,
 678   ERR_VFI,
 679   ERR_NR_ENTRIES
 680 };
 681
 682 /* Maximum number of operands an instruction can have.  */
 683 #define AARCH64_MAX_OPND_NUM 6
 684 /* Maximum number of qualifier sequences an instruction can have.  */
 685 #define AARCH64_MAX_QLF_SEQ_NUM 10
 686 /* Operand qualifier typedef; optimized for the size.  */
 687 typedef unsigned char aarch64_opnd_qualifier_t;
 688 /* Operand qualifier sequence typedef.  */
 689 typedef aarch64_opnd_qualifier_t        \
 690           aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
 691
 692 /* FIXME: improve the efficiency.  */
 693 static inline bfd_boolean
 694 empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
 695 {
 696   int i;
 697   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
 698     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
 699       return FALSE;
 700   return TRUE;
 701 }
 702
 703 /*  Forward declare error reporting type.  */
 704 typedef struct aarch64_operand_error aarch64_operand_error;
 705 /* Forward declare instruction sequence type.  */
 706 typedef struct aarch64_instr_sequence aarch64_instr_sequence;
 707 /* Forward declare instruction definition.  */
 708 typedef struct aarch64_inst aarch64_inst;
 709
 710 /* This structure holds information for a particular opcode.  */
 711
 712 struct aarch64_opcode
 713 {
 714   /* The name of the mnemonic.  */
 715   const char *name;
 716
 717   /* The opcode itself.  Those bits which will be filled in with
 718      operands are zeroes.  */
 719   aarch64_insn opcode;
 720
 721   /* The opcode mask.  This is used by the disassembler.  This is a
 722      mask containing ones indicating those bits which must match the
 723      opcode field, and zeroes indicating those bits which need not
 724      match (and are presumably filled in by operands).  */
 725   aarch64_insn mask;
 726
 727   /* Instruction class.  */
 728   enum aarch64_insn_class iclass;
 729
 730   /* Enumerator identifier.  */
 731   enum aarch64_op op;
 732
 733   /* Which architecture variant provides this instruction.  */
 734   const aarch64_feature_set *avariant;
 735
 736   /* An array of operand codes.  Each code is an index into the
 737      operand table.  They appear in the order which the operands must
 738      appear in assembly code, and are terminated by a zero.  */
 739   enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
 740
 741   /* A list of operand qualifier code sequence.  Each operand qualifier
 742      code qualifies the corresponding operand code.  Each operand
 743      qualifier sequence specifies a valid opcode variant and related
 744      constraint on operands.  */
 745   aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
 746
 747   /* Flags providing information about this instruction */
 748   uint64_t flags;
 749
 750   /* Extra constraints on the instruction that the verifier checks.  */
 751   uint32_t constraints;
 752
 753   /* If nonzero, this operand and operand 0 are both registers and
 754      are required to have the same register number.  */
 755   unsigned char tied_operand;
 756
 757   /* If non-NULL, a function to verify that a given instruction is valid.  */
 758   enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
 759                               bfd_vma, bfd_boolean, aarch64_operand_error *,
 760                               struct aarch64_instr_sequence *);
 761 };
 762
 763 typedef struct aarch64_opcode aarch64_opcode;
 764
 765 /* Table describing all the AArch64 opcodes.  */
 766 extern aarch64_opcode aarch64_opcode_table[];
 767
 768 /* Opcode flags.  */
 769 #define F_ALIAS (1 << 0)
 770 #define F_HAS_ALIAS (1 << 1)
 771 /* Disassembly preference priority 1-3 (the larger the higher).  If nothing
 772    is specified, it is the priority 0 by default, i.e. the lowest priority.  */
 773 #define F_P1 (1 << 2)
 774 #define F_P2 (2 << 2)
 775 #define F_P3 (3 << 2)
 776 /* Flag an instruction that is truly conditional executed, e.g. b.cond.  */
 777 #define F_COND (1 << 4)
 778 /* Instruction has the field of 'sf'.  */
 779 #define F_SF (1 << 5)
 780 /* Instruction has the field of 'size:Q'.  */
 781 #define F_SIZEQ (1 << 6)
 782 /* Floating-point instruction has the field of 'type'.  */
 783 #define F_FPTYPE (1 << 7)
 784 /* AdvSIMD scalar instruction has the field of 'size'.  */
 785 #define F_SSIZE (1 << 8)
 786 /* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q".  */
 787 #define F_T (1 << 9)
 788 /* Size of GPR operand in AdvSIMD instructions encoded in Q.  */
 789 #define F_GPRSIZE_IN_Q (1 << 10)
 790 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22.  */
 791 #define F_LDS_SIZE (1 << 11)
 792 /* Optional operand; assume maximum of 1 operand can be optional.  */
 793 #define F_OPD0_OPT (1 << 12)
 794 #define F_OPD1_OPT (2 << 12)
 795 #define F_OPD2_OPT (3 << 12)
 796 #define F_OPD3_OPT (4 << 12)
 797 #define F_OPD4_OPT (5 << 12)
 798 /* Default value for the optional operand when omitted from the assembly.  */
 799 #define F_DEFAULT(X) (((X) & 0x1f) << 15)
 800 /* Instruction that is an alias of another instruction needs to be
 801    encoded/decoded by converting it to/from the real form, followed by
 802    the encoding/decoding according to the rules of the real opcode.
 803    This compares to the direct coding using the alias's information.
 804    N.B. this flag requires F_ALIAS to be used together.  */
 805 #define F_CONV (1 << 20)
 806 /* Use together with F_ALIAS to indicate an alias opcode is a programmer
 807    friendly pseudo instruction available only in the assembly code (thus will
 808    not show up in the disassembly).  */
 809 #define F_PSEUDO (1 << 21)
 810 /* Instruction has miscellaneous encoding/decoding rules.  */
 811 #define F_MISC (1 << 22)
 812 /* Instruction has the field of 'N'; used in conjunction with F_SF.  */
 813 #define F_N (1 << 23)
 814 /* Opcode dependent field.  */
 815 #define F_OD(X) (((X) & 0x7) << 24)
 816 /* Instruction has the field of 'sz'.  */
 817 #define F_LSE_SZ (1 << 27)
 818 /* Require an exact qualifier match, even for NIL qualifiers.  */
 819 #define F_STRICT (1ULL << 28)
 820 /* This system instruction is used to read system registers.  */
 821 #define F_SYS_READ (1ULL << 29)
 822 /* This system instruction is used to write system registers.  */
 823 #define F_SYS_WRITE (1ULL << 30)
 824 /* This instruction has an extra constraint on it that imposes a requirement on
 825    subsequent instructions.  */
 826 #define F_SCAN (1ULL << 31)
 827 /* Next bit is 32.  */
 828
 829 /* Instruction constraints.  */
 830 /* This instruction has a predication constraint on the instruction at PC+4.  */
 831 #define C_SCAN_MOVPRFX (1U << 0)
 832 /* This instruction's operation width is determined by the operand with the
 833    largest element size.  */
 834 #define C_MAX_ELEM (1U << 1)
 835 /* Next bit is 2.  */
 836
 837 static inline bfd_boolean
 838 alias_opcode_p (const aarch64_opcode *opcode)
 839 {
 840   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 841 }
 842
 843 static inline bfd_boolean
 844 opcode_has_alias (const aarch64_opcode *opcode)
 845 {
 846   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 847 }
 848
 849 /* Priority for disassembling preference.  */
 850 static inline int
 851 opcode_priority (const aarch64_opcode *opcode)
 852 {
 853   return (opcode->flags >> 2) & 0x3;
 854 }
 855
 856 static inline bfd_boolean
 857 pseudo_opcode_p (const aarch64_opcode *opcode)
 858 {
 859   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 860 }
 861
 862 static inline bfd_boolean
 863 optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
 864 {
 865   return (((opcode->flags >> 12) & 0x7) == idx + 1)
 866     ? TRUE : FALSE;
 867 }
 868
 869 static inline aarch64_insn
 870 get_optional_operand_default_value (const aarch64_opcode *opcode)
 871 {
 872   return (opcode->flags >> 15) & 0x1f;
 873 }
 874
 875 static inline unsigned int
 876 get_opcode_dependent_value (const aarch64_opcode *opcode)
 877 {
 878   return (opcode->flags >> 24) & 0x7;
 879 }
 880
 881 static inline bfd_boolean
 882 opcode_has_special_coder (const aarch64_opcode *opcode)
 883 {
 884   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 885           | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
 886     : FALSE;
 887 }
 888 \f
 889 struct aarch64_name_value_pair
 890 {
 891   const char *  name;
 892   aarch64_insn  value;
 893 };
 894
 895 extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
 896 extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
 897 extern const struct aarch64_name_value_pair aarch64_prfops [32];
 898 extern const struct aarch64_name_value_pair aarch64_hint_options [];
 899
 900 typedef struct
 901 {
 902   const char *  name;
 903   aarch64_insn  value;
 904   uint32_t      flags;
 905 } aarch64_sys_reg;
 906
 907 extern const aarch64_sys_reg aarch64_sys_regs [];
 908 extern const aarch64_sys_reg aarch64_pstatefields [];
 909 extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
 910 extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
 911                                                 const aarch64_sys_reg *);
 912 extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
 913                                                     const aarch64_sys_reg *);
 914
 915 typedef struct
 916 {
 917   const char *name;
 918   uint32_t value;
 919   uint32_t flags ;
 920 } aarch64_sys_ins_reg;
 921
 922 extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
 923 extern bfd_boolean
 924 aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
 925                                  const aarch64_sys_ins_reg *);
 926
 927 extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
 928 extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
 929 extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
 930 extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
 931 extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
 932
 933 /* Shift/extending operator kinds.
 934    N.B. order is important; keep aarch64_operand_modifiers synced.  */
 935 enum aarch64_modifier_kind
 936 {
 937   AARCH64_MOD_NONE,
 938   AARCH64_MOD_MSL,
 939   AARCH64_MOD_ROR,
 940   AARCH64_MOD_ASR,
 941   AARCH64_MOD_LSR,
 942   AARCH64_MOD_LSL,
 943   AARCH64_MOD_UXTB,
 944   AARCH64_MOD_UXTH,
 945   AARCH64_MOD_UXTW,
 946   AARCH64_MOD_UXTX,
 947   AARCH64_MOD_SXTB,
 948   AARCH64_MOD_SXTH,
 949   AARCH64_MOD_SXTW,
 950   AARCH64_MOD_SXTX,
 951   AARCH64_MOD_MUL,
 952   AARCH64_MOD_MUL_VL,
 953 };
 954
 955 bfd_boolean
 956 aarch64_extend_operator_p (enum aarch64_modifier_kind);
 957
 958 enum aarch64_modifier_kind
 959 aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
 960 /* Condition.  */
 961
 962 typedef struct
 963 {
 964   /* A list of names with the first one as the disassembly preference;
 965      terminated by NULL if fewer than 3.  */
 966   const char *names[4];
 967   aarch64_insn value;
 968 } aarch64_cond;
 969
 970 extern const aarch64_cond aarch64_conds[16];
 971
 972 const aarch64_cond* get_cond_from_value (aarch64_insn value);
 973 const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
 974 \f
 975 /* Structure representing an operand.  */
 976
 977 struct aarch64_opnd_info
 978 {
 979   enum aarch64_opnd type;
 980   aarch64_opnd_qualifier_t qualifier;
 981   int idx;
 982
 983   union
 984     {
 985       struct
 986         {
 987           unsigned regno;
 988         } reg;
 989       struct
 990         {
 991           unsigned int regno;
 992           int64_t index;
 993         } reglane;
 994       /* e.g. LVn.  */
 995       struct
 996         {
 997           unsigned first_regno : 5;
 998           unsigned num_regs : 3;
 999           /* 1 if it is a list of reg element.  */
1000           unsigned has_index : 1;
1001           /* Lane index; valid only when has_index is 1.  */
1002           int64_t index;
1003         } reglist;
1004       /* e.g. immediate or pc relative address offset.  */
1005       struct
1006         {
1007           int64_t value;
1008           unsigned is_fp : 1;
1009         } imm;
1010       /* e.g. address in STR (register offset).  */
1011       struct
1012         {
1013           unsigned base_regno;
1014           struct
1015             {
1016               union
1017                 {
1018                   int imm;
1019                   unsigned regno;
1020                 };
1021               unsigned is_reg;
1022             } offset;
1023           unsigned pcrel : 1;           /* PC-relative.  */
1024           unsigned writeback : 1;
1025           unsigned preind : 1;          /* Pre-indexed.  */
1026           unsigned postind : 1;         /* Post-indexed.  */
1027         } addr;
1028
1029       struct
1030         {
1031           /* The encoding of the system register.  */
1032           aarch64_insn value;
1033
1034           /* The system register flags.  */
1035           uint32_t flags;
1036         } sysreg;
1037
1038       const aarch64_cond *cond;
1039       /* The encoding of the PSTATE field.  */
1040       aarch64_insn pstatefield;
1041       const aarch64_sys_ins_reg *sysins_op;
1042       const struct aarch64_name_value_pair *barrier;
1043       const struct aarch64_name_value_pair *hint_option;
1044       const struct aarch64_name_value_pair *prfop;
1045     };
1046
1047   /* Operand shifter; in use when the operand is a register offset address,
1048      add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}.  */
1049   struct
1050     {
1051       enum aarch64_modifier_kind kind;
1052       unsigned operator_present: 1;     /* Only valid during encoding.  */
1053       /* Value of the 'S' field in ld/st reg offset; used only in decoding.  */
1054       unsigned amount_present: 1;
1055       int64_t amount;
1056     } shifter;
1057
1058   unsigned skip:1;      /* Operand is not completed if there is a fixup needed
1059                            to be done on it.  In some (but not all) of these
1060                            cases, we need to tell libopcodes to skip the
1061                            constraint checking and the encoding for this
1062                            operand, so that the libopcodes can pick up the
1063                            right opcode before the operand is fixed-up.  This
1064                            flag should only be used during the
1065                            assembling/encoding.  */
1066   unsigned present:1;   /* Whether this operand is present in the assembly
1067                            line; not used during the disassembly.  */
1068 };
1069
1070 typedef struct aarch64_opnd_info aarch64_opnd_info;
1071
1072 /* Structure representing an instruction.
1073
1074    It is used during both the assembling and disassembling.  The assembler
1075    fills an aarch64_inst after a successful parsing and then passes it to the
1076    encoding routine to do the encoding.  During the disassembling, the
1077    disassembler calls the decoding routine to decode a binary instruction; on a
1078    successful return, such a structure will be filled with information of the
1079    instruction; then the disassembler uses the information to print out the
1080    instruction.  */
1081
1082 struct aarch64_inst
1083 {
1084   /* The value of the binary instruction.  */
1085   aarch64_insn value;
1086
1087   /* Corresponding opcode entry.  */
1088   const aarch64_opcode *opcode;
1089
1090   /* Condition for a truly conditional-executed instrutions, e.g. b.cond.  */
1091   const aarch64_cond *cond;
1092
1093   /* Operands information.  */
1094   aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1095 };
1096
1097 /* Defining the HINT #imm values for the aarch64_hint_options.  */
1098 #define HINT_OPD_CSYNC  0x11
1099 #define HINT_OPD_C      0x22
1100 #define HINT_OPD_J      0x24
1101 #define HINT_OPD_JC     0x26
1102 #define HINT_OPD_NULL   0x00
1103
1104 \f
1105 /* Diagnosis related declaration and interface.  */
1106
1107 /* Operand error kind enumerators.
1108
1109    AARCH64_OPDE_RECOVERABLE
1110      Less severe error found during the parsing, very possibly because that
1111      GAS has picked up a wrong instruction template for the parsing.
1112
1113    AARCH64_OPDE_SYNTAX_ERROR
1114      General syntax error; it can be either a user error, or simply because
1115      that GAS is trying a wrong instruction template.
1116
1117    AARCH64_OPDE_FATAL_SYNTAX_ERROR
1118      Definitely a user syntax error.
1119
1120    AARCH64_OPDE_INVALID_VARIANT
1121      No syntax error, but the operands are not a valid combination, e.g.
1122      FMOV D0,S0
1123
1124    AARCH64_OPDE_UNTIED_OPERAND
1125      The asm failed to use the same register for a destination operand
1126      and a tied source operand.
1127
1128    AARCH64_OPDE_OUT_OF_RANGE
1129      Error about some immediate value out of a valid range.
1130
1131    AARCH64_OPDE_UNALIGNED
1132      Error about some immediate value not properly aligned (i.e. not being a
1133      multiple times of a certain value).
1134
1135    AARCH64_OPDE_REG_LIST
1136      Error about the register list operand having unexpected number of
1137      registers.
1138
1139    AARCH64_OPDE_OTHER_ERROR
1140      Error of the highest severity and used for any severe issue that does not
1141      fall into any of the above categories.
1142
1143    The enumerators are only interesting to GAS.  They are declared here (in
1144    libopcodes) because that some errors are detected (and then notified to GAS)
1145    by libopcodes (rather than by GAS solely).
1146
1147    The first three errors are only deteced by GAS while the
1148    AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1149    only libopcodes has the information about the valid variants of each
1150    instruction.
1151
1152    The enumerators have an increasing severity.  This is helpful when there are
1153    multiple instruction templates available for a given mnemonic name (e.g.
1154    FMOV); this mechanism will help choose the most suitable template from which
1155    the generated diagnostics can most closely describe the issues, if any.  */
1156
1157 enum aarch64_operand_error_kind
1158 {
1159   AARCH64_OPDE_NIL,
1160   AARCH64_OPDE_RECOVERABLE,
1161   AARCH64_OPDE_SYNTAX_ERROR,
1162   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1163   AARCH64_OPDE_INVALID_VARIANT,
1164   AARCH64_OPDE_UNTIED_OPERAND,
1165   AARCH64_OPDE_OUT_OF_RANGE,
1166   AARCH64_OPDE_UNALIGNED,
1167   AARCH64_OPDE_REG_LIST,
1168   AARCH64_OPDE_OTHER_ERROR
1169 };
1170
1171 /* N.B. GAS assumes that this structure work well with shallow copy.  */
1172 struct aarch64_operand_error
1173 {
1174   enum aarch64_operand_error_kind kind;
1175   int index;
1176   const char *error;
1177   int data[3];  /* Some data for extra information.  */
1178   bfd_boolean non_fatal;
1179 };
1180
1181 /* AArch64 sequence structure used to track instructions with F_SCAN
1182    dependencies for both assembler and disassembler.  */
1183 struct aarch64_instr_sequence
1184 {
1185   /* The instruction that caused this sequence to be opened.  */
1186   aarch64_inst *instr;
1187   /* The number of instructions the above instruction allows to be kept in the
1188      sequence before an automatic close is done.  */
1189   int num_insns;
1190   /* The instructions currently added to the sequence.  */
1191   aarch64_inst **current_insns;
1192   /* The number of instructions already in the sequence.  */
1193   int next_insn;
1194 };
1195
1196 /* Encoding entrypoint.  */
1197
1198 extern int
1199 aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1200                        aarch64_insn *, aarch64_opnd_qualifier_t *,
1201                        aarch64_operand_error *, aarch64_instr_sequence *);
1202
1203 extern const aarch64_opcode *
1204 aarch64_replace_opcode (struct aarch64_inst *,
1205                         const aarch64_opcode *);
1206
1207 /* Given the opcode enumerator OP, return the pointer to the corresponding
1208    opcode entry.  */
1209
1210 extern const aarch64_opcode *
1211 aarch64_get_opcode (enum aarch64_op);
1212
1213 /* Generate the string representation of an operand.  */
1214 extern void
1215 aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
1216                        const aarch64_opnd_info *, int, int *, bfd_vma *,
1217                        char **);
1218
1219 /* Miscellaneous interface.  */
1220
1221 extern int
1222 aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1223
1224 extern aarch64_opnd_qualifier_t
1225 aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1226                                 const aarch64_opnd_qualifier_t, int);
1227
1228 extern bfd_boolean
1229 aarch64_is_destructive_by_operands (const aarch64_opcode *);
1230
1231 extern int
1232 aarch64_num_of_operands (const aarch64_opcode *);
1233
1234 extern int
1235 aarch64_stack_pointer_p (const aarch64_opnd_info *);
1236
1237 extern int
1238 aarch64_zero_register_p (const aarch64_opnd_info *);
1239
1240 extern enum err_type
1241 aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
1242                      aarch64_operand_error *);
1243
1244 extern void
1245 init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
1246
1247 /* Given an operand qualifier, return the expected data element size
1248    of a qualified operand.  */
1249 extern unsigned char
1250 aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1251
1252 extern enum aarch64_operand_class
1253 aarch64_get_operand_class (enum aarch64_opnd);
1254
1255 extern const char *
1256 aarch64_get_operand_name (enum aarch64_opnd);
1257
1258 extern const char *
1259 aarch64_get_operand_desc (enum aarch64_opnd);
1260
1261 extern bfd_boolean
1262 aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1263
1264 #ifdef DEBUG_AARCH64
1265 extern int debug_dump;
1266
1267 extern void
1268 aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1269
1270 #define DEBUG_TRACE(M, ...)                                     \
1271   {                                                             \
1272     if (debug_dump)                                             \
1273       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1274   }
1275
1276 #define DEBUG_TRACE_IF(C, M, ...)                               \
1277   {                                                             \
1278     if (debug_dump && (C))                                      \
1279       aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__);  \
1280   }
1281 #else  /* !DEBUG_AARCH64 */
1282 #define DEBUG_TRACE(M, ...) ;
1283 #define DEBUG_TRACE_IF(C, M, ...) ;
1284 #endif /* DEBUG_AARCH64 */
1285
1286 extern const char *const aarch64_sve_pattern_array[32];
1287 extern const char *const aarch64_sve_prfop_array[16];
1288
1289 #ifdef __cplusplus
1290 }
1291 #endif
1292
1293 #endif /* OPCODE_AARCH64_H */