include/opcode/alpha.h

   1 /* alpha.h -- Header file for Alpha opcode table
   2    Copyright 1996 Free Software Foundation, Inc.
   3    Contributed by Richard Henderson <rth@tamu.edu>,
   4    patterned after the PPC opcode table written by Ian Lance Taylor.
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef OPCODE_ALPHA_H
  23 #define OPCODE_ALPHA_H
  24
  25 #include "bfd.h"                /* for bfd_reloc_code_real_type */
  26
  27 /* The opcode table is an array of struct alpha_opcode.  */
  28
  29 struct alpha_opcode
  30 {
  31   /* The opcode name.  */
  32   const char *name;
  33
  34   /* The opcode itself.  Those bits which will be filled in with
  35      operands are zeroes.  */
  36   unsigned opcode;
  37
  38   /* The opcode mask.  This is used by the disassembler.  This is a
  39      mask containing ones indicating those bits which must match the
  40      opcode field, and zeroes indicating those bits which need not
  41      match (and are presumably filled in by operands).  */
  42   unsigned mask;
  43
  44   /* One bit flags for the opcode.  These are primarily used to
  45      indicate specific processors and environments support the
  46      instructions.  The defined values are listed below. */
  47   unsigned flags;
  48
  49   /* An array of operand codes.  Each code is an index into the
  50      operand table.  They appear in the order which the operands must
  51      appear in assembly code, and are terminated by a zero.  */
  52   unsigned char operands[4];
  53 };
  54
  55 /* The table itself is sorted by major opcode number, and is otherwise
  56    in the order in which the disassembler should consider
  57    instructions.  */
  58 extern const struct alpha_opcode alpha_opcodes[];
  59 extern const int alpha_num_opcodes;
  60
  61 /* Values defined for the flags field of a struct alpha_opcode.  */
  62
  63 /* CPU Availability */
  64 #define AXP_OPCODE_ALL          00001
  65 #define AXP_OPCODE_EV4          00002
  66 /* EV45 is not programatically different */
  67 #define AXP_OPCODE_EV5          00004
  68 #define AXP_OPCODE_EV56         00010
  69
  70 /* A macro to extract the major opcode from an instruction.  */
  71 #define AXP_OP(i)       (((i) >> 26) & 0x3F)
  72
  73 /* The total number of major opcodes. */
  74 #define AXP_NOPS        0x40
  75
  76 \f
  77 /* The operands table is an array of struct alpha_operand.  */
  78
  79 struct alpha_operand
  80 {
  81   /* The number of bits in the operand.  */
  82   int bits;
  83
  84   /* How far the operand is left shifted in the instruction.  */
  85   int shift;
  86
  87   /* The default relocation type for this operand.  */
  88   bfd_reloc_code_real_type default_reloc;
  89
  90   /* Insertion function.  This is used by the assembler.  To insert an
  91      operand value into an instruction, check this field.
  92
  93      If it is NULL, execute
  94          i |= (op & ((1 << o->bits) - 1)) << o->shift;
  95      (i is the instruction which we are filling in, o is a pointer to
  96      this structure, and op is the opcode value; this assumes twos
  97      complement arithmetic).
  98
  99      If this field is not NULL, then simply call it with the
 100      instruction and the operand value.  It will return the new value
 101      of the instruction.  If the ERRMSG argument is not NULL, then if
 102      the operand value is illegal, *ERRMSG will be set to a warning
 103      string (the operand will be inserted in any case).  If the
 104      operand value is legal, *ERRMSG will be unchanged (most operands
 105      can accept any value).  */
 106   unsigned (*insert) PARAMS ((unsigned instruction, int op,
 107                               const char **errmsg));
 108
 109   /* Extraction function.  This is used by the disassembler.  To
 110      extract this operand type from an instruction, check this field.
 111
 112      If it is NULL, compute
 113          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 114          if ((o->flags & AXP_OPERAND_SIGNED) != 0
 115              && (op & (1 << (o->bits - 1))) != 0)
 116            op -= 1 << o->bits;
 117      (i is the instruction, o is a pointer to this structure, and op
 118      is the result; this assumes twos complement arithmetic).
 119
 120      If this field is not NULL, then simply call it with the
 121      instruction value.  It will return the value of the operand.  If
 122      the INVALID argument is not NULL, *INVALID will be set to
 123      non-zero if this operand type can not actually be extracted from
 124      this operand (i.e., the instruction does not match).  If the
 125      operand is valid, *INVALID will not be changed.  */
 126   int (*extract) PARAMS ((unsigned instruction, int *invalid));
 127
 128   /* One bit syntax flags.  */
 129   unsigned flags;
 130 };
 131
 132 /* Elements in the table are retrieved by indexing with values from
 133    the operands field of the alpha_opcodes table.  */
 134
 135 extern const struct alpha_operand alpha_operands[];
 136 extern const int alpha_num_operands;
 137
 138 /* Values defined for the flags field of a struct alpha_operand.  */
 139
 140 /* Mask for selecting the type for typecheck purposes */
 141 #define AXP_OPERAND_TYPECHECK_MASK                                      \
 142   (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA | AXP_OPERAND_IR |            \
 143    AXP_OPERAND_FPR | AXP_OPERAND_RELATIVE | AXP_OPERAND_SIGNED |        \
 144    AXP_OPERAND_UNSIGNED)
 145
 146 /* This operand does not actually exist in the assembler input.  This
 147    is used to support extended mnemonics, for which two operands fields
 148    are identical.  The assembler should call the insert function with
 149    any op value.  The disassembler should call the extract function,
 150    ignore the return value, and check the value placed in the invalid
 151    argument.  */
 152 #define AXP_OPERAND_FAKE        01
 153
 154 /* The operand should be wrapped in parentheses rather than separated
 155    from the previous by a comma.  This is used for the load and store
 156    instructions which want their operands to look like "Ra,disp(Rb)".  */
 157 #define AXP_OPERAND_PARENS      02
 158
 159 /* Used in combination with PARENS, this supresses the supression of
 160    the comma.  This is used for "jmp Ra,(Rb),hint".  */
 161 #define AXP_OPERAND_COMMA       04
 162
 163 /* This operand names an integer register.  */
 164 #define AXP_OPERAND_IR          010
 165
 166 /* This operand names a floating point register.  */
 167 #define AXP_OPERAND_FPR         020
 168
 169 /* This operand is a relative branch displacement.  The disassembler
 170    prints these symbolically if possible.  */
 171 #define AXP_OPERAND_RELATIVE    040
 172
 173 /* This operand takes signed values.  */
 174 #define AXP_OPERAND_SIGNED      0100
 175
 176 /* This operand takes unsigned values.  This exists primarily so that
 177    a flags value of 0 can be treated as end-of-arguments.  */
 178 #define AXP_OPERAND_UNSIGNED    0200
 179
 180 /* Supress overflow detection on this field.  This is used for hints. */
 181 #define AXP_OPERAND_NOOVERFLOW  0400
 182
 183 /* Mask for optional argument default value.  */
 184 #define AXP_OPERAND_OPTIONAL_MASK 07000
 185
 186 /* This operand defaults to zero.  This is used for jump hints.  */
 187 #define AXP_OPERAND_DEFAULT_ZERO 01000
 188
 189 /* This operand should default to the first (real) operand and is used
 190    in conjunction with AXP_OPERAND_OPTIONAL.  This allows
 191    "and $0,3,$0" to be written as "and $0,3", etc.  I don't like
 192    it, but it's what DEC does.  */
 193 #define AXP_OPERAND_DEFAULT_FIRST 02000
 194
 195 /* Similarly, this operand should default to the second (real) operand.
 196    This allows "negl $0" instead of "negl $0,$0".  */
 197 #define AXP_OPERAND_DEFAULT_SECOND 04000
 198
 199 \f
 200 /* Register common names */
 201
 202 #define AXP_REG_V0      0
 203 #define AXP_REG_T0      1
 204 #define AXP_REG_T1      2
 205 #define AXP_REG_T2      3
 206 #define AXP_REG_T3      4
 207 #define AXP_REG_T4      5
 208 #define AXP_REG_T5      6
 209 #define AXP_REG_T6      7
 210 #define AXP_REG_T7      8
 211 #define AXP_REG_S0      9
 212 #define AXP_REG_S1      10
 213 #define AXP_REG_S2      11
 214 #define AXP_REG_S3      12
 215 #define AXP_REG_S4      13
 216 #define AXP_REG_S5      14
 217 #define AXP_REG_FP      15
 218 #define AXP_REG_A0      16
 219 #define AXP_REG_A1      17
 220 #define AXP_REG_A2      18
 221 #define AXP_REG_A3      19
 222 #define AXP_REG_A4      20
 223 #define AXP_REG_A5      21
 224 #define AXP_REG_T8      22
 225 #define AXP_REG_T9      23
 226 #define AXP_REG_T10     24
 227 #define AXP_REG_T11     25
 228 #define AXP_REG_RA      26
 229 #define AXP_REG_PV      27
 230 #define AXP_REG_T12     27
 231 #define AXP_REG_AT      28
 232 #define AXP_REG_GP      29
 233 #define AXP_REG_SP      30
 234 #define AXP_REG_ZERO    31
 235
 236 #endif /* OPCODE_ALPHA_H */