1 /* Opcode table for the ARC.
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
6 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
9 GAS/GDB is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS/GDB is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS or GDB; see the file COPYING3. If not, write to
21 the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
28 #define MAX_INSN_ARGS 8
32 #define MAX_INSN_FLGS 3
35 /* Instruction Class. */
54 /* Instruction Subclass. */
85 /* At most one flag from the set of flags can appear in the
87 F_CLASS_OPTIONAL
= (1 << 0),
89 /* Exactly one from from the set of flags must appear in the
91 F_CLASS_REQUIRED
= (1 << 1),
93 /* The conditional code can be extended over the standard variants
94 via .extCondCode pseudo-op. */
95 F_CLASS_EXTEND
= (1 << 2),
97 /* Condition code flag. */
98 F_CLASS_COND
= (1 << 3)
101 /* The opcode table is an array of struct arc_opcode. */
104 /* The opcode name. */
107 /* The opcode itself. Those bits which will be filled in with
108 operands are zeroes. */
111 /* The opcode mask. This is used by the disassembler. This is a
112 mask containing ones indicating those bits which must match the
113 opcode field, and zeroes indicating those bits which need not
114 match (and are presumably filled in by operands). */
117 /* One bit flags for the opcode. These are primarily used to
118 indicate specific processors and environments support the
119 instructions. The defined values are listed below. */
122 /* The instruction class. This is used by gdb. */
123 insn_class_t insn_class
;
125 /* The instruction subclass. */
126 insn_subclass_t subclass
;
128 /* An array of operand codes. Each code is an index into the
129 operand table. They appear in the order which the operands must
130 appear in assembly code, and are terminated by a zero. */
131 unsigned char operands
[MAX_INSN_ARGS
+ 1];
133 /* An array of flag codes. Each code is an index into the flag
134 table. They appear in the order which the flags must appear in
135 assembly code, and are terminated by a zero. */
136 unsigned char flags
[MAX_INSN_FLGS
+ 1];
139 /* The table itself is sorted by major opcode number, and is otherwise
140 in the order in which the disassembler should consider
142 extern const struct arc_opcode arc_opcodes
[];
144 /* CPU Availability. */
145 #define ARC_OPCODE_NONE 0x0000
146 #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
147 #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
148 #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
149 #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
150 #define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
153 #define ARC_OPCODE_ARCALL (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \
154 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
155 #define ARC_OPCODE_ARCFPX (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
157 /* CPU extensions. */
158 #define ARC_EA 0x0001
159 #define ARC_CD 0x0001 /* Mutual exclusive with EA. */
160 #define ARC_LLOCK 0x0002
161 #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
162 #define ARC_MPY 0x0004
163 #define ARC_MULT 0x0004
165 /* Floating point support. */
166 #define ARC_DPFP 0x0010
167 #define ARC_SPFP 0x0020
168 #define ARC_FPU 0x0030
169 #define ARC_FPUDA 0x0040
172 #define ARC_SWAP 0x0100
173 #define ARC_NORM 0x0200
174 #define ARC_BSCAN 0x0200
177 #define ARC_UIX 0x1000
178 #define ARC_TSTAMP 0x1000
181 #define ARC_VBFDW 0x1000
182 #define ARC_BARREL 0x1000
183 #define ARC_DSPA 0x1000
186 #define ARC_SHIFT 0x1000
189 #define ARC_INTR 0x1000
190 #define ARC_DIV 0x1000
193 #define ARC_XMAC 0x1000
194 #define ARC_CRC 0x1000
196 /* A macro to check for short instructions. */
197 #define ARC_SHORT(mask) \
198 (((mask) & 0xFFFF0000) ? 0 : 1)
200 /* The operands table is an array of struct arc_operand. */
203 /* The number of bits in the operand. */
206 /* How far the operand is left shifted in the instruction. */
209 /* The default relocation type for this operand. */
210 signed int default_reloc
;
212 /* One bit syntax flags. */
215 /* Insertion function. This is used by the assembler. To insert an
216 operand value into an instruction, check this field.
218 If it is NULL, execute
219 i |= (op & ((1 << o->bits) - 1)) << o->shift;
220 (i is the instruction which we are filling in, o is a pointer to
221 this structure, and op is the opcode value; this assumes twos
222 complement arithmetic).
224 If this field is not NULL, then simply call it with the
225 instruction and the operand value. It will return the new value
226 of the instruction. If the ERRMSG argument is not NULL, then if
227 the operand value is illegal, *ERRMSG will be set to a warning
228 string (the operand will be inserted in any case). If the
229 operand value is legal, *ERRMSG will be unchanged (most operands
230 can accept any value). */
231 unsigned (*insert
) (unsigned instruction
, int op
, const char **errmsg
);
233 /* Extraction function. This is used by the disassembler. To
234 extract this operand type from an instruction, check this field.
236 If it is NULL, compute
237 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
238 if ((o->flags & ARC_OPERAND_SIGNED) != 0
239 && (op & (1 << (o->bits - 1))) != 0)
241 (i is the instruction, o is a pointer to this structure, and op
242 is the result; this assumes twos complement arithmetic).
244 If this field is not NULL, then simply call it with the
245 instruction value. It will return the value of the operand. If
246 the INVALID argument is not NULL, *INVALID will be set to
247 TRUE if this operand type can not actually be extracted from
248 this operand (i.e., the instruction does not match). If the
249 operand is valid, *INVALID will not be changed. */
250 int (*extract
) (unsigned instruction
, bfd_boolean
*invalid
);
253 /* Elements in the table are retrieved by indexing with values from
254 the operands field of the arc_opcodes table. */
255 extern const struct arc_operand arc_operands
[];
256 extern const unsigned arc_num_operands
;
257 extern const unsigned arc_Toperand
;
258 extern const unsigned arc_NToperand
;
260 /* Values defined for the flags field of a struct arc_operand. */
262 /* This operand does not actually exist in the assembler input. This
263 is used to support extended mnemonics, for which two operands fields
264 are identical. The assembler should call the insert function with
265 any op value. The disassembler should call the extract function,
266 ignore the return value, and check the value placed in the invalid
268 #define ARC_OPERAND_FAKE 0x0001
270 /* This operand names an integer register. */
271 #define ARC_OPERAND_IR 0x0002
273 /* This operand takes signed values. */
274 #define ARC_OPERAND_SIGNED 0x0004
276 /* This operand takes unsigned values. This exists primarily so that
277 a flags value of 0 can be treated as end-of-arguments. */
278 #define ARC_OPERAND_UNSIGNED 0x0008
280 /* This operand takes long immediate values. */
281 #define ARC_OPERAND_LIMM 0x0010
283 /* This operand is identical like the previous one. */
284 #define ARC_OPERAND_DUPLICATE 0x0020
286 /* This operand is PC relative. Used for internal relocs. */
287 #define ARC_OPERAND_PCREL 0x0040
289 /* This operand is truncated. The truncation is done accordingly to
290 operand alignment attribute. */
291 #define ARC_OPERAND_TRUNCATE 0x0080
293 /* This operand is 16bit aligned. */
294 #define ARC_OPERAND_ALIGNED16 0x0100
296 /* This operand is 32bit aligned. */
297 #define ARC_OPERAND_ALIGNED32 0x0200
299 /* This operand can be ignored by matching process if it is not
301 #define ARC_OPERAND_IGNORE 0x0400
303 /* Don't check the range when matching. */
304 #define ARC_OPERAND_NCHK 0x0800
306 /* Mark the braket possition. */
307 #define ARC_OPERAND_BRAKET 0x1000
309 /* Mask for selecting the type for typecheck purposes. */
310 #define ARC_OPERAND_TYPECHECK_MASK \
312 ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \
313 ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
315 /* The flags structure. */
316 struct arc_flag_operand
324 /* The number of bits in the operand. */
327 /* How far the operand is left shifted in the instruction. */
330 /* Available for disassembler. */
331 unsigned char favail
;
334 /* The flag operands table. */
335 extern const struct arc_flag_operand arc_flag_operands
[];
336 extern const unsigned arc_num_flag_operands
;
338 /* The flag's class structure. */
339 struct arc_flag_class
342 flag_class_t flag_class
;
344 /* List of valid flags (codes). */
348 extern const struct arc_flag_class arc_flag_classes
[];
350 /* Structure for special cases. */
351 struct arc_flag_special
353 /* Name of special case instruction. */
356 /* List of flags applicable for special case instruction. */
360 extern const struct arc_flag_special arc_flag_special_cases
[];
361 extern const unsigned arc_num_flag_special
;
363 /* Relocation equivalence structure. */
364 struct arc_reloc_equiv_tab
366 const char * name
; /* String to lookup. */
367 const char * mnemonic
; /* Extra matching condition. */
368 unsigned flags
[32]; /* Extra matching condition. */
369 signed int oldreloc
; /* Old relocation. */
370 signed int newreloc
; /* New relocation. */
373 extern const struct arc_reloc_equiv_tab arc_reloc_equiv
[];
374 extern const unsigned arc_num_equiv_tab
;
376 /* Structure for operand operations for pseudo/alias instructions. */
377 struct arc_operand_operation
379 /* The index for operand from operand array. */
380 unsigned operand_idx
;
382 /* Defines if it needs the operand inserted by the assembler or
383 whether this operand comes from the pseudo instruction's
385 unsigned char needs_insert
;
387 /* Count we have to add to the operand. Use negative number to
388 subtract from the operand. Also use this number to add to 0 if
389 the operand needs to be inserted (i.e. needs_insert == 1). */
392 /* Index of the operand to swap with. To be done AFTER applying
394 unsigned swap_operand_idx
;
397 /* Structure for pseudo/alias instructions. */
398 struct arc_pseudo_insn
400 /* Mnemonic for pseudo/alias insn. */
401 const char *mnemonic_p
;
403 /* Mnemonic for real instruction. */
404 const char *mnemonic_r
;
406 /* Flag that will have to be added (if any). */
409 /* Amount of operands. */
410 unsigned operand_cnt
;
412 /* Array of operand operations. */
413 struct arc_operand_operation operand
[6];
416 extern const struct arc_pseudo_insn arc_pseudo_insns
[];
417 extern const unsigned arc_num_pseudo_insn
;
419 /* Structure for AUXILIARY registers. */
422 /* Register address. */
425 /* One bit flags for the opcode. These are primarily used to
426 indicate specific processors and environments support the
430 /* AUX register subclass. */
431 insn_subclass_t subclass
;
436 /* Size of the string. */
440 extern const struct arc_aux_reg arc_aux_regs
[];
441 extern const unsigned arc_num_aux_regs
;
443 extern const struct arc_opcode arc_relax_opcodes
[];
444 extern const unsigned arc_num_relax_opcodes
;
446 /* Macro used for generating one class of NPS instructions. */
447 #define NPS_CMEM_HIGH_VALUE 0x57f0
449 /* Macros to help generating regular pattern instructions. */
450 #define FIELDA(word) (word & 0x3F)
451 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
452 #define FIELDC(word) ((word & 0x3F) << 6)
453 #define FIELDF (0x01 << 15)
454 #define FIELDQ (0x1F)
456 #define INSN3OP(MOP,SOP) (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
457 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
458 #define INSN2OP(MOP,SOP) (INSN2OPX (MOP,0x2F,SOP))
460 #define INSN3OP_ABC(MOP,SOP) (INSN3OP (MOP,SOP))
461 #define INSN3OP_ALC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62))
462 #define INSN3OP_ABL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDC (62))
463 #define INSN3OP_ALL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
464 #define INSN3OP_0BC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62))
465 #define INSN3OP_0LC(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
466 #define INSN3OP_0BL(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
467 #define INSN3OP_0LL(MOP,SOP) \
468 (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
469 #define INSN3OP_ABU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22))
470 #define INSN3OP_ALU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
471 #define INSN3OP_0BU(MOP,SOP) (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
472 #define INSN3OP_0LU(MOP,SOP) \
473 (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
474 #define INSN3OP_BBS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22))
475 #define INSN3OP_0LS(MOP,SOP) (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
476 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
477 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
478 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
479 #define INSN3OP_C0LL(MOP,SOP) \
480 (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
481 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
482 #define INSN3OP_C0LU(MOP,SOP) \
483 (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
485 #define MINSN3OP_ABC (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
486 #define MINSN3OP_ALC (~(FIELDF | FIELDA (63) | FIELDC (63)))
487 #define MINSN3OP_ABL (~(FIELDF | FIELDA (63) | FIELDB (63)))
488 #define MINSN3OP_ALL (~(FIELDF | FIELDA (63)))
489 #define MINSN3OP_0BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
490 #define MINSN3OP_0LC (~(FIELDF | FIELDC (63)))
491 #define MINSN3OP_0BL (~(FIELDF | FIELDB (63)))
492 #define MINSN3OP_0LL (~(FIELDF))
493 #define MINSN3OP_ABU (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
494 #define MINSN3OP_ALU (~(FIELDF | FIELDA (63) | FIELDC (63)))
495 #define MINSN3OP_0BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
496 #define MINSN3OP_0LU (~(FIELDF | FIELDC (63)))
497 #define MINSN3OP_BBS (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
498 #define MINSN3OP_0LS (~(FIELDF | FIELDA (63) | FIELDC (63)))
499 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
500 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
501 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
502 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
503 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
504 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
506 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
507 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
508 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
509 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
510 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
511 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
513 #define MINSN2OP_BC (~(FIELDF | FIELDB (63) | FIELDC (63)))
514 #define MINSN2OP_BL (~(FIELDF | FIELDB (63)))
515 #define MINSN2OP_0C (~(FIELDF | FIELDC (63)))
516 #define MINSN2OP_0L (~(FIELDF))
517 #define MINSN2OP_BU (~(FIELDF | FIELDB (63) | FIELDC (63)))
518 #define MINSN2OP_0U (~(FIELDF | FIELDC (63)))
520 /* Various constants used when defining an extension instruction. */
521 #define ARC_SYNTAX_3OP (1 << 0)
522 #define ARC_SYNTAX_2OP (1 << 1)
523 #define ARC_SYNTAX_1OP (1 << 2)
524 #define ARC_SYNTAX_NOP (1 << 3)
525 #define ARC_SYNTAX_MASK (0x0F)
527 #define ARC_OP1_MUST_BE_IMM (1 << 0)
528 #define ARC_OP1_IMM_IMPLIED (1 << 1)
530 #define ARC_SUFFIX_NONE (1 << 0)
531 #define ARC_SUFFIX_COND (1 << 1)
532 #define ARC_SUFFIX_FLAG (1 << 2)
534 #define ARC_REGISTER_READONLY (1 << 0)
535 #define ARC_REGISTER_WRITEONLY (1 << 1)
536 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
538 /* Constants needed to initialize extension instructions. */
539 extern const unsigned char flags_none
[MAX_INSN_FLGS
+ 1];
540 extern const unsigned char flags_f
[MAX_INSN_FLGS
+ 1];
541 extern const unsigned char flags_cc
[MAX_INSN_FLGS
+ 1];
542 extern const unsigned char flags_ccf
[MAX_INSN_FLGS
+ 1];
544 extern const unsigned char arg_none
[MAX_INSN_ARGS
+ 1];
545 extern const unsigned char arg_32bit_rarbrc
[MAX_INSN_ARGS
+ 1];
546 extern const unsigned char arg_32bit_zarbrc
[MAX_INSN_ARGS
+ 1];
547 extern const unsigned char arg_32bit_rbrbrc
[MAX_INSN_ARGS
+ 1];
548 extern const unsigned char arg_32bit_rarbu6
[MAX_INSN_ARGS
+ 1];
549 extern const unsigned char arg_32bit_zarbu6
[MAX_INSN_ARGS
+ 1];
550 extern const unsigned char arg_32bit_rbrbu6
[MAX_INSN_ARGS
+ 1];
551 extern const unsigned char arg_32bit_rbrbs12
[MAX_INSN_ARGS
+ 1];
552 extern const unsigned char arg_32bit_ralimmrc
[MAX_INSN_ARGS
+ 1];
553 extern const unsigned char arg_32bit_rarblimm
[MAX_INSN_ARGS
+ 1];
554 extern const unsigned char arg_32bit_zalimmrc
[MAX_INSN_ARGS
+ 1];
555 extern const unsigned char arg_32bit_zarblimm
[MAX_INSN_ARGS
+ 1];
557 extern const unsigned char arg_32bit_rbrblimm
[MAX_INSN_ARGS
+ 1];
558 extern const unsigned char arg_32bit_ralimmu6
[MAX_INSN_ARGS
+ 1];
559 extern const unsigned char arg_32bit_zalimmu6
[MAX_INSN_ARGS
+ 1];
561 extern const unsigned char arg_32bit_zalimms12
[MAX_INSN_ARGS
+ 1];
562 extern const unsigned char arg_32bit_ralimmlimm
[MAX_INSN_ARGS
+ 1];
563 extern const unsigned char arg_32bit_zalimmlimm
[MAX_INSN_ARGS
+ 1];
565 extern const unsigned char arg_32bit_rbrc
[MAX_INSN_ARGS
+ 1];
566 extern const unsigned char arg_32bit_zarc
[MAX_INSN_ARGS
+ 1];
567 extern const unsigned char arg_32bit_rbu6
[MAX_INSN_ARGS
+ 1];
568 extern const unsigned char arg_32bit_zau6
[MAX_INSN_ARGS
+ 1];
569 extern const unsigned char arg_32bit_rblimm
[MAX_INSN_ARGS
+ 1];
570 extern const unsigned char arg_32bit_zalimm
[MAX_INSN_ARGS
+ 1];
572 extern const unsigned char arg_32bit_limmrc
[MAX_INSN_ARGS
+ 1];
573 extern const unsigned char arg_32bit_limmu6
[MAX_INSN_ARGS
+ 1];
574 extern const unsigned char arg_32bit_limms12
[MAX_INSN_ARGS
+ 1];
575 extern const unsigned char arg_32bit_limmlimm
[MAX_INSN_ARGS
+ 1];
577 extern const unsigned char arg_32bit_rc
[MAX_INSN_ARGS
+ 1];
578 extern const unsigned char arg_32bit_u6
[MAX_INSN_ARGS
+ 1];
579 extern const unsigned char arg_32bit_limm
[MAX_INSN_ARGS
+ 1];
581 #endif /* OPCODE_ARC_H */