include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        4
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BBIT0,
  46   BBIT1,
  47   BI,
  48   BIH,
  49   BITOP,
  50   BITSTREAM,
  51   BMU,
  52   BRANCH,
  53   BRCC,
  54   CONTROL,
  55   DIVREM,
  56   DMA,
  57   DPI,
  58   DSP,
  59   EI,
  60   ENTER,
  61   FLOAT,
  62   INVALID,
  63   JLI,
  64   JUMP,
  65   KERNEL,
  66   LEAVE,
  67   LOAD,
  68   LOGICAL,
  69   LOOP,
  70   MEMORY,
  71   MISC,
  72   MOVE,
  73   MPY,
  74   NET,
  75   PROTOCOL_DECODE,
  76   PMU,
  77   POP,
  78   PUSH,
  79   STORE,
  80   SUB,
  81   ULTRAIP,
  82   XY
  83 } insn_class_t;
  84
  85 /* Instruction Subclass.  */
  86 typedef enum
  87 {
  88   NONE     = 0,
  89   CVT      = (1U << 1),
  90   BTSCN    = (1U << 2),
  91   CD       = (1U << 3),
  92   CD1      = CD,
  93   CD2      = CD,
  94   COND     = (1U << 4),
  95   DIV      = (1U << 5),
  96   DP       = (1U << 6),
  97   DPA      = (1U << 7),
  98   DPX      = (1U << 8),
  99   LL64     = (1U << 9),
 100   MPY1E    = (1U << 10),
 101   MPY6E    = (1U << 11),
 102   MPY7E    = (1U << 12),
 103   MPY8E    = (1U << 13),
 104   MPY9E    = (1U << 14),
 105   NPS400   = (1U << 15),
 106   QUARKSE1 = (1U << 16),
 107   QUARKSE2 = (1U << 17),
 108   SHFT1    = (1U << 18),
 109   SHFT2    = (1U << 19),
 110   SWAP     = (1U << 20),
 111   SP       = (1U << 21),
 112   SPX      = (1U << 22)
 113 } insn_subclass_t;
 114
 115 /* Flags class.  */
 116 typedef enum
 117 {
 118   F_CLASS_NONE = 0,
 119
 120   /* At most one flag from the set of flags can appear in the
 121      instruction.  */
 122   F_CLASS_OPTIONAL = (1 << 0),
 123
 124   /* Exactly one from from the set of flags must appear in the
 125      instruction.  */
 126   F_CLASS_REQUIRED = (1 << 1),
 127
 128   /* The conditional code can be extended over the standard variants
 129      via .extCondCode pseudo-op.  */
 130   F_CLASS_EXTEND = (1 << 2),
 131
 132   /* Condition code flag.  */
 133   F_CLASS_COND = (1 << 3),
 134
 135   /* Write back mode.  */
 136   F_CLASS_WB = (1 << 4),
 137
 138   /* Data size.  */
 139   F_CLASS_ZZ = (1 << 5),
 140
 141   /* Implicit flag.  */
 142   F_CLASS_IMPLICIT = (1 << 6)
 143 } flag_class_t;
 144
 145 /* The opcode table is an array of struct arc_opcode.  */
 146 struct arc_opcode
 147 {
 148   /* The opcode name.  */
 149   const char * name;
 150
 151   /* The opcode itself.  Those bits which will be filled in with
 152      operands are zeroes.  */
 153   unsigned long long opcode;
 154
 155   /* The opcode mask.  This is used by the disassembler.  This is a
 156      mask containing ones indicating those bits which must match the
 157      opcode field, and zeroes indicating those bits which need not
 158      match (and are presumably filled in by operands).  */
 159   unsigned long long mask;
 160
 161   /* One bit flags for the opcode.  These are primarily used to
 162      indicate specific processors and environments support the
 163      instructions.  The defined values are listed below.  */
 164   unsigned cpu;
 165
 166   /* The instruction class.  This is used by gdb.  */
 167   insn_class_t insn_class;
 168
 169   /* The instruction subclass.  */
 170   insn_subclass_t subclass;
 171
 172   /* An array of operand codes.  Each code is an index into the
 173      operand table.  They appear in the order which the operands must
 174      appear in assembly code, and are terminated by a zero.  */
 175   unsigned char operands[MAX_INSN_ARGS + 1];
 176
 177   /* An array of flag codes.  Each code is an index into the flag
 178      table.  They appear in the order which the flags must appear in
 179      assembly code, and are terminated by a zero.  */
 180   unsigned char flags[MAX_INSN_FLGS + 1];
 181 };
 182
 183 /* The table itself is sorted by major opcode number, and is otherwise
 184    in the order in which the disassembler should consider
 185    instructions.  */
 186 extern const struct arc_opcode arc_opcodes[];
 187
 188 /* Return length of an instruction represented by OPCODE, in bytes.  */
 189 extern int arc_opcode_len (const struct arc_opcode *opcode);
 190
 191 /* CPU Availability.  */
 192 #define ARC_OPCODE_NONE     0x0000
 193 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 194 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 195 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 196 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 197
 198 /* CPU combi.  */
 199 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 200                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 201 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 202 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 203 #define ARC_OPCODE_ARCMPY6E  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
 204
 205 /* The operands table is an array of struct arc_operand.  */
 206 struct arc_operand
 207 {
 208   /* The number of bits in the operand.  */
 209   unsigned int bits;
 210
 211   /* How far the operand is left shifted in the instruction.  */
 212   unsigned int shift;
 213
 214   /* The default relocation type for this operand.  */
 215   signed int default_reloc;
 216
 217   /* One bit syntax flags.  */
 218   unsigned int flags;
 219
 220   /* Insertion function.  This is used by the assembler.  To insert an
 221      operand value into an instruction, check this field.
 222
 223      If it is NULL, execute
 224          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 225      (i is the instruction which we are filling in, o is a pointer to
 226      this structure, and op is the opcode value; this assumes twos
 227      complement arithmetic).
 228
 229      If this field is not NULL, then simply call it with the
 230      instruction and the operand value.  It will return the new value
 231      of the instruction.  If the ERRMSG argument is not NULL, then if
 232      the operand value is illegal, *ERRMSG will be set to a warning
 233      string (the operand will be inserted in any case).  If the
 234      operand value is legal, *ERRMSG will be unchanged (most operands
 235      can accept any value).  */
 236   unsigned long long (*insert) (unsigned long long instruction,
 237                                 long long int op,
 238                                 const char **errmsg);
 239
 240   /* Extraction function.  This is used by the disassembler.  To
 241      extract this operand type from an instruction, check this field.
 242
 243      If it is NULL, compute
 244          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 245          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 246              && (op & (1 << (o->bits - 1))) != 0)
 247            op -= 1 << o->bits;
 248      (i is the instruction, o is a pointer to this structure, and op
 249      is the result; this assumes twos complement arithmetic).
 250
 251      If this field is not NULL, then simply call it with the
 252      instruction value.  It will return the value of the operand.  If
 253      the INVALID argument is not NULL, *INVALID will be set to
 254      TRUE if this operand type can not actually be extracted from
 255      this operand (i.e., the instruction does not match).  If the
 256      operand is valid, *INVALID will not be changed.  */
 257   long long int (*extract) (unsigned long long instruction,
 258                             bfd_boolean *invalid);
 259 };
 260
 261 /* Elements in the table are retrieved by indexing with values from
 262    the operands field of the arc_opcodes table.  */
 263 extern const struct arc_operand arc_operands[];
 264 extern const unsigned arc_num_operands;
 265 extern const unsigned arc_Toperand;
 266 extern const unsigned arc_NToperand;
 267
 268 /* Values defined for the flags field of a struct arc_operand.  */
 269
 270 /* This operand does not actually exist in the assembler input.  This
 271    is used to support extended mnemonics, for which two operands fields
 272    are identical.  The assembler should call the insert function with
 273    any op value.  The disassembler should call the extract function,
 274    ignore the return value, and check the value placed in the invalid
 275    argument.  */
 276 #define ARC_OPERAND_FAKE        0x0001
 277
 278 /* This operand names an integer register.  */
 279 #define ARC_OPERAND_IR          0x0002
 280
 281 /* This operand takes signed values.  */
 282 #define ARC_OPERAND_SIGNED      0x0004
 283
 284 /* This operand takes unsigned values.  This exists primarily so that
 285    a flags value of 0 can be treated as end-of-arguments.  */
 286 #define ARC_OPERAND_UNSIGNED    0x0008
 287
 288 /* This operand takes long immediate values.  */
 289 #define ARC_OPERAND_LIMM        0x0010
 290
 291 /* This operand is identical like the previous one.  */
 292 #define ARC_OPERAND_DUPLICATE   0x0020
 293
 294 /* This operand is PC relative.  Used for internal relocs.  */
 295 #define ARC_OPERAND_PCREL       0x0040
 296
 297 /* This operand is truncated.  The truncation is done accordingly to
 298    operand alignment attribute.  */
 299 #define ARC_OPERAND_TRUNCATE    0x0080
 300
 301 /* This operand is 16bit aligned.  */
 302 #define ARC_OPERAND_ALIGNED16   0x0100
 303
 304 /* This operand is 32bit aligned.  */
 305 #define ARC_OPERAND_ALIGNED32   0x0200
 306
 307 /* This operand can be ignored by matching process if it is not
 308    present.  */
 309 #define ARC_OPERAND_IGNORE      0x0400
 310
 311 /* Don't check the range when matching.  */
 312 #define ARC_OPERAND_NCHK        0x0800
 313
 314 /* Mark the braket possition.  */
 315 #define ARC_OPERAND_BRAKET      0x1000
 316
 317 /* Address type operand for NPS400.  */
 318 #define ARC_OPERAND_ADDRTYPE    0x2000
 319
 320 /* Mark the colon position.  */
 321 #define ARC_OPERAND_COLON       0x4000
 322
 323 /* Mask for selecting the type for typecheck purposes.  */
 324 #define ARC_OPERAND_TYPECHECK_MASK               \
 325   (ARC_OPERAND_IR                                \
 326    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 327    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 328    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 329
 330 /* Macro to determine if an operand is a fake operand.  */
 331 #define ARC_OPERAND_IS_FAKE(op)                     \
 332   ((operand->flags & ARC_OPERAND_FAKE)              \
 333    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 334         || (operand->flags & ARC_OPERAND_COLON)))
 335
 336 /* The flags structure.  */
 337 struct arc_flag_operand
 338 {
 339   /* The flag name.  */
 340   const char * name;
 341
 342   /* The flag code.  */
 343   unsigned code;
 344
 345   /* The number of bits in the operand.  */
 346   unsigned int bits;
 347
 348   /* How far the operand is left shifted in the instruction.  */
 349   unsigned int shift;
 350
 351   /* Available for disassembler.  */
 352   unsigned char favail;
 353 };
 354
 355 /* The flag operands table.  */
 356 extern const struct arc_flag_operand arc_flag_operands[];
 357 extern const unsigned arc_num_flag_operands;
 358
 359 /* The flag's class structure.  */
 360 struct arc_flag_class
 361 {
 362   /* Flag class.  */
 363   flag_class_t flag_class;
 364
 365   /* List of valid flags (codes).  */
 366   unsigned flags[256];
 367 };
 368
 369 extern const struct arc_flag_class arc_flag_classes[];
 370
 371 /* Structure for special cases.  */
 372 struct arc_flag_special
 373 {
 374   /* Name of special case instruction.  */
 375   const char *name;
 376
 377   /* List of flags applicable for special case instruction.  */
 378   unsigned flags[32];
 379 };
 380
 381 extern const struct arc_flag_special arc_flag_special_cases[];
 382 extern const unsigned arc_num_flag_special;
 383
 384 /* Relocation equivalence structure.  */
 385 struct arc_reloc_equiv_tab
 386 {
 387   const char * name;       /* String to lookup.  */
 388   const char * mnemonic;   /* Extra matching condition.  */
 389   unsigned     flags[32];  /* Extra matching condition.  */
 390   signed int   oldreloc;   /* Old relocation.  */
 391   signed int   newreloc;   /* New relocation.  */
 392 };
 393
 394 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 395 extern const unsigned arc_num_equiv_tab;
 396
 397 /* Structure for operand operations for pseudo/alias instructions.  */
 398 struct arc_operand_operation
 399 {
 400   /* The index for operand from operand array.  */
 401   unsigned operand_idx;
 402
 403   /* Defines if it needs the operand inserted by the assembler or
 404      whether this operand comes from the pseudo instruction's
 405      operands.  */
 406   unsigned char needs_insert;
 407
 408   /* Count we have to add to the operand.  Use negative number to
 409      subtract from the operand.  Also use this number to add to 0 if
 410      the operand needs to be inserted (i.e. needs_insert == 1).  */
 411   int count;
 412
 413   /* Index of the operand to swap with.  To be done AFTER applying
 414      inc_count.  */
 415   unsigned swap_operand_idx;
 416 };
 417
 418 /* Structure for pseudo/alias instructions.  */
 419 struct arc_pseudo_insn
 420 {
 421   /* Mnemonic for pseudo/alias insn.  */
 422   const char * mnemonic_p;
 423
 424   /* Mnemonic for real instruction.  */
 425   const char * mnemonic_r;
 426
 427   /* Flag that will have to be added (if any).  */
 428   const char * flag_r;
 429
 430   /* Amount of operands.  */
 431   unsigned operand_cnt;
 432
 433   /* Array of operand operations.  */
 434   struct arc_operand_operation operand[6];
 435 };
 436
 437 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 438 extern const unsigned arc_num_pseudo_insn;
 439
 440 /* Structure for AUXILIARY registers.  */
 441 struct arc_aux_reg
 442 {
 443   /* Register address.  */
 444   int address;
 445
 446   /* One bit flags for the opcode.  These are primarily used to
 447      indicate specific processors and environments support the
 448      instructions.  */
 449   unsigned cpu;
 450
 451   /* AUX register subclass.  */
 452   insn_subclass_t subclass;
 453
 454   /* Register name.  */
 455   const char * name;
 456
 457   /* Size of the string.  */
 458   size_t length;
 459 };
 460
 461 extern const struct arc_aux_reg arc_aux_regs[];
 462 extern const unsigned arc_num_aux_regs;
 463
 464 extern const struct arc_opcode arc_relax_opcodes[];
 465 extern const unsigned arc_num_relax_opcodes;
 466
 467 /* Macro used for generating one class of NPS instructions.  */
 468 #define NPS_CMEM_HIGH_VALUE 0x57f0
 469
 470 /* Macros to help generating regular pattern instructions.  */
 471 #define FIELDA(word) (word & 0x3F)
 472 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 473 #define FIELDC(word) ((word & 0x3F) << 6)
 474 #define FIELDF       (0x01 << 15)
 475 #define FIELDQ       (0x1F)
 476
 477 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 478 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 479 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 480
 481 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 482 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 483 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 484 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 485 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 486 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 487 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 488 #define INSN3OP_0LL(MOP,SOP)                                    \
 489   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 490 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 491 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 492 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 493 #define INSN3OP_0LU(MOP,SOP)                                    \
 494   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 495 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 496 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 497 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 498 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 499 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 500 #define INSN3OP_C0LL(MOP,SOP)                                   \
 501   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 502 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 503 #define INSN3OP_C0LU(MOP,SOP)                                   \
 504   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 505
 506 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
 507
 508 #define MINSN3OP_ABC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 509 #define MINSN3OP_ALC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 510 #define MINSN3OP_ABL  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
 511 #define MINSN3OP_ALL  (MASK_32BIT (~(FIELDF | FIELDA (63))))
 512 #define MINSN3OP_0BC  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 513 #define MINSN3OP_0LC  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 514 #define MINSN3OP_0BL  (MASK_32BIT (~(FIELDF | FIELDB (63))))
 515 #define MINSN3OP_0LL  (MASK_32BIT (~(FIELDF)))
 516 #define MINSN3OP_ABU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 517 #define MINSN3OP_ALU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 518 #define MINSN3OP_0BU  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 519 #define MINSN3OP_0LU  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 520 #define MINSN3OP_BBS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 521 #define MINSN3OP_0LS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 522 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 523 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
 524 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 525 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
 526 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 527 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 528
 529 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 530 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 531 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 532 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 533 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 534 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 535
 536 #define MINSN2OP_BC  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 537 #define MINSN2OP_BL  (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
 538 #define MINSN2OP_0C  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 539 #define MINSN2OP_0L  (MASK_32BIT ((~(FIELDF))))
 540 #define MINSN2OP_BU  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 541 #define MINSN2OP_0U  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 542
 543 /* Various constants used when defining an extension instruction.  */
 544 #define ARC_SYNTAX_3OP          (1 << 0)
 545 #define ARC_SYNTAX_2OP          (1 << 1)
 546 #define ARC_SYNTAX_1OP          (1 << 2)
 547 #define ARC_SYNTAX_NOP          (1 << 3)
 548 #define ARC_SYNTAX_MASK         (0x0F)
 549
 550 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 551 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 552
 553 #define ARC_SUFFIX_NONE         (1 << 0)
 554 #define ARC_SUFFIX_COND         (1 << 1)
 555 #define ARC_SUFFIX_FLAG         (1 << 2)
 556
 557 #define ARC_REGISTER_READONLY    (1 << 0)
 558 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 559 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 560
 561 /* Constants needed to initialize extension instructions.  */
 562 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 563 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 564 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 565 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 566
 567 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 568 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 569 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 570 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 571 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 572 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 573 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 574 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 579
 580 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 581 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 582 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 583
 584 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 585 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 586 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 587
 588 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 589 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 590 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 591 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 592 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 594
 595 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 596 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 597 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 599
 600 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 601 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 603
 604 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 605    Instruction Set Reference Manual v2.4 for a description of address types.  */
 606
 607 typedef enum
 608 {
 609   /* Addresses in memory.  */
 610
 611   /* Buffer descriptor.  */
 612   ARC_NPS400_ADDRTYPE_BD,
 613
 614   /* Job identifier.  */
 615   ARC_NPS400_ADDRTYPE_JID,
 616
 617   /* Linked Buffer Descriptor.  */
 618   ARC_NPS400_ADDRTYPE_LBD,
 619
 620   /* Multicast Buffer Descriptor.  */
 621   ARC_NPS400_ADDRTYPE_MBD,
 622
 623   /* Summarized Address.  */
 624   ARC_NPS400_ADDRTYPE_SD,
 625
 626   /* SMEM Security Context Local Memory.  */
 627   ARC_NPS400_ADDRTYPE_SM,
 628
 629   /* Extended Address.  */
 630   ARC_NPS400_ADDRTYPE_XA,
 631
 632   /* Extended Summarized Address.  */
 633   ARC_NPS400_ADDRTYPE_XD,
 634
 635   /* CMEM offset addresses.  */
 636
 637   /* On-demand Counter Descriptor.  */
 638   ARC_NPS400_ADDRTYPE_CD,
 639
 640   /* CMEM Buffer Descriptor.  */
 641   ARC_NPS400_ADDRTYPE_CBD,
 642
 643   /* CMEM Job Identifier.  */
 644   ARC_NPS400_ADDRTYPE_CJID,
 645
 646   /* CMEM Linked Buffer Descriptor.  */
 647   ARC_NPS400_ADDRTYPE_CLBD,
 648
 649   /* CMEM Offset.  */
 650   ARC_NPS400_ADDRTYPE_CM,
 651
 652   /* CMEM Summarized Address.  */
 653   ARC_NPS400_ADDRTYPE_CSD,
 654
 655   /* CMEM Extended Address.  */
 656   ARC_NPS400_ADDRTYPE_CXA,
 657
 658   /* CMEM Extended Summarized Address.  */
 659   ARC_NPS400_ADDRTYPE_CXD
 660
 661 } arc_nps_address_type;
 662
 663 #define ARC_NUM_ADDRTYPES 16
 664
 665 #ifdef __cplusplus
 666 }
 667 #endif
 668
 669 #endif /* OPCODE_ARC_H */