include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2017 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        3
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BBIT0,
  46   BBIT1,
  47   BI,
  48   BIH,
  49   BITOP,
  50   BITSTREAM,
  51   BMU,
  52   BRANCH,
  53   BRCC,
  54   CONTROL,
  55   DIVREM,
  56   DPI,
  57   DSP,
  58   EI,
  59   ENTER,
  60   FLOAT,
  61   INVALID,
  62   JLI,
  63   JUMP,
  64   KERNEL,
  65   LEAVE,
  66   LOAD,
  67   LOGICAL,
  68   LOOP,
  69   MEMORY,
  70   MOVE,
  71   MPY,
  72   NET,
  73   PROTOCOL_DECODE,
  74   PMU,
  75   POP,
  76   PUSH,
  77   STORE,
  78   SUB,
  79   XY
  80 } insn_class_t;
  81
  82 /* Instruction Subclass.  */
  83 typedef enum
  84 {
  85   NONE,
  86   CVT,
  87   BTSCN,
  88   CD1,
  89   CD2,
  90   COND,
  91   DIV,
  92   DP,
  93   DPA,
  94   DPX,
  95   MPY1E,
  96   MPY6E,
  97   MPY7E,
  98   MPY8E,
  99   MPY9E,
 100   NPS400,
 101   QUARKSE,
 102   SHFT1,
 103   SHFT2,
 104   SWAP,
 105   SP,
 106   SPX
 107 } insn_subclass_t;
 108
 109 /* Flags class.  */
 110 typedef enum
 111 {
 112   F_CLASS_NONE = 0,
 113
 114   /* At most one flag from the set of flags can appear in the
 115      instruction.  */
 116   F_CLASS_OPTIONAL = (1 << 0),
 117
 118   /* Exactly one from from the set of flags must appear in the
 119      instruction.  */
 120   F_CLASS_REQUIRED = (1 << 1),
 121
 122   /* The conditional code can be extended over the standard variants
 123      via .extCondCode pseudo-op.  */
 124   F_CLASS_EXTEND = (1 << 2),
 125
 126   /* Condition code flag.  */
 127   F_CLASS_COND = (1 << 3),
 128
 129   /* Write back mode.  */
 130   F_CLASS_WB = (1 << 4),
 131
 132   /* Data size.  */
 133   F_CLASS_ZZ = (1 << 5),
 134
 135   /* Implicit flag.  */
 136   F_CLASS_IMPLICIT = (1 << 6)
 137 } flag_class_t;
 138
 139 /* The opcode table is an array of struct arc_opcode.  */
 140 struct arc_opcode
 141 {
 142   /* The opcode name.  */
 143   const char *name;
 144
 145   /* The opcode itself.  Those bits which will be filled in with
 146      operands are zeroes.  */
 147   unsigned long long opcode;
 148
 149   /* The opcode mask.  This is used by the disassembler.  This is a
 150      mask containing ones indicating those bits which must match the
 151      opcode field, and zeroes indicating those bits which need not
 152      match (and are presumably filled in by operands).  */
 153   unsigned long long mask;
 154
 155   /* One bit flags for the opcode.  These are primarily used to
 156      indicate specific processors and environments support the
 157      instructions.  The defined values are listed below.  */
 158   unsigned cpu;
 159
 160   /* The instruction class.  This is used by gdb.  */
 161   insn_class_t insn_class;
 162
 163   /* The instruction subclass.  */
 164   insn_subclass_t subclass;
 165
 166   /* An array of operand codes.  Each code is an index into the
 167      operand table.  They appear in the order which the operands must
 168      appear in assembly code, and are terminated by a zero.  */
 169   unsigned char operands[MAX_INSN_ARGS + 1];
 170
 171   /* An array of flag codes.  Each code is an index into the flag
 172      table.  They appear in the order which the flags must appear in
 173      assembly code, and are terminated by a zero.  */
 174   unsigned char flags[MAX_INSN_FLGS + 1];
 175 };
 176
 177 /* The table itself is sorted by major opcode number, and is otherwise
 178    in the order in which the disassembler should consider
 179    instructions.  */
 180 extern const struct arc_opcode arc_opcodes[];
 181
 182 /* Return length of an instruction represented by OPCODE, in bytes.  */
 183 extern int arc_opcode_len (const struct arc_opcode *opcode);
 184
 185 /* CPU Availability.  */
 186 #define ARC_OPCODE_NONE     0x0000
 187 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 188 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 189 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 190 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 191
 192 /* CPU combi.  */
 193 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 194                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 195 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 196 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 197
 198 /* CPU extensions.  */
 199 #define ARC_EA       0x0001
 200 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 201 #define ARC_LLOCK    0x0002
 202 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 203 #define ARC_MPY      0x0004
 204 #define ARC_MULT     0x0004
 205 #define ARC_NPS400   0x0008
 206
 207 /* Floating point support.  */
 208 #define ARC_DPFP     0x0010
 209 #define ARC_SPFP     0x0020
 210 #define ARC_FPU      0x0030
 211 #define ARC_FPUDA    0x0040
 212
 213 /* NORM & SWAP.  */
 214 #define ARC_SWAP     0x0100
 215 #define ARC_NORM     0x0200
 216 #define ARC_BSCAN    0x0200
 217
 218 /* A7 specific.  */
 219 #define ARC_UIX      0x1000
 220 #define ARC_TSTAMP   0x1000
 221
 222 /* A6 specific.  */
 223 #define ARC_VBFDW    0x1000
 224 #define ARC_BARREL   0x1000
 225 #define ARC_DSPA     0x1000
 226
 227 /* EM specific.  */
 228 #define ARC_SHIFT    0x1000
 229
 230 /* V2 specific.  */
 231 #define ARC_INTR     0x1000
 232 #define ARC_DIV      0x1000
 233
 234 /* V1 specific.  */
 235 #define ARC_XMAC     0x1000
 236 #define ARC_CRC      0x1000
 237
 238 /* The operands table is an array of struct arc_operand.  */
 239 struct arc_operand
 240 {
 241   /* The number of bits in the operand.  */
 242   unsigned int bits;
 243
 244   /* How far the operand is left shifted in the instruction.  */
 245   unsigned int shift;
 246
 247   /* The default relocation type for this operand.  */
 248   signed int default_reloc;
 249
 250   /* One bit syntax flags.  */
 251   unsigned int flags;
 252
 253   /* Insertion function.  This is used by the assembler.  To insert an
 254      operand value into an instruction, check this field.
 255
 256      If it is NULL, execute
 257          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 258      (i is the instruction which we are filling in, o is a pointer to
 259      this structure, and op is the opcode value; this assumes twos
 260      complement arithmetic).
 261
 262      If this field is not NULL, then simply call it with the
 263      instruction and the operand value.  It will return the new value
 264      of the instruction.  If the ERRMSG argument is not NULL, then if
 265      the operand value is illegal, *ERRMSG will be set to a warning
 266      string (the operand will be inserted in any case).  If the
 267      operand value is legal, *ERRMSG will be unchanged (most operands
 268      can accept any value).  */
 269   unsigned long long (*insert) (unsigned long long instruction,
 270                                 long long int op,
 271                                 const char **errmsg);
 272
 273   /* Extraction function.  This is used by the disassembler.  To
 274      extract this operand type from an instruction, check this field.
 275
 276      If it is NULL, compute
 277          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 278          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 279              && (op & (1 << (o->bits - 1))) != 0)
 280            op -= 1 << o->bits;
 281      (i is the instruction, o is a pointer to this structure, and op
 282      is the result; this assumes twos complement arithmetic).
 283
 284      If this field is not NULL, then simply call it with the
 285      instruction value.  It will return the value of the operand.  If
 286      the INVALID argument is not NULL, *INVALID will be set to
 287      TRUE if this operand type can not actually be extracted from
 288      this operand (i.e., the instruction does not match).  If the
 289      operand is valid, *INVALID will not be changed.  */
 290   long long int (*extract) (unsigned long long instruction,
 291                             bfd_boolean *invalid);
 292 };
 293
 294 /* Elements in the table are retrieved by indexing with values from
 295    the operands field of the arc_opcodes table.  */
 296 extern const struct arc_operand arc_operands[];
 297 extern const unsigned arc_num_operands;
 298 extern const unsigned arc_Toperand;
 299 extern const unsigned arc_NToperand;
 300
 301 /* Values defined for the flags field of a struct arc_operand.  */
 302
 303 /* This operand does not actually exist in the assembler input.  This
 304    is used to support extended mnemonics, for which two operands fields
 305    are identical.  The assembler should call the insert function with
 306    any op value.  The disassembler should call the extract function,
 307    ignore the return value, and check the value placed in the invalid
 308    argument.  */
 309 #define ARC_OPERAND_FAKE        0x0001
 310
 311 /* This operand names an integer register.  */
 312 #define ARC_OPERAND_IR          0x0002
 313
 314 /* This operand takes signed values.  */
 315 #define ARC_OPERAND_SIGNED      0x0004
 316
 317 /* This operand takes unsigned values.  This exists primarily so that
 318    a flags value of 0 can be treated as end-of-arguments.  */
 319 #define ARC_OPERAND_UNSIGNED    0x0008
 320
 321 /* This operand takes long immediate values.  */
 322 #define ARC_OPERAND_LIMM        0x0010
 323
 324 /* This operand is identical like the previous one.  */
 325 #define ARC_OPERAND_DUPLICATE   0x0020
 326
 327 /* This operand is PC relative.  Used for internal relocs.  */
 328 #define ARC_OPERAND_PCREL       0x0040
 329
 330 /* This operand is truncated.  The truncation is done accordingly to
 331    operand alignment attribute.  */
 332 #define ARC_OPERAND_TRUNCATE    0x0080
 333
 334 /* This operand is 16bit aligned.  */
 335 #define ARC_OPERAND_ALIGNED16   0x0100
 336
 337 /* This operand is 32bit aligned.  */
 338 #define ARC_OPERAND_ALIGNED32   0x0200
 339
 340 /* This operand can be ignored by matching process if it is not
 341    present.  */
 342 #define ARC_OPERAND_IGNORE      0x0400
 343
 344 /* Don't check the range when matching.  */
 345 #define ARC_OPERAND_NCHK        0x0800
 346
 347 /* Mark the braket possition.  */
 348 #define ARC_OPERAND_BRAKET      0x1000
 349
 350 /* Address type operand for NPS400.  */
 351 #define ARC_OPERAND_ADDRTYPE    0x2000
 352
 353 /* Mark the colon position.  */
 354 #define ARC_OPERAND_COLON       0x4000
 355
 356 /* Mask for selecting the type for typecheck purposes.  */
 357 #define ARC_OPERAND_TYPECHECK_MASK               \
 358   (ARC_OPERAND_IR                                \
 359    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 360    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 361    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 362
 363 /* Macro to determine if an operand is a fake operand.  */
 364 #define ARC_OPERAND_IS_FAKE(op)                     \
 365   ((operand->flags & ARC_OPERAND_FAKE)              \
 366    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 367         || (operand->flags & ARC_OPERAND_COLON)))
 368
 369 /* The flags structure.  */
 370 struct arc_flag_operand
 371 {
 372   /* The flag name.  */
 373   const char *name;
 374
 375   /* The flag code.  */
 376   unsigned code;
 377
 378   /* The number of bits in the operand.  */
 379   unsigned int bits;
 380
 381   /* How far the operand is left shifted in the instruction.  */
 382   unsigned int shift;
 383
 384   /* Available for disassembler.  */
 385   unsigned char favail;
 386 };
 387
 388 /* The flag operands table.  */
 389 extern const struct arc_flag_operand arc_flag_operands[];
 390 extern const unsigned arc_num_flag_operands;
 391
 392 /* The flag's class structure.  */
 393 struct arc_flag_class
 394 {
 395   /* Flag class.  */
 396   flag_class_t flag_class;
 397
 398   /* List of valid flags (codes).  */
 399   unsigned flags[256];
 400 };
 401
 402 extern const struct arc_flag_class arc_flag_classes[];
 403
 404 /* Structure for special cases.  */
 405 struct arc_flag_special
 406 {
 407   /* Name of special case instruction.  */
 408   const char *name;
 409
 410   /* List of flags applicable for special case instruction.  */
 411   unsigned flags[32];
 412 };
 413
 414 extern const struct arc_flag_special arc_flag_special_cases[];
 415 extern const unsigned arc_num_flag_special;
 416
 417 /* Relocation equivalence structure.  */
 418 struct arc_reloc_equiv_tab
 419 {
 420   const char * name;       /* String to lookup.  */
 421   const char * mnemonic;   /* Extra matching condition.  */
 422   unsigned     flags[32];  /* Extra matching condition.  */
 423   signed int   oldreloc;   /* Old relocation.  */
 424   signed int   newreloc;   /* New relocation.  */
 425 };
 426
 427 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 428 extern const unsigned arc_num_equiv_tab;
 429
 430 /* Structure for operand operations for pseudo/alias instructions.  */
 431 struct arc_operand_operation
 432 {
 433   /* The index for operand from operand array.  */
 434   unsigned operand_idx;
 435
 436   /* Defines if it needs the operand inserted by the assembler or
 437      whether this operand comes from the pseudo instruction's
 438      operands.  */
 439   unsigned char needs_insert;
 440
 441   /* Count we have to add to the operand.  Use negative number to
 442      subtract from the operand.  Also use this number to add to 0 if
 443      the operand needs to be inserted (i.e. needs_insert == 1).  */
 444   int count;
 445
 446   /* Index of the operand to swap with.  To be done AFTER applying
 447      inc_count.  */
 448   unsigned swap_operand_idx;
 449 };
 450
 451 /* Structure for pseudo/alias instructions.  */
 452 struct arc_pseudo_insn
 453 {
 454   /* Mnemonic for pseudo/alias insn.  */
 455   const char *mnemonic_p;
 456
 457   /* Mnemonic for real instruction.  */
 458   const char *mnemonic_r;
 459
 460   /* Flag that will have to be added (if any).  */
 461   const char *flag_r;
 462
 463   /* Amount of operands.  */
 464   unsigned operand_cnt;
 465
 466   /* Array of operand operations.  */
 467   struct arc_operand_operation operand[6];
 468 };
 469
 470 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 471 extern const unsigned arc_num_pseudo_insn;
 472
 473 /* Structure for AUXILIARY registers.  */
 474 struct arc_aux_reg
 475 {
 476   /* Register address.  */
 477   int address;
 478
 479   /* One bit flags for the opcode.  These are primarily used to
 480      indicate specific processors and environments support the
 481      instructions.  */
 482   unsigned cpu;
 483
 484   /* AUX register subclass.  */
 485   insn_subclass_t subclass;
 486
 487   /* Register name.  */
 488   const char *name;
 489
 490   /* Size of the string.  */
 491   size_t length;
 492 };
 493
 494 extern const struct arc_aux_reg arc_aux_regs[];
 495 extern const unsigned arc_num_aux_regs;
 496
 497 extern const struct arc_opcode arc_relax_opcodes[];
 498 extern const unsigned arc_num_relax_opcodes;
 499
 500 /* Macro used for generating one class of NPS instructions.  */
 501 #define NPS_CMEM_HIGH_VALUE 0x57f0
 502
 503 /* Macros to help generating regular pattern instructions.  */
 504 #define FIELDA(word) (word & 0x3F)
 505 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 506 #define FIELDC(word) ((word & 0x3F) << 6)
 507 #define FIELDF       (0x01 << 15)
 508 #define FIELDQ       (0x1F)
 509
 510 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 511 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 512 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 513
 514 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 515 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 516 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 517 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 518 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 519 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 520 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 521 #define INSN3OP_0LL(MOP,SOP)                                    \
 522   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 523 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 524 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 525 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 526 #define INSN3OP_0LU(MOP,SOP)                                    \
 527   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 528 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 529 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 530 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 531 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 532 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 533 #define INSN3OP_C0LL(MOP,SOP)                                   \
 534   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 535 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 536 #define INSN3OP_C0LU(MOP,SOP)                                   \
 537   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 538
 539 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
 540
 541 #define MINSN3OP_ABC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 542 #define MINSN3OP_ALC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 543 #define MINSN3OP_ABL  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
 544 #define MINSN3OP_ALL  (MASK_32BIT (~(FIELDF | FIELDA (63))))
 545 #define MINSN3OP_0BC  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 546 #define MINSN3OP_0LC  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 547 #define MINSN3OP_0BL  (MASK_32BIT (~(FIELDF | FIELDB (63))))
 548 #define MINSN3OP_0LL  (MASK_32BIT (~(FIELDF)))
 549 #define MINSN3OP_ABU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 550 #define MINSN3OP_ALU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 551 #define MINSN3OP_0BU  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 552 #define MINSN3OP_0LU  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 553 #define MINSN3OP_BBS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 554 #define MINSN3OP_0LS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 555 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 556 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
 557 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 558 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
 559 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 560 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 561
 562 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 563 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 564 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 565 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 566 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 567 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 568
 569 #define MINSN2OP_BC  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 570 #define MINSN2OP_BL  (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
 571 #define MINSN2OP_0C  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 572 #define MINSN2OP_0L  (MASK_32BIT ((~(FIELDF))))
 573 #define MINSN2OP_BU  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 574 #define MINSN2OP_0U  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 575
 576 /* Various constants used when defining an extension instruction.  */
 577 #define ARC_SYNTAX_3OP          (1 << 0)
 578 #define ARC_SYNTAX_2OP          (1 << 1)
 579 #define ARC_SYNTAX_1OP          (1 << 2)
 580 #define ARC_SYNTAX_NOP          (1 << 3)
 581 #define ARC_SYNTAX_MASK         (0x0F)
 582
 583 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 584 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 585
 586 #define ARC_SUFFIX_NONE         (1 << 0)
 587 #define ARC_SUFFIX_COND         (1 << 1)
 588 #define ARC_SUFFIX_FLAG         (1 << 2)
 589
 590 #define ARC_REGISTER_READONLY    (1 << 0)
 591 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 592 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 593
 594 /* Constants needed to initialize extension instructions.  */
 595 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 596 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 597 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 598 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 599
 600 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 601 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 604 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 605 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 606 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 607 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 608 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 609 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 610 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 611 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 612
 613 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 614 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 615 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 616
 617 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 618 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 619 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 620
 621 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 622 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 623 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 624 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 625 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 626 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 627
 628 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 629 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 630 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 631 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 632
 633 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 634 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 635 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 636
 637 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 638    Instruction Set Reference Manual v2.4 for a description of address types.  */
 639
 640 typedef enum
 641 {
 642   /* Addresses in memory.  */
 643
 644   /* Buffer descriptor.  */
 645   ARC_NPS400_ADDRTYPE_BD,
 646
 647   /* Job identifier.  */
 648   ARC_NPS400_ADDRTYPE_JID,
 649
 650   /* Linked Buffer Descriptor.  */
 651   ARC_NPS400_ADDRTYPE_LBD,
 652
 653   /* Multicast Buffer Descriptor.  */
 654   ARC_NPS400_ADDRTYPE_MBD,
 655
 656   /* Summarized Address.  */
 657   ARC_NPS400_ADDRTYPE_SD,
 658
 659   /* SMEM Security Context Local Memory.  */
 660   ARC_NPS400_ADDRTYPE_SM,
 661
 662   /* Extended Address.  */
 663   ARC_NPS400_ADDRTYPE_XA,
 664
 665   /* Extended Summarized Address.  */
 666   ARC_NPS400_ADDRTYPE_XD,
 667
 668   /* CMEM offset addresses.  */
 669
 670   /* On-demand Counter Descriptor.  */
 671   ARC_NPS400_ADDRTYPE_CD,
 672
 673   /* CMEM Buffer Descriptor.  */
 674   ARC_NPS400_ADDRTYPE_CBD,
 675
 676   /* CMEM Job Identifier.  */
 677   ARC_NPS400_ADDRTYPE_CJID,
 678
 679   /* CMEM Linked Buffer Descriptor.  */
 680   ARC_NPS400_ADDRTYPE_CLBD,
 681
 682   /* CMEM Offset.  */
 683   ARC_NPS400_ADDRTYPE_CM,
 684
 685   /* CMEM Summarized Address.  */
 686   ARC_NPS400_ADDRTYPE_CSD,
 687
 688   /* CMEM Extended Address.  */
 689   ARC_NPS400_ADDRTYPE_CXA,
 690
 691   /* CMEM Extended Summarized Address.  */
 692   ARC_NPS400_ADDRTYPE_CXD
 693
 694 } arc_nps_address_type;
 695
 696 #define ARC_NUM_ADDRTYPES 16
 697
 698 #ifdef __cplusplus
 699 }
 700 #endif
 701
 702 #endif /* OPCODE_ARC_H */