include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2016 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        3
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41   {
  42     ACL,
  43     ARITH,
  44     AUXREG,
  45     BITOP,
  46     BRANCH,
  47     CONTROL,
  48     DPI,
  49     DSP,
  50     FLOAT,
  51     INVALID,
  52     JUMP,
  53     KERNEL,
  54     LOGICAL,
  55     MEMORY,
  56     NET,
  57   } insn_class_t;
  58
  59 /* Instruction Subclass.  */
  60 typedef enum
  61   {
  62     NONE,
  63     CVT,
  64     BTSCN,
  65     CD1,
  66     CD2,
  67     COND,
  68     DIV,
  69     DP,
  70     DPA,
  71     DPX,
  72     MPY1E,
  73     MPY6E,
  74     MPY7E,
  75     MPY8E,
  76     MPY9E,
  77     NPS400,
  78     QUARKSE,
  79     SHFT1,
  80     SHFT2,
  81     SWAP,
  82     SP,
  83     SPX
  84   } insn_subclass_t;
  85
  86 /* Flags class.  */
  87 typedef enum
  88   {
  89     F_CLASS_NONE = 0,
  90
  91     /* At most one flag from the set of flags can appear in the
  92        instruction.  */
  93     F_CLASS_OPTIONAL = (1 << 0),
  94
  95     /* Exactly one from from the set of flags must appear in the
  96        instruction.  */
  97     F_CLASS_REQUIRED = (1 << 1),
  98
  99     /* The conditional code can be extended over the standard variants
 100        via .extCondCode pseudo-op.  */
 101     F_CLASS_EXTEND = (1 << 2),
 102
 103     /* Condition code flag.  */
 104     F_CLASS_COND = (1 << 3)
 105   } flag_class_t;
 106
 107 /* The opcode table is an array of struct arc_opcode.  */
 108 struct arc_opcode
 109 {
 110   /* The opcode name.  */
 111   const char *name;
 112
 113   /* The opcode itself.  Those bits which will be filled in with
 114      operands are zeroes.  */
 115   unsigned opcode;
 116
 117   /* The opcode mask.  This is used by the disassembler.  This is a
 118      mask containing ones indicating those bits which must match the
 119      opcode field, and zeroes indicating those bits which need not
 120      match (and are presumably filled in by operands).  */
 121   unsigned mask;
 122
 123   /* One bit flags for the opcode.  These are primarily used to
 124      indicate specific processors and environments support the
 125      instructions.  The defined values are listed below.  */
 126   unsigned cpu;
 127
 128   /* The instruction class.  This is used by gdb.  */
 129   insn_class_t insn_class;
 130
 131   /* The instruction subclass.  */
 132   insn_subclass_t subclass;
 133
 134   /* An array of operand codes.  Each code is an index into the
 135      operand table.  They appear in the order which the operands must
 136      appear in assembly code, and are terminated by a zero.  */
 137   unsigned char operands[MAX_INSN_ARGS + 1];
 138
 139   /* An array of flag codes.  Each code is an index into the flag
 140      table.  They appear in the order which the flags must appear in
 141      assembly code, and are terminated by a zero.  */
 142   unsigned char flags[MAX_INSN_FLGS + 1];
 143 };
 144
 145 /* Structure used to describe 48 and 64 bit instructions.  */
 146 struct arc_long_opcode
 147 {
 148   /* The base instruction is either 16 or 32 bits, and is described like a
 149      normal instruction.  */
 150   struct arc_opcode base_opcode;
 151
 152   /* The template value for the 32-bit LIMM extension.  Used by the
 153      assembler and disassembler in the same way as the 'opcode' field of
 154      'struct arc_opcode'.  */
 155   unsigned limm_template;
 156
 157   /* The mask value for the 32-bit LIMM extension.  Used by the
 158      disassembler just like the 'mask' field in 'struct arc_opcode'.  */
 159   unsigned limm_mask;
 160
 161   /* Array of operand codes similar to the 'operands' array in 'struct
 162      arc_opcode'.  These operands are used to fill in the LIMM value.  */
 163   unsigned char operands[MAX_INSN_ARGS + 1];
 164 };
 165
 166 extern const struct arc_long_opcode arc_long_opcodes[];
 167 extern const unsigned arc_num_long_opcodes;
 168
 169 /* The table itself is sorted by major opcode number, and is otherwise
 170    in the order in which the disassembler should consider
 171    instructions.  */
 172 extern const struct arc_opcode arc_opcodes[];
 173
 174 /* CPU Availability.  */
 175 #define ARC_OPCODE_NONE     0x0000
 176 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 177 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 178 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 179 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 180
 181 /* CPU combi.  */
 182 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 183                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 184 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 185
 186 /* CPU extensions.  */
 187 #define ARC_EA       0x0001
 188 #define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
 189 #define ARC_LLOCK    0x0002
 190 #define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
 191 #define ARC_MPY      0x0004
 192 #define ARC_MULT     0x0004
 193 #define ARC_NPS400   0x0008
 194
 195 /* Floating point support.  */
 196 #define ARC_DPFP     0x0010
 197 #define ARC_SPFP     0x0020
 198 #define ARC_FPU      0x0030
 199 #define ARC_FPUDA    0x0040
 200
 201 /* NORM & SWAP.  */
 202 #define ARC_SWAP     0x0100
 203 #define ARC_NORM     0x0200
 204 #define ARC_BSCAN    0x0200
 205
 206 /* A7 specific.  */
 207 #define ARC_UIX      0x1000
 208 #define ARC_TSTAMP   0x1000
 209
 210 /* A6 specific.  */
 211 #define ARC_VBFDW    0x1000
 212 #define ARC_BARREL   0x1000
 213 #define ARC_DSPA     0x1000
 214
 215 /* EM specific.  */
 216 #define ARC_SHIFT    0x1000
 217
 218 /* V2 specific.  */
 219 #define ARC_INTR     0x1000
 220 #define ARC_DIV      0x1000
 221
 222 /* V1 specific.  */
 223 #define ARC_XMAC     0x1000
 224 #define ARC_CRC      0x1000
 225
 226 /* A macro to check for short instructions.  */
 227 #define ARC_SHORT(mask)                         \
 228   (((mask) & 0xFFFF0000) ? 0 : 1)
 229
 230 /* The operands table is an array of struct arc_operand.  */
 231 struct arc_operand
 232 {
 233   /* The number of bits in the operand.  */
 234   unsigned int bits;
 235
 236   /* How far the operand is left shifted in the instruction.  */
 237   unsigned int shift;
 238
 239   /* The default relocation type for this operand.  */
 240   signed int default_reloc;
 241
 242   /* One bit syntax flags.  */
 243   unsigned int flags;
 244
 245   /* Insertion function.  This is used by the assembler.  To insert an
 246      operand value into an instruction, check this field.
 247
 248      If it is NULL, execute
 249          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 250      (i is the instruction which we are filling in, o is a pointer to
 251      this structure, and op is the opcode value; this assumes twos
 252      complement arithmetic).
 253
 254      If this field is not NULL, then simply call it with the
 255      instruction and the operand value.  It will return the new value
 256      of the instruction.  If the ERRMSG argument is not NULL, then if
 257      the operand value is illegal, *ERRMSG will be set to a warning
 258      string (the operand will be inserted in any case).  If the
 259      operand value is legal, *ERRMSG will be unchanged (most operands
 260      can accept any value).  */
 261   unsigned (*insert) (unsigned instruction, int op, const char **errmsg);
 262
 263   /* Extraction function.  This is used by the disassembler.  To
 264      extract this operand type from an instruction, check this field.
 265
 266      If it is NULL, compute
 267          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 268          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 269              && (op & (1 << (o->bits - 1))) != 0)
 270            op -= 1 << o->bits;
 271      (i is the instruction, o is a pointer to this structure, and op
 272      is the result; this assumes twos complement arithmetic).
 273
 274      If this field is not NULL, then simply call it with the
 275      instruction value.  It will return the value of the operand.  If
 276      the INVALID argument is not NULL, *INVALID will be set to
 277      TRUE if this operand type can not actually be extracted from
 278      this operand (i.e., the instruction does not match).  If the
 279      operand is valid, *INVALID will not be changed.  */
 280   int (*extract) (unsigned instruction, bfd_boolean *invalid);
 281 };
 282
 283 /* Elements in the table are retrieved by indexing with values from
 284    the operands field of the arc_opcodes table.  */
 285 extern const struct arc_operand arc_operands[];
 286 extern const unsigned arc_num_operands;
 287 extern const unsigned arc_Toperand;
 288 extern const unsigned arc_NToperand;
 289
 290 /* Values defined for the flags field of a struct arc_operand.  */
 291
 292 /* This operand does not actually exist in the assembler input.  This
 293    is used to support extended mnemonics, for which two operands fields
 294    are identical.  The assembler should call the insert function with
 295    any op value.  The disassembler should call the extract function,
 296    ignore the return value, and check the value placed in the invalid
 297    argument.  */
 298 #define ARC_OPERAND_FAKE        0x0001
 299
 300 /* This operand names an integer register.  */
 301 #define ARC_OPERAND_IR          0x0002
 302
 303 /* This operand takes signed values.  */
 304 #define ARC_OPERAND_SIGNED      0x0004
 305
 306 /* This operand takes unsigned values.  This exists primarily so that
 307    a flags value of 0 can be treated as end-of-arguments.  */
 308 #define ARC_OPERAND_UNSIGNED    0x0008
 309
 310 /* This operand takes long immediate values.  */
 311 #define ARC_OPERAND_LIMM        0x0010
 312
 313 /* This operand is identical like the previous one.  */
 314 #define ARC_OPERAND_DUPLICATE   0x0020
 315
 316 /* This operand is PC relative.  Used for internal relocs.  */
 317 #define ARC_OPERAND_PCREL       0x0040
 318
 319 /* This operand is truncated.  The truncation is done accordingly to
 320    operand alignment attribute.  */
 321 #define ARC_OPERAND_TRUNCATE    0x0080
 322
 323 /* This operand is 16bit aligned.  */
 324 #define ARC_OPERAND_ALIGNED16   0x0100
 325
 326 /* This operand is 32bit aligned.  */
 327 #define ARC_OPERAND_ALIGNED32   0x0200
 328
 329 /* This operand can be ignored by matching process if it is not
 330    present.  */
 331 #define ARC_OPERAND_IGNORE      0x0400
 332
 333 /* Don't check the range when matching.  */
 334 #define ARC_OPERAND_NCHK        0x0800
 335
 336 /* Mark the braket possition.  */
 337 #define ARC_OPERAND_BRAKET      0x1000
 338
 339 /* Mask for selecting the type for typecheck purposes.  */
 340 #define ARC_OPERAND_TYPECHECK_MASK              \
 341   (ARC_OPERAND_IR |                             \
 342    ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED |      \
 343    ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)
 344
 345 /* The flags structure.  */
 346 struct arc_flag_operand
 347 {
 348   /* The flag name.  */
 349   const char *name;
 350
 351   /* The flag code.  */
 352   unsigned code;
 353
 354   /* The number of bits in the operand.  */
 355   unsigned int bits;
 356
 357   /* How far the operand is left shifted in the instruction.  */
 358   unsigned int shift;
 359
 360   /* Available for disassembler.  */
 361   unsigned char favail;
 362 };
 363
 364 /* The flag operands table.  */
 365 extern const struct arc_flag_operand arc_flag_operands[];
 366 extern const unsigned arc_num_flag_operands;
 367
 368 /* The flag's class structure.  */
 369 struct arc_flag_class
 370 {
 371   /* Flag class.  */
 372   flag_class_t flag_class;
 373
 374   /* List of valid flags (codes).  */
 375   unsigned flags[256];
 376 };
 377
 378 extern const struct arc_flag_class arc_flag_classes[];
 379
 380 /* Structure for special cases.  */
 381 struct arc_flag_special
 382 {
 383   /* Name of special case instruction.  */
 384   const char *name;
 385
 386   /* List of flags applicable for special case instruction.  */
 387   unsigned flags[32];
 388 };
 389
 390 extern const struct arc_flag_special arc_flag_special_cases[];
 391 extern const unsigned arc_num_flag_special;
 392
 393 /* Relocation equivalence structure.  */
 394 struct arc_reloc_equiv_tab
 395 {
 396   const char * name;       /* String to lookup.  */
 397   const char * mnemonic;   /* Extra matching condition.  */
 398   unsigned     flags[32];  /* Extra matching condition.  */
 399   signed int   oldreloc;   /* Old relocation.  */
 400   signed int   newreloc;   /* New relocation.  */
 401 };
 402
 403 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 404 extern const unsigned arc_num_equiv_tab;
 405
 406 /* Structure for operand operations for pseudo/alias instructions.  */
 407 struct arc_operand_operation
 408 {
 409   /* The index for operand from operand array.  */
 410   unsigned operand_idx;
 411
 412   /* Defines if it needs the operand inserted by the assembler or
 413      whether this operand comes from the pseudo instruction's
 414      operands.  */
 415   unsigned char needs_insert;
 416
 417   /* Count we have to add to the operand.  Use negative number to
 418      subtract from the operand.  Also use this number to add to 0 if
 419      the operand needs to be inserted (i.e. needs_insert == 1).  */
 420   int count;
 421
 422   /* Index of the operand to swap with.  To be done AFTER applying
 423      inc_count.  */
 424   unsigned swap_operand_idx;
 425 };
 426
 427 /* Structure for pseudo/alias instructions.  */
 428 struct arc_pseudo_insn
 429 {
 430   /* Mnemonic for pseudo/alias insn.  */
 431   const char *mnemonic_p;
 432
 433   /* Mnemonic for real instruction.  */
 434   const char *mnemonic_r;
 435
 436   /* Flag that will have to be added (if any).  */
 437   const char *flag_r;
 438
 439   /* Amount of operands.  */
 440   unsigned operand_cnt;
 441
 442   /* Array of operand operations.  */
 443   struct arc_operand_operation operand[6];
 444 };
 445
 446 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 447 extern const unsigned arc_num_pseudo_insn;
 448
 449 /* Structure for AUXILIARY registers.  */
 450 struct arc_aux_reg
 451 {
 452   /* Register address.  */
 453   int address;
 454
 455   /* One bit flags for the opcode.  These are primarily used to
 456      indicate specific processors and environments support the
 457      instructions.  */
 458   unsigned cpu;
 459
 460   /* AUX register subclass.  */
 461   insn_subclass_t subclass;
 462
 463   /* Register name.  */
 464   const char *name;
 465
 466   /* Size of the string.  */
 467   size_t length;
 468 };
 469
 470 extern const struct arc_aux_reg arc_aux_regs[];
 471 extern const unsigned arc_num_aux_regs;
 472
 473 extern const struct arc_opcode arc_relax_opcodes[];
 474 extern const unsigned arc_num_relax_opcodes;
 475
 476 /* Macro used for generating one class of NPS instructions.  */
 477 #define NPS_CMEM_HIGH_VALUE 0x57f0
 478
 479 /* Macros to help generating regular pattern instructions.  */
 480 #define FIELDA(word) (word & 0x3F)
 481 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 482 #define FIELDC(word) ((word & 0x3F) << 6)
 483 #define FIELDF       (0x01 << 15)
 484 #define FIELDQ       (0x1F)
 485
 486 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 487 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 488 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 489
 490 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 491 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 492 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 493 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 494 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 495 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 496 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 497 #define INSN3OP_0LL(MOP,SOP)                                    \
 498   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 499 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 500 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 501 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 502 #define INSN3OP_0LU(MOP,SOP)                                    \
 503   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 504 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 505 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 506 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 507 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 508 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 509 #define INSN3OP_C0LL(MOP,SOP)                                   \
 510   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 511 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 512 #define INSN3OP_C0LU(MOP,SOP)                                   \
 513   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 514
 515 #define MINSN3OP_ABC  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 516 #define MINSN3OP_ALC  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 517 #define MINSN3OP_ABL  (~(FIELDF | FIELDA (63) | FIELDB (63)))
 518 #define MINSN3OP_ALL  (~(FIELDF | FIELDA (63)))
 519 #define MINSN3OP_0BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 520 #define MINSN3OP_0LC  (~(FIELDF | FIELDC (63)))
 521 #define MINSN3OP_0BL  (~(FIELDF | FIELDB (63)))
 522 #define MINSN3OP_0LL  (~(FIELDF))
 523 #define MINSN3OP_ABU  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 524 #define MINSN3OP_ALU  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 525 #define MINSN3OP_0BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 526 #define MINSN3OP_0LU  (~(FIELDF | FIELDC (63)))
 527 #define MINSN3OP_BBS  (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63)))
 528 #define MINSN3OP_0LS  (~(FIELDF | FIELDA (63) | FIELDC (63)))
 529 #define MINSN3OP_CBBC (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 530 #define MINSN3OP_CBBL (~(FIELDF | FIELDQ | FIELDB (63)))
 531 #define MINSN3OP_C0LC (~(FIELDF | FIELDQ | FIELDC (63)))
 532 #define MINSN3OP_C0LL (~(FIELDF | FIELDQ))
 533 #define MINSN3OP_CBBU (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63)))
 534 #define MINSN3OP_C0LU (~(FIELDF | FIELDQ | FIELDC (63)))
 535
 536 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 537 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 538 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 539 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 540 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 541 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 542
 543 #define MINSN2OP_BC  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 544 #define MINSN2OP_BL  (~(FIELDF | FIELDB (63)))
 545 #define MINSN2OP_0C  (~(FIELDF | FIELDC (63)))
 546 #define MINSN2OP_0L  (~(FIELDF))
 547 #define MINSN2OP_BU  (~(FIELDF | FIELDB (63) | FIELDC (63)))
 548 #define MINSN2OP_0U  (~(FIELDF | FIELDC (63)))
 549
 550 /* Various constants used when defining an extension instruction.  */
 551 #define ARC_SYNTAX_3OP          (1 << 0)
 552 #define ARC_SYNTAX_2OP          (1 << 1)
 553 #define ARC_SYNTAX_1OP          (1 << 2)
 554 #define ARC_SYNTAX_NOP          (1 << 3)
 555 #define ARC_SYNTAX_MASK         (0x0F)
 556
 557 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 558 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 559
 560 #define ARC_SUFFIX_NONE         (1 << 0)
 561 #define ARC_SUFFIX_COND         (1 << 1)
 562 #define ARC_SUFFIX_FLAG         (1 << 2)
 563
 564 #define ARC_REGISTER_READONLY    (1 << 0)
 565 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 566 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 567
 568 /* Constants needed to initialize extension instructions.  */
 569 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 570 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 571 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 572 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 573
 574 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 579 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 580 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 581 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 582 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 583 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 584 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 585 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 586
 587 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 588 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 589 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 590
 591 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 592 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 593 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 594
 595 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 596 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 597 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 599 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 600 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 601
 602 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 604 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 605 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 606
 607 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 608 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 609 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 610
 611 #ifdef __cplusplus
 612 }
 613 #endif
 614
 615 #endif /* OPCODE_ARC_H */