include/opcode/hppa.h

   1 /* Table of opcodes for the PA-RISC.
   2    Copyright (C) 1990, 1991, 1993, 1995, 1999 Free Software Foundation, Inc.
   3
   4    Contributed by the Center for Software Science at the
   5    University of Utah (pa-gdb-bugs@cs.utah.edu).
   6
   7 This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler.
   8
   9 GAS/GDB is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 1, or (at your option)
  12 any later version.
  13
  14 GAS/GDB is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with GAS or GDB; see the file COPYING.  If not, write to
  21 the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #if !defined(__STDC__) && !defined(const)
  24 #define const
  25 #endif
  26
  27 /*
  28  * Structure of an opcode table entry.
  29  */
  30
  31 /* There are two kinds of delay slot nullification: normal which is
  32  * controled by the nullification bit, and conditional, which depends
  33  * on the direction of the branch and its success or failure.
  34  *
  35  * NONE is unfortunately #defined in the hiux system include files.
  36  * #undef it away.
  37  */
  38 #undef NONE
  39 struct pa_opcode
  40 {
  41     const char *name;
  42     unsigned long int match;    /* Bits that must be set...  */
  43     unsigned long int mask;     /* ... in these bits. */
  44     char *args;
  45     enum pa_arch arch;
  46     char flags;
  47 };
  48
  49 /* Enable/disable strict syntax checking.  Not currently used, but will
  50    be necessary for PA2.0 support in the future.  */
  51 #define FLAG_STRICT 0x1
  52
  53 /*
  54    All hppa opcodes are 32 bits.
  55
  56    The match component is a mask saying which bits must match a
  57    particular opcode in order for an instruction to be an instance
  58    of that opcode.
  59
  60    The args component is a string containing one character for each operand of
  61    the instruction.  Characters used as a prefix allow any second character to
  62    be used without conflicting with the main operand characters.
  63
  64    Bit positions in this description follow HP usage of lsb = 31,
  65    "at" is lsb of field.
  66
  67    In the args field, the following characters must match exactly:
  68
  69         '+,() '
  70
  71    In the args field, the following characters are unused:
  72
  73         '  "#  &     -  /   34 6789:;< > @'
  74         ' BC      JKLM          XY [\]  '
  75         '   de gh   lm           y { } '
  76
  77    Here are all the characters:
  78
  79         ' !"#$%&'()*+-,./0123456789:;<=>?@'
  80         'ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_'
  81         'abcdefghijklmnopqrstuvwxyz{|}~'
  82
  83 Kinds of operands:
  84    x    integer register field at 15.
  85    b    integer register field at 10.
  86    t    integer register field at 31.
  87    a    integer register field at 10 and 15 (for PERMH)
  88    5    5 bit immediate at 15.
  89    s    2 bit space specifier at 17.
  90    S    3 bit space specifier at 18.
  91    V    5 bit immediate value at 31
  92    i    11 bit immediate value at 31
  93    j    14 bit immediate value at 31
  94    k    21 bit immediate value at 31
  95    n    nullification for branch instructions
  96    N    nullification for spop and copr instructions
  97    w    12 bit branch displacement
  98    W    17 bit branch displacement (PC relative)
  99    z    17 bit branch displacement (just a number, not an address)
 100
 101 Also these:
 102
 103    .    2 bit shift amount at 25
 104    *    4 bit shift amount at 25
 105    p    5 bit shift count at 26 (to support the SHD instruction) encoded as
 106         31-p
 107    ~    6 bit shift count at 20,22:26 encoded as 63-~.
 108    P    5 bit bit position at 26
 109    T    5 bit field length at 31 (encoded as 32-T)
 110    A    13 bit immediate at 18 (to support the BREAK instruction)
 111    ^    like b, but describes a control register
 112    !    sar (cr11) register
 113    D    26 bit immediate at 31 (to support the DIAG instruction)
 114    $    9 bit immediate at 28 (to support POPBTS)
 115
 116    v    3 bit Special Function Unit identifier at 25
 117    O    20 bit Special Function Unit operation split between 15 bits at 20
 118         and 5 bits at 31
 119    o    15 bit Special Function Unit operation at 20
 120    2    22 bit Special Function Unit operation split between 17 bits at 20
 121         and 5 bits at 31
 122    1    15 bit Special Function Unit operation split between 10 bits at 20
 123         and 5 bits at 31
 124    0    10 bit Special Function Unit operation split between 5 bits at 20
 125         and 5 bits at 31
 126    u    3 bit coprocessor unit identifier at 25
 127    F    Source Floating Point Operand Format Completer encoded 2 bits at 20
 128    I    Source Floating Point Operand Format Completer encoded 1 bits at 20
 129         (for 0xe format FP instructions)
 130    G    Destination Floating Point Operand Format Completer encoded 2 bits at 18
 131    H    Floating Point Operand Format at 26 for 'fmpyadd' and 'fmpysub'
 132         (very similar to 'F')
 133
 134    r    5 bit immediate value at 31 (for the break instruction)
 135         (very similar to V above, except the value is unsigned instead of
 136         low_sign_ext)
 137    R    5 bit immediate value at 15 (for the ssm, rsm, probei instructions)
 138         (same as r above, except the value is in a different location)
 139    U    10 bit immediate value at 15 (for SSM, RSM on pa2.0)
 140    Q    5 bit immediate value at 10 (a bit position specified in
 141         the bb instruction. It's the same as r above, except the
 142         value is in a different location)
 143    Z    %r1 -- implicit target of addil instruction.
 144
 145 Completer operands all have 'c' as the prefix:
 146
 147    cx   indexed load completer.
 148    cm   short load and store completer.
 149    cs   store bytes short completer.
 150
 151    cw   read/write completer for PROBE
 152    cW   wide completer for MFCTL
 153    cL   local processor completer for cache control
 154    cZ   System Control Completer (to support LPA, LHA, etc.)
 155
 156    ci   correction completer for DCOR
 157    ca   add completer
 158    cy   32 bit add carry completer
 159    cY   64 bit add carry completer
 160    cv   signed overflow trap completer
 161    ct   trap on condition completer for ADDI, SUB
 162    cT   trap on condition completer for UADDCM
 163    cb   32 bit borrow completer for SUB
 164    cB   64 bit borrow completer for SUB
 165
 166    ch   left/right half completer
 167    cH   signed/unsigned saturation completer
 168    cS   signed/unsigned completer at 21
 169    c*   permutation completer
 170
 171 Condition operands all have '?' as the prefix:
 172
 173    ?f   Floating point compare conditions (encoded as 5 bits at 31)
 174
 175    ?a   add conditions
 176    ?A   64 bit add conditions
 177    ?@   add branch conditions followed by nullify
 178    ?d   non-negated add branch conditions
 179    ?D   negated add branch conditions
 180    ?w   wide mode non-negated add branch conditions
 181    ?W   wide mode negated add branch conditions
 182
 183    ?s   compare/subtract conditions
 184    ?S   64 bit compare/subtract conditions
 185    ?t   non-negated compare conditions
 186    ?T   negated compare conditions
 187    ?r   64 bit non-negated compare conditions
 188    ?R   64 bit negated compare conditions
 189    ?Q   64 bit compare conditions for CMPIB instruction
 190    ?n   compare conditions followed by nullify
 191
 192    ?l   logical conditions
 193    ?L   64 bit logical conditions
 194
 195    ?b   branch on bit conditions
 196    ?B   64 bit branch on bit conditions
 197
 198    ?x   shift/extract/deposit conditions
 199    ?X   64 bit shift/extract/deposit conditions
 200    ?y   shift/extract/deposit conditions followed by nullify for conditional
 201         branches
 202
 203    ?u   unit conditions
 204    ?U   64 bit unit conditions
 205
 206 Floating point registers all have 'f' as a prefix:
 207
 208    ft   target register at 31
 209    fT   target register with L/R halves at 31
 210    fa   operand 1 register at 10
 211    fA   operand 1 register with L/R halves at 10
 212    fX   Same as fA, except prints a space before register during disasm
 213    fb   operand 2 register at 15
 214    fB   operand 2 register with L/R halves at 15
 215    fC   operand 3 register with L/R halves at 16:18,21:23
 216
 217 Float registers for fmpyadd and fmpysub:
 218
 219    fi   mult operand 1 register at 10
 220    fj   mult operand 2 register at 15
 221    fk   mult target register at 20
 222    fl   add/sub operand register at 25
 223    fm   add/sub target register at 31
 224
 225 */
 226
 227
 228 /* List of characters not to put a space after.  Note that
 229    "," is included, as the "spopN" operations use literal
 230    commas in their completer sections. */
 231 static const char *const completer_chars = ",CcY<>?!@+&U~FfGHINnOoZMadu|/=0123%e$m}";
 232
 233 /* The order of the opcodes in this table is significant:
 234
 235    * The assembler requires that all instances of the same mnemonic must be
 236    consecutive.  If they aren't, the assembler will bomb at runtime.
 237
 238    * The disassembler should not care about the order of the opcodes.  */
 239
 240 static const struct pa_opcode pa_opcodes[] =
 241 {
 242
 243
 244 /* pseudo-instructions */
 245
 246 { "b",          0xe8000000, 0xffe0e000, "nW", pa10}, /* bl foo,r0 */
 247 { "ldi",        0x34000000, 0xffe0c000, "j,x", pa10},   /* ldo val(r0),r */
 248 { "comib",      0x84000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 249 /* This entry is for the disassembler only.  It will never be used by
 250    assembler.  */
 251 { "comib",      0x8c000000, 0xfc000000, "?nn5,b,w", pa10}, /* comib{tf}*/
 252 { "comb",       0x80000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 253 /* This entry is for the disassembler only.  It will never be used by
 254    assembler.  */
 255 { "comb",       0x88000000, 0xfc000000, "?nnx,b,w", pa10}, /* comb{tf} */
 256 { "addb",       0xa0000000, 0xfc000000, "?@nx,b,w", pa10}, /* addb{tf} */
 257 /* This entry is for the disassembler only.  It will never be used by
 258    assembler.  */
 259 { "addb",       0xa8000000, 0xfc000000, "?@nx,b,w", pa10},
 260 { "addib",      0xa4000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 261 /* This entry is for the disassembler only.  It will never be used by
 262    assembler.  */
 263 { "addib",      0xac000000, 0xfc000000, "?@n5,b,w", pa10}, /* addib{tf}*/
 264 { "nop",        0x08000240, 0xffffffff, "", pa10},      /* or 0,0,0 */
 265 { "copy",       0x08000240, 0xffe0ffe0, "x,t", pa10},   /* or r,0,t */
 266 { "mtsar",      0x01601840, 0xffe0ffff, "x", pa10}, /* mtctl r,cr11 */
 267
 268 /* Loads and Stores for integer registers.  */
 269 { "ldd",        0x0c0000c0, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT},
 270 { "ldd",        0x0c0000c0, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT},
 271 { "ldd",        0x0c0010c0, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT},
 272 { "ldd",        0x0c0010c0, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT},
 273 { "ldw",        0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 274 { "ldw",        0x0c000080, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 275 { "ldw",        0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 276 { "ldw",        0x0c001080, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 277 { "ldw",        0x48000000, 0xfc000000, "j(s,b),x", pa10},
 278 { "ldw",        0x48000000, 0xfc000000, "j(b),x", pa10},
 279 { "ldh",        0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 280 { "ldh",        0x0c000040, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 281 { "ldh",        0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 282 { "ldh",        0x0c001040, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 283 { "ldh",        0x44000000, 0xfc000000, "j(s,b),x", pa10},
 284 { "ldh",        0x44000000, 0xfc000000, "j(b),x", pa10},
 285 { "ldb",        0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 286 { "ldb",        0x0c000000, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 287 { "ldb",        0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 288 { "ldb",        0x0c001000, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 289 { "ldb",        0x40000000, 0xfc000000, "j(s,b),x", pa10},
 290 { "ldb",        0x40000000, 0xfc000000, "j(b),x", pa10},
 291 { "std",        0x0c0012c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT},
 292 { "std",        0x0c0012c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT},
 293 { "stw",        0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 294 { "stw",        0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 295 { "stw",        0x68000000, 0xfc000000, "x,j(s,b)", pa10},
 296 { "stw",        0x68000000, 0xfc000000, "x,j(b)", pa10},
 297 { "sth",        0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 298 { "sth",        0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 299 { "sth",        0x64000000, 0xfc000000, "x,j(s,b)", pa10},
 300 { "sth",        0x64000000, 0xfc000000, "x,j(b)", pa10},
 301 { "stb",        0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10, FLAG_STRICT},
 302 { "stb",        0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10, FLAG_STRICT},
 303 { "stb",        0x60000000, 0xfc000000, "x,j(s,b)", pa10},
 304 { "stb",        0x60000000, 0xfc000000, "x,j(b)", pa10},
 305 { "ldwm",       0x4c000000, 0xfc000000, "j(s,b),x", pa10},
 306 { "ldwm",       0x4c000000, 0xfc000000, "j(b),x", pa10},
 307 { "stwm",       0x6c000000, 0xfc000000, "x,j(s,b)", pa10},
 308 { "stwm",       0x6c000000, 0xfc000000, "x,j(b)", pa10},
 309 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(s,b),t", pa10},
 310 { "ldwx",       0x0c000080, 0xfc001fc0, "cxx(b),t", pa10},
 311 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(s,b),t", pa10},
 312 { "ldhx",       0x0c000040, 0xfc001fc0, "cxx(b),t", pa10},
 313 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(s,b),t", pa10},
 314 { "ldbx",       0x0c000000, 0xfc001fc0, "cxx(b),t", pa10},
 315 { "ldwa",       0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10, FLAG_STRICT},
 316 { "ldwa",       0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10, FLAG_STRICT},
 317 { "ldcw",       0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10, FLAG_STRICT},
 318 { "ldcw",       0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10, FLAG_STRICT},
 319 { "ldcw",       0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10, FLAG_STRICT},
 320 { "ldcw",       0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10, FLAG_STRICT},
 321 { "stwa",       0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10, FLAG_STRICT},
 322 { "stby",       0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10, FLAG_STRICT},
 323 { "stby",       0x0c001300, 0xfc001fc0, "csx,V(b)", pa10, FLAG_STRICT},
 324 { "ldda",       0x0c000100, 0xfc00dfc0, "cxx(b),t", pa20, FLAG_STRICT},
 325 { "ldda",       0x0c001100, 0xfc00dfc0, "cm5(b),t", pa20, FLAG_STRICT},
 326 { "ldcd",       0x0c000140, 0xfc001fc0, "cxx(s,b),t", pa20, FLAG_STRICT},
 327 { "ldcd",       0x0c000140, 0xfc001fc0, "cxx(b),t", pa20, FLAG_STRICT},
 328 { "ldcd",       0x0c001140, 0xfc001fc0, "cm5(s,b),t", pa20, FLAG_STRICT},
 329 { "ldcd",       0x0c001140, 0xfc001fc0, "cm5(b),t", pa20, FLAG_STRICT},
 330 { "stda",       0x0c0013c0, 0xfc001fc0, "cmx,V(s,b)", pa20, FLAG_STRICT},
 331 { "stda",       0x0c0013c0, 0xfc001fc0, "cmx,V(b)", pa20, FLAG_STRICT},
 332 { "ldwax",      0x0c000180, 0xfc00dfc0, "cxx(b),t", pa10},
 333 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(s,b),t", pa10},
 334 { "ldcwx",      0x0c0001c0, 0xfc001fc0, "cxx(b),t", pa10},
 335 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(s,b),t", pa10},
 336 { "ldws",       0x0c001080, 0xfc001fc0, "cm5(b),t", pa10},
 337 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(s,b),t", pa10},
 338 { "ldhs",       0x0c001040, 0xfc001fc0, "cm5(b),t", pa10},
 339 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(s,b),t", pa10},
 340 { "ldbs",       0x0c001000, 0xfc001fc0, "cm5(b),t", pa10},
 341 { "ldwas",      0x0c001180, 0xfc00dfc0, "cm5(b),t", pa10},
 342 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(s,b),t", pa10},
 343 { "ldcws",      0x0c0011c0, 0xfc001fc0, "cm5(b),t", pa10},
 344 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(s,b)", pa10},
 345 { "stws",       0x0c001280, 0xfc001fc0, "cmx,V(b)", pa10},
 346 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(s,b)", pa10},
 347 { "sths",       0x0c001240, 0xfc001fc0, "cmx,V(b)", pa10},
 348 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(s,b)", pa10},
 349 { "stbs",       0x0c001200, 0xfc001fc0, "cmx,V(b)", pa10},
 350 { "stwas",      0x0c001380, 0xfc00dfc0, "cmx,V(b)", pa10},
 351 { "stdby",      0x0c001340, 0xfc001fc0, "csx,V(s,b)", pa20, FLAG_STRICT},
 352 { "stdby",      0x0c001340, 0xfc001fc0, "csx,V(b)", pa20, FLAG_STRICT},
 353 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(s,b)", pa10},
 354 { "stbys",      0x0c001300, 0xfc001fc0, "csx,V(b)", pa10},
 355
 356 /* Immediate instructions.  */
 357 { "ldo",        0x34000000, 0xfc00c000, "j(b),x", pa10},
 358 { "ldil",       0x20000000, 0xfc000000, "k,b", pa10},
 359 { "addil",      0x28000000, 0xfc000000, "k,b,Z", pa10},
 360 { "addil",      0x28000000, 0xfc000000, "k,b", pa10},
 361
 362 /* Branching instructions. */
 363 { "bl",         0xe8000000, 0xfc00e000, "nW,b", pa10},
 364 { "gate",       0xe8002000, 0xfc00e000, "nW,b", pa10},
 365 { "blr",        0xe8004000, 0xfc00e001, "nx,b", pa10},
 366 { "bv",         0xe800c000, 0xfc00fffd, "nx(b)", pa10},
 367 { "bv",         0xe800c000, 0xfc00fffd, "n(b)", pa10},
 368 { "be",         0xe0000000, 0xfc000000, "nz(S,b)", pa10},
 369 { "ble",        0xe4000000, 0xfc000000, "nz(S,b)", pa10},
 370 { "movb",       0xc8000000, 0xfc000000, "?ynx,b,w", pa10},
 371 { "movib",      0xcc000000, 0xfc000000, "?yn5,b,w", pa10},
 372 { "combt",      0x80000000, 0xfc000000, "?tnx,b,w", pa10},
 373 { "combf",      0x88000000, 0xfc000000, "?tnx,b,w", pa10},
 374 { "comibt",     0x84000000, 0xfc000000, "?tn5,b,w", pa10},
 375 { "comibf",     0x8c000000, 0xfc000000, "?tn5,b,w", pa10},
 376 { "addbt",      0xa0000000, 0xfc000000, "?dnx,b,w", pa10},
 377 { "addbf",      0xa8000000, 0xfc000000, "?dnx,b,w", pa10},
 378 { "addibt",     0xa4000000, 0xfc000000, "?dn5,b,w", pa10},
 379 { "addibf",     0xac000000, 0xfc000000, "?dn5,b,w", pa10},
 380 { "bb",         0xc0006000, 0xffe06000, "?Bnx,!,w", pa20, FLAG_STRICT},
 381 { "bb",         0xc4006000, 0xfc006000, "?Bnx,Q,w", pa20, FLAG_STRICT},
 382 { "bb",         0xc0004000, 0xffe06000, "?bnx,!,w", pa10, FLAG_STRICT},
 383 { "bb",         0xc4004000, 0xfc004000, "?bnx,Q,w", pa10},
 384 { "bvb",        0xc0004000, 0xffe04000, "?bnx,w", pa10},
 385 { "clrbts",     0xe8004005, 0xffffffff, "", pa20, FLAG_STRICT},
 386 { "popbts",     0xe8004005, 0xfffff007, "$", pa20, FLAG_STRICT},
 387 { "pushnom",    0xe8004001, 0xffffffff, "", pa20, FLAG_STRICT},
 388 { "pushbts",    0xe8004001, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 389
 390 /* Computation Instructions */
 391
 392 { "cmpclr",     0x080008a0, 0xfc000fe0, "?Sx,b,t", pa20, FLAG_STRICT},
 393 { "cmpclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10, FLAG_STRICT},
 394 { "comclr",     0x08000880, 0xfc000fe0, "?sx,b,t", pa10},
 395 { "or",         0x08000260, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 396 { "or",         0x08000240, 0xfc000fe0, "?lx,b,t", pa10},
 397 { "xor",        0x080002a0, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 398 { "xor",        0x08000280, 0xfc000fe0, "?lx,b,t", pa10},
 399 { "and",        0x08000220, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 400 { "and",        0x08000200, 0xfc000fe0, "?lx,b,t", pa10},
 401 { "andcm",      0x08000020, 0xfc000fe0, "?Lx,b,t", pa20, FLAG_STRICT},
 402 { "andcm",      0x08000000, 0xfc000fe0, "?lx,b,t", pa10},
 403 { "uxor",       0x080003a0, 0xfc000fe0, "?Ux,b,t", pa20, FLAG_STRICT},
 404 { "uxor",       0x08000380, 0xfc000fe0, "?ux,b,t", pa10},
 405 { "uaddcm",     0x080009a0, 0xfc000fa0, "cT?Ux,b,t", pa20, FLAG_STRICT},
 406 { "uaddcm",     0x08000980, 0xfc000fa0, "cT?ux,b,t", pa10, FLAG_STRICT},
 407 { "uaddcm",     0x08000980, 0xfc000fe0, "?ux,b,t", pa10},
 408 { "uaddcmt",    0x080009c0, 0xfc000fe0, "?ux,b,t", pa10},
 409 { "dcor",       0x08000ba0, 0xfc1f0fa0, "ci?Ub,t", pa20, FLAG_STRICT},
 410 { "dcor",       0x08000b80, 0xfc1f0fa0, "ci?ub,t", pa10, FLAG_STRICT},
 411 { "dcor",       0x08000b80, 0xfc1f0fe0, "?ub,t",   pa10},
 412 { "idcor",      0x08000bc0, 0xfc1f0fe0, "?ub,t",   pa10},
 413 { "addi",       0xb0000000, 0xfc000000, "ct?ai,b,x", pa10, FLAG_STRICT},
 414 { "addi",       0xb4000000, 0xfc000000, "cv?ai,b,x", pa10, FLAG_STRICT},
 415 { "addi",       0xb4000000, 0xfc000800, "?ai,b,x", pa10},
 416 { "addio",      0xb4000800, 0xfc000800, "?ai,b,x", pa10},
 417 { "addit",      0xb0000000, 0xfc000800, "?ai,b,x", pa10},
 418 { "addito",     0xb0000800, 0xfc000800, "?ai,b,x", pa10},
 419 { "add",        0x08000720, 0xfc0007e0, "cY?Ax,b,t", pa20, FLAG_STRICT},
 420 { "add",        0x08000700, 0xfc0007e0, "cy?ax,b,t", pa10, FLAG_STRICT},
 421 { "add",        0x08000220, 0xfc0003e0, "ca?Ax,b,t", pa20, FLAG_STRICT},
 422 { "add",        0x08000200, 0xfc0003e0, "ca?ax,b,t", pa10, FLAG_STRICT},
 423 { "add",        0x08000600, 0xfc000fe0, "?ax,b,t", pa10},
 424 { "addl",       0x08000a00, 0xfc000fe0, "?ax,b,t", pa10},
 425 { "addo",       0x08000e00, 0xfc000fe0, "?ax,b,t", pa10},
 426 { "addc",       0x08000700, 0xfc000fe0, "?ax,b,t", pa10},
 427 { "addco",      0x08000f00, 0xfc000fe0, "?ax,b,t", pa10},
 428 { "sub",        0x080004e0, 0xfc0007e0, "ct?Sx,b,t", pa20, FLAG_STRICT},
 429 { "sub",        0x080004c0, 0xfc0007e0, "ct?sx,b,t", pa10, FLAG_STRICT},
 430 { "sub",        0x08000520, 0xfc0007e0, "cB?Sx,b,t", pa20, FLAG_STRICT},
 431 { "sub",        0x08000500, 0xfc0007e0, "cb?sx,b,t", pa10, FLAG_STRICT},
 432 { "sub",        0x08000420, 0xfc0007e0, "cv?Sx,b,t", pa20, FLAG_STRICT},
 433 { "sub",        0x08000400, 0xfc0007e0, "cv?sx,b,t", pa10, FLAG_STRICT},
 434 { "sub",        0x08000400, 0xfc000fe0, "?sx,b,t", pa10},
 435 { "subo",       0x08000c00, 0xfc000fe0, "?sx,b,t", pa10},
 436 { "subb",       0x08000500, 0xfc000fe0, "?sx,b,t", pa10},
 437 { "subbo",      0x08000d00, 0xfc000fe0, "?sx,b,t", pa10},
 438 { "subt",       0x080004c0, 0xfc000fe0, "?sx,b,t", pa10},
 439 { "subto",      0x08000cc0, 0xfc000fe0, "?sx,b,t", pa10},
 440 { "ds",         0x08000440, 0xfc000fe0, "?sx,b,t", pa10},
 441 { "subi",       0x94000000, 0xfc000000, "cv?si,b,x", pa10, FLAG_STRICT},
 442 { "subi",       0x94000000, 0xfc000800, "?si,b,x", pa10},
 443 { "subio",      0x94000800, 0xfc000800, "?si,b,x", pa10},
 444 { "cmpiclr",    0x90000800, 0xfc000800, "?Si,b,x", pa20, FLAG_STRICT},
 445 { "cmpiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10, FLAG_STRICT},
 446 { "comiclr",    0x90000000, 0xfc000800, "?si,b,x", pa10},
 447 { "shladd",     0x08000220, 0xfc000320, "ca?Ax,.,b,t", pa20, FLAG_STRICT},
 448 { "shladd",     0x08000200, 0xfc000320, "ca?ax,.,b,t", pa10, FLAG_STRICT},
 449 { "sh1add",     0x08000640, 0xfc000fe0, "?ax,b,t", pa10},
 450 { "sh1addl",    0x08000a40, 0xfc000fe0, "?ax,b,t", pa10},
 451 { "sh1addo",    0x08000e40, 0xfc000fe0, "?ax,b,t", pa10},
 452 { "sh2add",     0x08000680, 0xfc000fe0, "?ax,b,t", pa10},
 453 { "sh2addl",    0x08000a80, 0xfc000fe0, "?ax,b,t", pa10},
 454 { "sh2addo",    0x08000e80, 0xfc000fe0, "?ax,b,t", pa10},
 455 { "sh3add",     0x080006c0, 0xfc000fe0, "?ax,b,t", pa10},
 456 { "sh3addl",    0x08000ac0, 0xfc000fe0, "?ax,b,t", pa10},
 457 { "sh3addo",    0x08000ec0, 0xfc000fe0, "?ax,b,t", pa10},
 458
 459 /* Subword Operation Instructions */
 460
 461 { "hadd",       0x08000300, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
 462 { "havg",       0x080002c0, 0xfc00ffe0, "x,b,t", pa20, FLAG_STRICT},
 463 { "hshl",       0xf8008800, 0xffe0fc20, "x,*,t", pa20, FLAG_STRICT},
 464 { "hshladd",    0x08000700, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 465 { "hshr",       0xf800c800, 0xfc1ff820, "cSb,*,t", pa20, FLAG_STRICT},
 466 { "hshradd",    0x08000500, 0xfc00ff20, "x,.,b,t", pa20, FLAG_STRICT},
 467 { "hsub",       0x08000100, 0xfc00ff20, "cHx,b,t", pa20, FLAG_STRICT},
 468 { "mixh",       0xf8008400, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
 469 { "mixw",       0xf8008000, 0xfc009fe0, "chx,b,t", pa20, FLAG_STRICT},
 470 { "permh",      0xf8000000, 0xfc009020, "c*a,t", pa20, FLAG_STRICT},
 471
 472
 473 /* Extract and Deposit Instructions */
 474
 475 { "shrpd",      0xd0000200, 0xfc001fe0, "?Xx,b,!,t", pa20, FLAG_STRICT},
 476 { "shrpd",      0xd0000400, 0xfc001400, "?Xx,b,~,t", pa20, FLAG_STRICT},
 477 { "shrpw",      0xd0000000, 0xfc001fe0, "?xx,b,!,t", pa10, FLAG_STRICT},
 478 { "shrpw",      0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10, FLAG_STRICT},
 479 { "vshd",       0xd0000000, 0xfc001fe0, "?xx,b,t", pa10},
 480 { "shd",        0xd0000800, 0xfc001c00, "?xx,b,p,t", pa10},
 481 { "extrd",      0xd0001200, 0xfc001ae0, "cS?Xb,!,%,x", pa20, FLAG_STRICT},
 482 { "extrd",      0xd8000000, 0xfc000000, "cS?Xb,q,|,x", pa20, FLAG_STRICT},
 483 { "extrw",      0xd0001000, 0xfc001be0, "cS?xb,!,T,x", pa10, FLAG_STRICT},
 484 { "extrw",      0xd0001800, 0xfc001800, "cS?xb,P,T,x", pa10, FLAG_STRICT},
 485 { "vextru",     0xd0001000, 0xfc001fe0, "?xb,T,x", pa10},
 486 { "vextrs",     0xd0001400, 0xfc001fe0, "?xb,T,x", pa10},
 487 { "extru",      0xd0001800, 0xfc001c00, "?xb,P,T,x", pa10},
 488 { "extrs",      0xd0001c00, 0xfc001c00, "?xb,P,T,x", pa10},
 489 { "depd",       0xd4000200, 0xfc001ae0, "cz?Xx,!,%,b", pa20, FLAG_STRICT},
 490 { "depd",       0xf0000000, 0xfc000000, "cz?Xx,~,|,b", pa20, FLAG_STRICT},
 491 { "depdi",      0xd4001200, 0xfc001ae0, "cz?X5,!,%,b", pa20, FLAG_STRICT},
 492 { "depdi",      0xf4000000, 0xfc000000, "cz?X5,~,|,b", pa20, FLAG_STRICT},
 493 { "depw",       0xd4000000, 0xfc001be0, "cz?xx,!,T,b", pa10, FLAG_STRICT},
 494 { "depw",       0xd4000800, 0xfc001800, "cz?xx,p,T,b", pa10, FLAG_STRICT},
 495 { "depwi",      0xd4001000, 0xfc001be0, "cz?x5,!,T,b", pa10, FLAG_STRICT},
 496 { "depwi",      0xd4001800, 0xfc001800, "cz?x5,p,T,b", pa10, FLAG_STRICT},
 497 { "zvdep",      0xd4000000, 0xfc001fe0, "?xx,T,b", pa10},
 498 { "vdep",       0xd4000400, 0xfc001fe0, "?xx,T,b", pa10},
 499 { "zdep",       0xd4000800, 0xfc001c00, "?xx,p,T,b", pa10},
 500 { "dep",        0xd4000c00, 0xfc001c00, "?xx,p,T,b", pa10},
 501 { "zvdepi",     0xd4001000, 0xfc001fe0, "?x5,T,b", pa10},
 502 { "vdepi",      0xd4001400, 0xfc001fe0, "?x5,T,b", pa10},
 503 { "zdepi",      0xd4001800, 0xfc001c00, "?x5,p,T,b", pa10},
 504 { "depi",       0xd4001c00, 0xfc001c00, "?x5,p,T,b", pa10},
 505
 506 /* System Control Instructions */
 507
 508 { "break",      0x00000000, 0xfc001fe0, "r,A", pa10},
 509 { "rfi",        0x00000c00, 0xffffff1f, "cr", pa10, FLAG_STRICT},
 510 { "rfi",        0x00000c00, 0xffffffff, "", pa10},
 511 { "rfir",       0x00000ca0, 0xffffffff, "", pa11},
 512 { "ssm",        0x00000d60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
 513 { "ssm",        0x00000d60, 0xffe0ffe0, "R,t", pa10},
 514 { "rsm",        0x00000e60, 0xfc00ffe0, "U,t", pa20, FLAG_STRICT},
 515 { "rsm",        0x00000e60, 0xffe0ffe0, "R,t", pa10},
 516 { "mtsm",       0x00001860, 0xffe0ffff, "x", pa10},
 517 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(s,b),t", pa10},
 518 { "ldsid",      0x000010a0, 0xfc1f3fe0, "(b),t", pa10},
 519 { "mtsp",       0x00001820, 0xffe01fff, "x,S", pa10},
 520 { "mtctl",      0x00001840, 0xfc00ffff, "x,^", pa10},
 521 { "mtsarcm",    0x016018C0, 0xffe0ffff, "x", pa20, FLAG_STRICT},
 522 { "mfia",       0x000014A0, 0xffffffe0, "t", pa20, FLAG_STRICT},
 523 { "mfsp",       0x000004a0, 0xffff1fe0, "S,t", pa10},
 524 { "mfctl",      0x016048a0, 0xffffffe0, "cW!,t", pa20, FLAG_STRICT},
 525 { "mfctl",      0x000008a0, 0xfc1fffe0, "^,t", pa10},
 526 { "sync",       0x00000400, 0xffffffff, "", pa10},
 527 { "syncdma",    0x00100400, 0xffffffff, "", pa10},
 528 { "probe",      0x04001180, 0xfc003fa0, "cw(s,b),x,t", pa10, FLAG_STRICT},
 529 { "probe",      0x04001180, 0xfc003fa0, "cw(b),x,t", pa10, FLAG_STRICT},
 530 { "probei",     0x04003180, 0xfc003fa0, "cw(s,b),R,t", pa10, FLAG_STRICT},
 531 { "probei",     0x04003180, 0xfc003fa0, "cw(b),R,t", pa10, FLAG_STRICT},
 532 { "prober",     0x04001180, 0xfc003fe0, "(s,b),x,t", pa10},
 533 { "prober",     0x04001180, 0xfc003fe0, "(b),x,t", pa10},
 534 { "proberi",    0x04003180, 0xfc003fe0, "(s,b),R,t", pa10},
 535 { "proberi",    0x04003180, 0xfc003fe0, "(b),R,t", pa10},
 536 { "probew",     0x040011c0, 0xfc003fe0, "(s,b),x,t", pa10},
 537 { "probew",     0x040011c0, 0xfc003fe0, "(b),x,t", pa10},
 538 { "probewi",    0x040031c0, 0xfc003fe0, "(s,b),R,t", pa10},
 539 { "probewi",    0x040031c0, 0xfc003fe0, "(b),R,t", pa10},
 540 { "lpa",        0x04001340, 0xfc003fc0, "cZx(s,b),t", pa10},
 541 { "lpa",        0x04001340, 0xfc003fc0, "cZx(b),t", pa10},
 542 { "lha",        0x04001300, 0xfc003fc0, "cZx(s,b),t", pa10},
 543 { "lha",        0x04001300, 0xfc003fc0, "cZx(b),t", pa10},
 544 { "lci",        0x04001300, 0xfc003fe0, "x(s,b),t", pa10},
 545 { "lci",        0x04001300, 0xfc003fe0, "x(b),t", pa10},
 546 { "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(s,b)", pa20, FLAG_STRICT},
 547 { "pdtlb",      0x04001600, 0xfc003fdf, "cLcZx(b)", pa20, FLAG_STRICT},
 548 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(s,b)", pa10},
 549 { "pdtlb",      0x04001200, 0xfc003fdf, "cZx(b)", pa10},
 550 { "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(S,b)", pa20, FLAG_STRICT},
 551 { "pitlb",      0x04000600, 0xfc001fdf, "cLcZx(b)", pa20, FLAG_STRICT},
 552 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(S,b)", pa10},
 553 { "pitlb",      0x04000200, 0xfc001fdf, "cZx(b)", pa10},
 554 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(s,b)", pa10},
 555 { "pdtlbe",     0x04001240, 0xfc003fdf, "cZx(b)", pa10},
 556 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(S,b)", pa10},
 557 { "pitlbe",     0x04000240, 0xfc001fdf, "cZx(b)", pa10},
 558 { "idtlba",     0x04001040, 0xfc003fff, "x,(s,b)", pa10},
 559 { "idtlba",     0x04001040, 0xfc003fff, "x,(b)", pa10},
 560 { "iitlba",     0x04000040, 0xfc001fff, "x,(S,b)", pa10},
 561 { "iitlba",     0x04000040, 0xfc001fff, "x,(b)", pa10},
 562 { "idtlbp",     0x04001000, 0xfc003fff, "x,(s,b)", pa10},
 563 { "idtlbp",     0x04001000, 0xfc003fff, "x,(b)", pa10},
 564 { "iitlbp",     0x04000000, 0xfc001fff, "x,(S,b)", pa10},
 565 { "iitlbp",     0x04000000, 0xfc001fff, "x,(b)", pa10},
 566 { "pdc",        0x04001380, 0xfc003fdf, "cZx(s,b)", pa10},
 567 { "pdc",        0x04001380, 0xfc003fdf, "cZx(b)", pa10},
 568 { "fdc",        0x04001280, 0xfc003fdf, "cZx(s,b)", pa10},
 569 { "fdc",        0x04001280, 0xfc003fdf, "cZx(b)", pa10},
 570 { "fic",        0x04000280, 0xfc001fdf, "cZx(S,b)", pa10},
 571 { "fic",        0x04000280, 0xfc001fdf, "cZx(b)", pa10},
 572 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(s,b)", pa10},
 573 { "fdce",       0x040012c0, 0xfc003fdf, "cZx(b)", pa10},
 574 { "fice",       0x040002c0, 0xfc001fdf, "cZx(S,b)", pa10},
 575 { "fice",       0x040002c0, 0xfc001fdf, "cZx(b)", pa10},
 576 { "diag",       0x14000000, 0xfc000000, "D", pa10},
 577 { "idtlbt",     0x04001800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
 578 { "iitlbt",     0x04000800, 0xfc00ffff, "x,b", pa20, FLAG_STRICT},
 579
 580 /* These may be specific to certain versions of the PA.  Joel claimed
 581    they were 72000 (7200?) specific.  However, I'm almost certain the
 582    mtcpu/mfcpu were undocumented, but available in the older 700 machines.  */
 583 { "mtcpu",      0x14001600, 0xfc00ffff, "x,^"},
 584 { "mfcpu",      0x14001A00, 0xfc00ffff, "^,x"},
 585 { "tocen",      0x14403600, 0xffffffff, ""},
 586 { "tocdis",     0x14401620, 0xffffffff, ""},
 587 { "shdwgr",     0x14402600, 0xffffffff, ""},
 588 { "grshdw",     0x14400620, 0xffffffff, ""},
 589
 590 /* gfw and gfr are not in the HP PA 1.1 manual, but they are in either
 591    the Timex FPU or the Mustang ERS (not sure which) manual.  */
 592 { "gfw",        0x04001680, 0xfc003fdf, "cZx(s,b)", pa11},
 593 { "gfw",        0x04001680, 0xfc003fdf, "cZx(b)", pa11},
 594 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(s,b)", pa11},
 595 { "gfr",        0x04001a80, 0xfc003fdf, "cZx(b)", pa11},
 596
 597 /* Floating Point Coprocessor Instructions */
 598
 599 { "fldwx",      0x24000000, 0xfc001f80, "cxx(s,b),fT", pa10},
 600 { "fldwx",      0x24000000, 0xfc001f80, "cxx(b),fT", pa10},
 601 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(s,b),ft", pa10},
 602 { "flddx",      0x2c000000, 0xfc001fc0, "cxx(b),ft", pa10},
 603 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(s,b)", pa10},
 604 { "fstwx",      0x24000200, 0xfc001f80, "cxfT,x(b)", pa10},
 605 { "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
 606 { "fstdx",      0x2c000200, 0xfc001fc0, "cxft,x(b)", pa10},
 607 { "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10},
 608 { "fstqx",      0x3c000200, 0xfc001fc0, "cxft,x(b)", pa10},
 609 { "fldws",      0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10},
 610 { "fldws",      0x24001000, 0xfc001f80, "cm5(b),fT", pa10},
 611 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(s,b),ft", pa10},
 612 { "fldds",      0x2c001000, 0xfc001fc0, "cm5(b),ft", pa10},
 613 { "fstws",      0x24001200, 0xfc001f80, "cmfT,5(s,b)", pa10},
 614 { "fstws",      0x24001200, 0xfc001f80, "cmfT,5(b)", pa10},
 615 { "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
 616 { "fstds",      0x2c001200, 0xfc001fc0, "cmft,5(b)", pa10},
 617 { "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10},
 618 { "fstqs",      0x3c001200, 0xfc001fc0, "cmft,5(b)", pa10},
 619 { "fadd",       0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
 620 { "fadd",       0x38000600, 0xfc00e720, "IfA,fB,fT", pa10},
 621 { "fsub",       0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
 622 { "fsub",       0x38002600, 0xfc00e720, "IfA,fB,fT", pa10},
 623 { "fmpy",       0x30004600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
 624 { "fmpy",       0x38004600, 0xfc00e720, "IfA,fB,fT", pa10},
 625 { "fdiv",       0x30006600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
 626 { "fdiv",       0x38006600, 0xfc00e720, "IfA,fB,fT", pa10},
 627 { "fsqrt",      0x30008000, 0xfc1fe7e0, "Ffa,fT", pa10},
 628 { "fsqrt",      0x38008000, 0xfc1fe720, "FfA,fT", pa10},
 629 { "fabs",       0x30006000, 0xfc1fe7e0, "Ffa,fT", pa10},
 630 { "fabs",       0x38006000, 0xfc1fe720, "FfA,fT", pa10},
 631 { "frem",       0x30008600, 0xfc00e7e0, "Ffa,fb,fT", pa10},
 632 { "frem",       0x38008600, 0xfc00e720, "FfA,fB,fT", pa10},
 633 { "frnd",       0x3000a000, 0xfc1fe7e0, "Ffa,fT", pa10},
 634 { "frnd",       0x3800a000, 0xfc1fe720, "FfA,fT", pa10},
 635 { "fcpy",       0x30004000, 0xfc1fe7e0, "Ffa,fT", pa10},
 636 { "fcpy",       0x38004000, 0xfc1fe720, "FfA,fT", pa10},
 637 { "fcnvff",     0x30000200, 0xfc1f87e0, "FGfa,fT", pa10},
 638 { "fcnvff",     0x38000200, 0xfc1f8720, "FGfA,fT", pa10},
 639 { "fcnvxf",     0x30008200, 0xfc1f87e0, "FGfa,fT", pa10},
 640 { "fcnvxf",     0x38008200, 0xfc1f8720, "FGfA,fT", pa10},
 641 { "fcnvfx",     0x30010200, 0xfc1f87e0, "FGfa,fT", pa10},
 642 { "fcnvfx",     0x38010200, 0xfc1f8720, "FGfA,fT", pa10},
 643 { "fcnvfxt",    0x30018200, 0xfc1f87e0, "FGfa,fT", pa10},
 644 { "fcnvfxt",    0x38018200, 0xfc1f8720, "FGfA,fT", pa10},
 645 { "fmpyfadd",   0xb8000000, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
 646 { "fmpynfadd",  0xb8000020, 0xfc000020, "IfA,fB,fC,fT", pa20, FLAG_STRICT},
 647 { "fneg",       0x3000c000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
 648 { "fneg",       0x3800c000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
 649 { "fnegabs",    0x3000e000, 0xfc1fe7e0, "Ffa,fT", pa20, FLAG_STRICT},
 650 { "fnegabs",    0x3800e000, 0xfc1fe720, "IfA,fT", pa20, FLAG_STRICT},
 651 { "fcmp",       0x30000400, 0xfc00e7e0, "F?ffa,fb", pa10},
 652 { "fcmp",       0x38000400, 0xfc00e720, "I?ffA,fB", pa10},
 653 { "xmpyu",      0x38004700, 0xfc00e720, "fX,fB,fT", pa11},
 654 { "fmpyadd",    0x18000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
 655 { "fmpysub",    0x98000000, 0xfc000000, "Hfi,fj,fk,fl,fm", pa11},
 656 { "ftest",      0x30002420, 0xffffffff, "", pa10},
 657 { "fid",        0x30000000, 0xffffffff, "", pa11},
 658
 659 /* Performance Monitor Instructions */
 660
 661 { "pmdis",      0x30000280, 0xffffffdf, "N", pa20, FLAG_STRICT},
 662 { "pmenb",      0x30000680, 0xffffffff, "", pa20, FLAG_STRICT},
 663
 664 /* Assist Instructions */
 665
 666 { "spop0",      0x10000000, 0xfc000600, "v,ON", pa10},
 667 { "spop1",      0x10000200, 0xfc000600, "v,oNt", pa10},
 668 { "spop2",      0x10000400, 0xfc000600, "v,1Nb", pa10},
 669 { "spop3",      0x10000600, 0xfc000600, "v,0Nx,b", pa10},
 670 { "copr",       0x30000000, 0xfc000000, "u,2N", pa10},
 671 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10},
 672 { "cldwx",      0x24000000, 0xfc001e00, "ucxx(b),t", pa10},
 673 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10},
 674 { "clddx",      0x2c000000, 0xfc001e00, "ucxx(b),t", pa10},
 675 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10},
 676 { "cstwx",      0x24000200, 0xfc001e00, "ucxt,x(b)", pa10},
 677 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10},
 678 { "cstdx",      0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10},
 679 { "cldws",      0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10},
 680 { "cldws",      0x24001000, 0xfc001e00, "ucm5(b),t", pa10},
 681 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10},
 682 { "cldds",      0x2c001000, 0xfc001e00, "ucm5(b),t", pa10},
 683 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10},
 684 { "cstws",      0x24001200, 0xfc001e00, "ucmt,5(b)", pa10},
 685 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10},
 686 { "cstds",      0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10},
 687 { "cldw",       0x24000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
 688 { "cldw",       0x24000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
 689 { "cldw",       0x24001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
 690 { "cldw",       0x24001000, 0xfc001e00, "ucm5(b),t", pa10, FLAG_STRICT},
 691 { "cldd",       0x2c000000, 0xfc001e00, "ucxx(s,b),t", pa10, FLAG_STRICT},
 692 { "cldd",       0x2c000000, 0xfc001e00, "ucxx(b),t", pa10, FLAG_STRICT},
 693 { "cldd",       0x2c001000, 0xfc001e00, "ucm5(s,b),t", pa10, FLAG_STRICT},
 694 { "cldd",       0x2c001000, 0xfc001e00, "ucm5(b),t", pa20, FLAG_STRICT},
 695 { "cstw",       0x24000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
 696 { "cstw",       0x24000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
 697 { "cstw",       0x24001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
 698 { "cstw",       0x24001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
 699 { "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(s,b)", pa10, FLAG_STRICT},
 700 { "cstd",       0x2c000200, 0xfc001e00, "ucxt,x(b)", pa10, FLAG_STRICT},
 701 { "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(s,b)", pa10, FLAG_STRICT},
 702 { "cstd",       0x2c001200, 0xfc001e00, "ucmt,5(b)", pa10, FLAG_STRICT},
 703 };
 704
 705 #define NUMOPCODES ((sizeof pa_opcodes)/(sizeof pa_opcodes[0]))
 706
 707 /* SKV 12/18/92. Added some denotations for various operands. */
 708
 709 #define PA_IMM11_AT_31 'i'
 710 #define PA_IMM14_AT_31 'j'
 711 #define PA_IMM21_AT_31 'k'
 712 #define PA_DISP12 'w'
 713 #define PA_DISP17 'W'
 714
 715 #define N_HPPA_OPERAND_FORMATS 5