include/opcode/m68k.h

   1 /* Opcode table header for m680[01234]0/m6888[12]/m68851.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
   3    2003, 2004, 2006 Free Software Foundation, Inc.
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    1, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  20    02110-1301, USA.  */
  21
  22 /* These are used as bit flags for the arch field in the m68k_opcode
  23    structure.  */
  24 #define _m68k_undef  0
  25 #define m68000   0x001
  26 #define m68010   0x002
  27 #define m68020   0x004
  28 #define m68030   0x008
  29 #define m68040   0x010
  30 #define m68060   0x020
  31 #define m68881   0x040
  32 #define m68851   0x080
  33 #define cpu32    0x100          /* e.g., 68332 */
  34 #define m68k_mask  0x1ff
  35
  36 #define mcfmac   0x200          /* ColdFire MAC. */
  37 #define mcfemac  0x400          /* ColdFire EMAC. */
  38 #define cfloat   0x800          /* ColdFire FPU.  */
  39 #define mcfhwdiv 0x1000         /* ColdFire hardware divide.  */
  40
  41 #define mcfisa_a 0x2000         /* ColdFire ISA_A.  */
  42 #define mcfisa_aa 0x4000        /* ColdFire ISA_A+.  */
  43 #define mcfisa_b 0x8000         /* ColdFire ISA_B.  */
  44 #define mcfusp   0x10000        /* ColdFire USP instructions.  */
  45
  46 /* Handy aliases.  */
  47 #define m68040up   (m68040 | m68060)
  48 #define m68030up   (m68030 | m68040up)
  49 #define m68020up   (m68020 | m68030up)
  50 #define m68010up   (m68010 | cpu32 | m68020up)
  51 #define m68000up   (m68000 | m68010up)
  52
  53 #define mfloat  (m68881 | m68040 | m68060)
  54 #define mmmu    (m68851 | m68030 | m68040 | m68060)
  55
  56 /* The structure used to hold information for an opcode.  */
  57
  58 struct m68k_opcode
  59 {
  60   /* The opcode name.  */
  61   const char *name;
  62   /* The pseudo-size of the instruction(in bytes).  Used to determine
  63      number of bytes necessary to disassemble the instruction.  */
  64   unsigned int size;
  65   /* The opcode itself.  */
  66   unsigned long opcode;
  67   /* The mask used by the disassembler.  */
  68   unsigned long match;
  69   /* The arguments.  */
  70   const char *args;
  71   /* The architectures which support this opcode.  */
  72   unsigned int arch;
  73 };
  74
  75 /* The structure used to hold information for an opcode alias.  */
  76
  77 struct m68k_opcode_alias
  78 {
  79   /* The alias name.  */
  80   const char *alias;
  81   /* The instruction for which this is an alias.  */
  82   const char *primary;
  83 };
  84
  85 /* We store four bytes of opcode for all opcodes because that is the
  86    most any of them need.  The actual length of an instruction is
  87    always at least 2 bytes, and is as much longer as necessary to hold
  88    the operands it has.
  89
  90    The match field is a mask saying which bits must match particular
  91    opcode in order for an instruction to be an instance of that
  92    opcode.
  93
  94    The args field is a string containing two characters for each
  95    operand of the instruction.  The first specifies the kind of
  96    operand; the second, the place it is stored.  */
  97
  98 /* Kinds of operands:
  99    Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
 100
 101    D  data register only.  Stored as 3 bits.
 102    A  address register only.  Stored as 3 bits.
 103    a  address register indirect only.  Stored as 3 bits.
 104    R  either kind of register.  Stored as 4 bits.
 105    r  either kind of register indirect only.  Stored as 4 bits.
 106       At the moment, used only for cas2 instruction.
 107    F  floating point coprocessor register only.   Stored as 3 bits.
 108    O  an offset (or width): immediate data 0-31 or data register.
 109       Stored as 6 bits in special format for BF... insns.
 110    +  autoincrement only.  Stored as 3 bits (number of the address register).
 111    -  autodecrement only.  Stored as 3 bits (number of the address register).
 112    Q  quick immediate data.  Stored as 3 bits.
 113       This matches an immediate operand only when value is in range 1 .. 8.
 114    M  moveq immediate data.  Stored as 8 bits.
 115       This matches an immediate operand only when value is in range -128..127
 116    T  trap vector immediate data.  Stored as 4 bits.
 117
 118    k  K-factor for fmove.p instruction.   Stored as a 7-bit constant or
 119       a three bit register offset, depending on the field type.
 120
 121    #  immediate data.  Stored in special places (b, w or l)
 122       which say how many bits to store.
 123    ^  immediate data for floating point instructions.   Special places
 124       are offset by 2 bytes from '#'...
 125    B  pc-relative address, converted to an offset
 126       that is treated as immediate data.
 127    d  displacement and register.  Stores the register as 3 bits
 128       and stores the displacement in the entire second word.
 129
 130    C  the CCR.  No need to store it; this is just for filtering validity.
 131    S  the SR.  No need to store, just as with CCR.
 132    U  the USP.  No need to store, just as with CCR.
 133    E  the MAC ACC.  No need to store, just as with CCR.
 134    e  the EMAC ACC[0123].
 135    G  the MAC/EMAC MACSR.  No need to store, just as with CCR.
 136    g  the EMAC ACCEXT{01,23}.
 137    H  the MASK.  No need to store, just as with CCR.
 138    i  the MAC/EMAC scale factor.
 139
 140    I  Coprocessor ID.   Not printed if 1.   The Coprocessor ID is always
 141       extracted from the 'd' field of word one, which means that an extended
 142       coprocessor opcode can be skipped using the 'i' place, if needed.
 143
 144    s  System Control register for the floating point coprocessor.
 145
 146    J  Misc register for movec instruction, stored in 'j' format.
 147         Possible values:
 148         0x000   SFC     Source Function Code reg        [60, 40, 30, 20, 10]
 149         0x001   DFC     Data Function Code reg          [60, 40, 30, 20, 10]
 150         0x002   CACR    Cache Control Register          [60, 40, 30, 20, mcf]
 151         0x003   TC      MMU Translation Control         [60, 40]
 152         0x004   ITT0    Instruction Transparent
 153                                 Translation reg 0       [60, 40]
 154         0x005   ITT1    Instruction Transparent
 155                                 Translation reg 1       [60, 40]
 156         0x006   DTT0    Data Transparent
 157                                 Translation reg 0       [60, 40]
 158         0x007   DTT1    Data Transparent
 159                                 Translation reg 1       [60, 40]
 160         0x008   BUSCR   Bus Control Register            [60]
 161         0x800   USP     User Stack Pointer              [60, 40, 30, 20, 10]
 162         0x801   VBR     Vector Base reg                 [60, 40, 30, 20, 10, mcf]
 163         0x802   CAAR    Cache Address Register          [        30, 20]
 164         0x803   MSP     Master Stack Pointer            [    40, 30, 20]
 165         0x804   ISP     Interrupt Stack Pointer         [    40, 30, 20]
 166         0x805   MMUSR   MMU Status reg                  [    40]
 167         0x806   URP     User Root Pointer               [60, 40]
 168         0x807   SRP     Supervisor Root Pointer         [60, 40]
 169         0x808   PCR     Processor Configuration reg     [60]
 170         0xC00   ROMBAR  ROM Base Address Register       [520X]
 171         0xC04   RAMBAR0 RAM Base Address Register 0     [520X]
 172         0xC05   RAMBAR1 RAM Base Address Register 0     [520X]
 173         0xC0F   MBAR0   RAM Base Address Register 0     [520X]
 174         0xC04   FLASHBAR FLASH Base Address Register    [mcf528x]
 175         0xC05   RAMBAR  Static RAM Base Address Register [mcf528x]
 176
 177     L  Register list of the type d0-d7/a0-a7 etc.
 178        (New!  Improved!  Can also hold fp0-fp7, as well!)
 179        The assembler tries to see if the registers match the insn by
 180        looking at where the insn wants them stored.
 181
 182     l  Register list like L, but with all the bits reversed.
 183        Used for going the other way. . .
 184
 185     c  cache identifier which may be "nc" for no cache, "ic"
 186        for instruction cache, "dc" for data cache, or "bc"
 187        for both caches.  Used in cinv and cpush.  Always
 188        stored in position "d".
 189
 190     u  Any register, with ``upper'' or ``lower'' specification.  Used
 191        in the mac instructions with size word.
 192
 193  The remainder are all stored as 6 bits using an address mode and a
 194  register number; they differ in which addressing modes they match.
 195
 196    *  all                                       (modes 0-6,7.0-4)
 197    ~  alterable memory                          (modes 2-6,7.0,7.1)
 198                                                 (not 0,1,7.2-4)
 199    %  alterable                                 (modes 0-6,7.0,7.1)
 200                                                 (not 7.2-4)
 201    ;  data                                      (modes 0,2-6,7.0-4)
 202                                                 (not 1)
 203    @  data, but not immediate                   (modes 0,2-6,7.0-3)
 204                                                 (not 1,7.4)
 205    !  control                                   (modes 2,5,6,7.0-3)
 206                                                 (not 0,1,3,4,7.4)
 207    &  alterable control                         (modes 2,5,6,7.0,7.1)
 208                                                 (not 0,1,3,4,7.2-4)
 209    $  alterable data                            (modes 0,2-6,7.0,7.1)
 210                                                 (not 1,7.2-4)
 211    ?  alterable control, or data register       (modes 0,2,5,6,7.0,7.1)
 212                                                 (not 1,3,4,7.2-4)
 213    /  control, or data register                 (modes 0,2,5,6,7.0-3)
 214                                                 (not 1,3,4,7.4)
 215    >  *save operands                            (modes 2,4,5,6,7.0,7.1)
 216                                                 (not 0,1,3,7.2-4)
 217    <  *restore operands                         (modes 2,3,5,6,7.0-3)
 218                                                 (not 0,1,4,7.4)
 219
 220    coldfire move operands:
 221    m                                            (modes 0-4)
 222    n                                            (modes 5,7.2)
 223    o                                            (modes 6,7.0,7.1,7.3,7.4)
 224    p                                            (modes 0-5)
 225
 226    coldfire bset/bclr/btst/mulsl/mulul operands:
 227    q                                            (modes 0,2-5)
 228    v                                            (modes 0,2-5,7.0,7.1)
 229    b                                            (modes 0,2-5,7.2)
 230    w                                            (modes 2-5,7.2)
 231    y                                            (modes 2,5)
 232    z                                            (modes 2,5,7.2)
 233    x  mov3q immediate operand.
 234    4                                            (modes 2,3,4,5)
 235   */
 236
 237 /* For the 68851:  */
 238 /* I didn't use much imagination in choosing the
 239    following codes, so many of them aren't very
 240    mnemonic. -rab
 241
 242    0  32 bit pmmu register
 243         Possible values:
 244         000     TC      Translation Control Register (68030, 68851)
 245
 246    1  16 bit pmmu register
 247         111     AC      Access Control (68851)
 248
 249    2  8 bit pmmu register
 250         100     CAL     Current Access Level (68851)
 251         101     VAL     Validate Access Level (68851)
 252         110     SCC     Stack Change Control (68851)
 253
 254    3  68030-only pmmu registers (32 bit)
 255         010     TT0     Transparent Translation reg 0
 256                         (aka Access Control reg 0 -- AC0 -- on 68ec030)
 257         011     TT1     Transparent Translation reg 1
 258                         (aka Access Control reg 1 -- AC1 -- on 68ec030)
 259
 260    W  wide pmmu registers
 261         Possible values:
 262         001     DRP     Dma Root Pointer (68851)
 263         010     SRP     Supervisor Root Pointer (68030, 68851)
 264         011     CRP     Cpu Root Pointer (68030, 68851)
 265
 266    f    function code register (68030, 68851)
 267         0       SFC
 268         1       DFC
 269
 270    V    VAL register only (68851)
 271
 272    X    BADx, BACx (16 bit)
 273         100     BAD     Breakpoint Acknowledge Data (68851)
 274         101     BAC     Breakpoint Acknowledge Control (68851)
 275
 276    Y    PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
 277    Z    PCSR (68851)
 278
 279    |    memory          (modes 2-6, 7.*)
 280
 281    t  address test level (68030 only)
 282       Stored as 3 bits, range 0-7.
 283       Also used for breakpoint instruction now.
 284
 285 */
 286
 287 /* Places to put an operand, for non-general operands:
 288    Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
 289
 290    s  source, low bits of first word.
 291    d  dest, shifted 9 in first word
 292    1  second word, shifted 12
 293    2  second word, shifted 6
 294    3  second word, shifted 0
 295    4  third word, shifted 12
 296    5  third word, shifted 6
 297    6  third word, shifted 0
 298    7  second word, shifted 7
 299    8  second word, shifted 10
 300    9  second word, shifted 5
 301    D  store in both place 1 and place 3; for divul and divsl.
 302    B  first word, low byte, for branch displacements
 303    W  second word (entire), for branch displacements
 304    L  second and third words (entire), for branch displacements
 305       (also overloaded for move16)
 306    b  second word, low byte
 307    w  second word (entire) [variable word/long branch offset for dbra]
 308    W  second word (entire) (must be signed 16 bit value)
 309    l  second and third word (entire)
 310    g  variable branch offset for bra and similar instructions.
 311       The place to store depends on the magnitude of offset.
 312    t  store in both place 7 and place 8; for floating point operations
 313    c  branch offset for cpBcc operations.
 314       The place to store is word two if bit six of word one is zero,
 315       and words two and three if bit six of word one is one.
 316    i  Increment by two, to skip over coprocessor extended operands.   Only
 317       works with the 'I' format.
 318    k  Dynamic K-factor field.   Bits 6-4 of word 2, used as a register number.
 319       Also used for dynamic fmovem instruction.
 320    C  floating point coprocessor constant - 7 bits.  Also used for static
 321       K-factors...
 322    j  Movec register #, stored in 12 low bits of second word.
 323    m  For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
 324       and remaining 3 bits of register shifted 9 bits in first word.
 325       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 326       Use with `R' or `u' format.
 327    n  `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
 328       with MSB shifted 6 bits in first word and remaining 3 bits of
 329       register shifted 9 bits in first word.  No upper/lower
 330       indication is done.)  Use with `R' or `u' format.
 331    o  For M[S]ACw; 4 bits shifted 12 in second word (like `1').
 332       Indicate upper/lower in 1 bit shifted 7 bits in second word.
 333       Use with `R' or `u' format.
 334    M  For M[S]ACw; 4 bits in low bits of first word.  Indicate
 335       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 336       `R' or `u' format.
 337    N  For M[S]ACw; 4 bits in low bits of second word.  Indicate
 338       upper/lower in 1 bit shifted 6 bits in second word.  Use with
 339       `R' or `u' format.
 340    h  shift indicator (scale factor), 1 bit shifted 10 in second word
 341
 342  Places to put operand, for general operands:
 343    d  destination, shifted 6 bits in first word
 344    b  source, at low bit of first word, and immediate uses one byte
 345    w  source, at low bit of first word, and immediate uses two bytes
 346    l  source, at low bit of first word, and immediate uses four bytes
 347    s  source, at low bit of first word.
 348       Used sometimes in contexts where immediate is not allowed anyway.
 349    f  single precision float, low bit of 1st word, immediate uses 4 bytes
 350    F  double precision float, low bit of 1st word, immediate uses 8 bytes
 351    x  extended precision float, low bit of 1st word, immediate uses 12 bytes
 352    p  packed float, low bit of 1st word, immediate uses 12 bytes
 353    G  EMAC accumulator, load  (bit 4 2nd word, !bit8 first word)
 354    H  EMAC accumulator, non load  (bit 4 2nd word, bit 8 first word)
 355    F  EMAC ACCx
 356    f  EMAC ACCy
 357    I  MAC/EMAC scale factor
 358    /  Like 's', but set 2nd word, bit 5 if trailing_ampersand set
 359    ]  first word, bit 10
 360 */
 361
 362 extern const struct m68k_opcode m68k_opcodes[];
 363 extern const struct m68k_opcode_alias m68k_opcode_aliases[];
 364
 365 extern const int m68k_numopcodes, m68k_numaliases;
 366
 367 /* end of m68k-opcode.h */