1 /* mips.h. Mips opcode list for GDB, the GNU debugger.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Ralph Campbell and OSF
5 Commented and modified by Ian Lance Taylor, Cygnus Support
7 This file is part of GDB, GAS, and the GNU binutils.
9 GDB, GAS, and the GNU binutils are free software; you can redistribute
10 them and/or modify them under the terms of the GNU General Public
11 License as published by the Free Software Foundation; either version
12 1, or (at your option) any later version.
14 GDB, GAS, and the GNU binutils are distributed in the hope that they
15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 the GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this file; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
26 /* These are bit masks and shift counts to use to access the various
27 fields of an instruction. To retrieve the X field of an
28 instruction, use the expression
29 (i >> OP_SH_X) & OP_MASK_X
30 To set the same field (to j), use
31 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
33 Make sure you use fields that are appropriate for the instruction,
36 The 'i' format uses OP, RS, RT and IMMEDIATE.
38 The 'j' format uses OP and TARGET.
40 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
42 The 'b' format uses OP, RS, RT and DELTA.
44 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
46 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
48 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
49 breakpoint instruction are not defined; Kane says the breakpoint
50 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
51 only use ten bits). An optional two-operand form of break/sdbbp
52 allows the lower ten bits to be set too, and MIPS32 and later
53 architectures allow 20 bits to be set with a signal operand
56 The syscall instruction uses CODE20.
58 The general coprocessor instructions use COPZ. */
60 #define OP_MASK_OP 0x3f
62 #define OP_MASK_RS 0x1f
64 #define OP_MASK_FR 0x1f
66 #define OP_MASK_FMT 0x1f
68 #define OP_MASK_BCC 0x7
70 #define OP_MASK_CODE 0x3ff
72 #define OP_MASK_CODE2 0x3ff
74 #define OP_MASK_RT 0x1f
76 #define OP_MASK_FT 0x1f
78 #define OP_MASK_CACHE 0x1f
79 #define OP_SH_CACHE 16
80 #define OP_MASK_RD 0x1f
82 #define OP_MASK_FS 0x1f
84 #define OP_MASK_PREFX 0x1f
85 #define OP_SH_PREFX 11
86 #define OP_MASK_CCC 0x7
88 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
89 #define OP_SH_CODE20 6
90 #define OP_MASK_SHAMT 0x1f
92 #define OP_MASK_FD 0x1f
94 #define OP_MASK_TARGET 0x3ffffff
95 #define OP_SH_TARGET 0
96 #define OP_MASK_COPZ 0x1ffffff
98 #define OP_MASK_IMMEDIATE 0xffff
99 #define OP_SH_IMMEDIATE 0
100 #define OP_MASK_DELTA 0xffff
101 #define OP_SH_DELTA 0
102 #define OP_MASK_FUNCT 0x3f
103 #define OP_SH_FUNCT 0
104 #define OP_MASK_SPEC 0x3f
106 #define OP_SH_LOCC 8 /* FP condition code. */
107 #define OP_SH_HICC 18 /* FP condition code. */
108 #define OP_MASK_CC 0x7
109 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
110 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
111 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
112 #define OP_MASK_COP1SPEC 0xf
113 #define OP_MASK_COP1SCLR 0x4
114 #define OP_MASK_COP1CMP 0x3
115 #define OP_SH_COP1CMP 4
116 #define OP_SH_FORMAT 21 /* FP short format field. */
117 #define OP_MASK_FORMAT 0x7
118 #define OP_SH_TRUE 16
119 #define OP_MASK_TRUE 0x1
121 #define OP_MASK_GE 0x01
122 #define OP_SH_UNSIGNED 16
123 #define OP_MASK_UNSIGNED 0x1
124 #define OP_SH_HINT 16
125 #define OP_MASK_HINT 0x1f
126 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
127 #define OP_MASK_MMI 0x3f
128 #define OP_SH_MMISUB 6
129 #define OP_MASK_MMISUB 0x1f
130 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
131 #define OP_SH_PERFREG 1
132 #define OP_SH_SEL 0 /* Coprocessor select field. */
133 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
134 #define OP_SH_CODE19 6 /* 19 bit wait code. */
135 #define OP_MASK_CODE19 0x7ffff
137 /* This structure holds information for a particular instruction. */
141 /* The name of the instruction. */
143 /* A string describing the arguments for this instruction. */
145 /* The basic opcode for the instruction. When assembling, this
146 opcode is modified by the arguments to produce the actual opcode
147 that is used. If pinfo is INSN_MACRO, then this is 0. */
149 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
150 relevant portions of the opcode when disassembling. If the
151 actual opcode anded with the match field equals the opcode field,
152 then we have found the correct instruction. If pinfo is
153 INSN_MACRO, then this field is the macro identifier. */
155 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
156 of bits describing the instruction, notably any relevant hazard
159 /* A collection of bits describing the instruction sets of which this
160 instruction or macro is a member. */
161 unsigned long membership
;
164 /* These are the characters which may appears in the args field of an
165 instruction. They appear in the order in which the fields appear
166 when the instruction is used. Commas and parentheses in the args
167 string are ignored when assembling, and written into the output
170 Each of these characters corresponds to a mask field defined above.
172 "<" 5 bit shift amount (OP_*_SHAMT)
173 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
174 "a" 26 bit target address (OP_*_TARGET)
175 "b" 5 bit base register (OP_*_RS)
176 "c" 10 bit breakpoint code (OP_*_CODE)
177 "d" 5 bit destination register specifier (OP_*_RD)
178 "h" 5 bit prefx hint (OP_*_PREFX)
179 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
180 "j" 16 bit signed immediate (OP_*_DELTA)
181 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
182 "o" 16 bit signed offset (OP_*_DELTA)
183 "p" 16 bit PC relative branch target address (OP_*_DELTA)
184 "q" 10 bit extra breakpoint code (OP_*_CODE2)
185 "r" 5 bit same register used as both source and target (OP_*_RS)
186 "s" 5 bit source register specifier (OP_*_RS)
187 "t" 5 bit target register (OP_*_RT)
188 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
189 "v" 5 bit same register used as both source and destination (OP_*_RS)
190 "w" 5 bit same register used as both target and destination (OP_*_RT)
191 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
192 (used by clo and clz)
193 "C" 25 bit coprocessor function code (OP_*_COPZ)
194 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
195 "J" 19 bit wait function code (OP_*_CODE19)
196 "x" accept and ignore register name
197 "z" must be zero register
199 Floating point instructions:
200 "D" 5 bit destination register (OP_*_FD)
201 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
202 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
203 "S" 5 bit fs source 1 register (OP_*_FS)
204 "T" 5 bit ft source 2 register (OP_*_FT)
205 "R" 5 bit fr source 3 register (OP_*_FR)
206 "V" 5 bit same register used as floating source and destination (OP_*_FS)
207 "W" 5 bit same register used as floating target and destination (OP_*_FT)
209 Coprocessor instructions:
210 "E" 5 bit target register (OP_*_RT)
211 "G" 5 bit destination register (OP_*_RD)
212 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
213 "P" 5 bit performance-monitor register (OP_*_PERFREG)
216 "A" General 32 bit expression
218 "F" 64 bit floating point constant in .rdata
219 "L" 64 bit floating point constant in .lit8
220 "f" 32 bit floating point constant
221 "l" 32 bit floating point constant in .lit4
224 "()" parens surrounding optional value
225 "," separates operands
227 Characters used so far, for quick reference when adding more:
229 "ABCDEFGHIJLMNPRSTUVW"
230 "abcdfhijklopqrstuvwxz"
233 /* These are the bits which may be set in the pinfo field of an
234 instructions, if it is not equal to INSN_MACRO. */
236 /* Modifies the general purpose register in OP_*_RD. */
237 #define INSN_WRITE_GPR_D 0x00000001
238 /* Modifies the general purpose register in OP_*_RT. */
239 #define INSN_WRITE_GPR_T 0x00000002
240 /* Modifies general purpose register 31. */
241 #define INSN_WRITE_GPR_31 0x00000004
242 /* Modifies the floating point register in OP_*_FD. */
243 #define INSN_WRITE_FPR_D 0x00000008
244 /* Modifies the floating point register in OP_*_FS. */
245 #define INSN_WRITE_FPR_S 0x00000010
246 /* Modifies the floating point register in OP_*_FT. */
247 #define INSN_WRITE_FPR_T 0x00000020
248 /* Reads the general purpose register in OP_*_RS. */
249 #define INSN_READ_GPR_S 0x00000040
250 /* Reads the general purpose register in OP_*_RT. */
251 #define INSN_READ_GPR_T 0x00000080
252 /* Reads the floating point register in OP_*_FS. */
253 #define INSN_READ_FPR_S 0x00000100
254 /* Reads the floating point register in OP_*_FT. */
255 #define INSN_READ_FPR_T 0x00000200
256 /* Reads the floating point register in OP_*_FR. */
257 #define INSN_READ_FPR_R 0x00000400
258 /* Modifies coprocessor condition code. */
259 #define INSN_WRITE_COND_CODE 0x00000800
260 /* Reads coprocessor condition code. */
261 #define INSN_READ_COND_CODE 0x00001000
263 #define INSN_TLB 0x00002000
264 /* Reads coprocessor register other than floating point register. */
265 #define INSN_COP 0x00004000
266 /* Instruction loads value from memory, requiring delay. */
267 #define INSN_LOAD_MEMORY_DELAY 0x00008000
268 /* Instruction loads value from coprocessor, requiring delay. */
269 #define INSN_LOAD_COPROC_DELAY 0x00010000
270 /* Instruction has unconditional branch delay slot. */
271 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
272 /* Instruction has conditional branch delay slot. */
273 #define INSN_COND_BRANCH_DELAY 0x00040000
274 /* Conditional branch likely: if branch not taken, insn nullified. */
275 #define INSN_COND_BRANCH_LIKELY 0x00080000
276 /* Moves to coprocessor register, requiring delay. */
277 #define INSN_COPROC_MOVE_DELAY 0x00100000
278 /* Loads coprocessor register from memory, requiring delay. */
279 #define INSN_COPROC_MEMORY_DELAY 0x00200000
280 /* Reads the HI register. */
281 #define INSN_READ_HI 0x00400000
282 /* Reads the LO register. */
283 #define INSN_READ_LO 0x00800000
284 /* Modifies the HI register. */
285 #define INSN_WRITE_HI 0x01000000
286 /* Modifies the LO register. */
287 #define INSN_WRITE_LO 0x02000000
288 /* Takes a trap (easier to keep out of delay slot). */
289 #define INSN_TRAP 0x04000000
290 /* Instruction stores value into memory. */
291 #define INSN_STORE_MEMORY 0x08000000
292 /* Instruction uses single precision floating point. */
293 #define FP_S 0x10000000
294 /* Instruction uses double precision floating point. */
295 #define FP_D 0x20000000
296 /* Instruction is part of the tx39's integer multiply family. */
297 #define INSN_MULT 0x40000000
298 /* Instruction synchronize shared memory. */
299 #define INSN_SYNC 0x80000000
301 /* Instruction is actually a macro. It should be ignored by the
302 disassembler, and requires special treatment by the assembler. */
303 #define INSN_MACRO 0xffffffff
305 /* Masks used to mark instructions to indicate which MIPS ISA level
306 they were introduced in. ISAs, as defined below, are logical
307 ORs of these bits, indicatingthat they support the instructions
308 defined at the given level. */
310 #define INSN_ISA_MASK 0x00000fff
311 #define INSN_ISA1 0x00000010
312 #define INSN_ISA2 0x00000020
313 #define INSN_ISA3 0x00000040
314 #define INSN_ISA4 0x00000080
315 #define INSN_ISA5 0x00000100
316 #define INSN_ISA32 0x00000200
317 #define INSN_ISA64 0x00000400
319 /* Masks used for MIPS-defined ASEs. */
322 #define INSN_MIPS3D 0x00004000
324 /* Chip specific instructions. These are bitmasks. */
326 /* MIPS R4650 instruction. */
327 #define INSN_4650 0x00010000
328 /* LSI R4010 instruction. */
329 #define INSN_4010 0x00020000
330 /* NEC VR4100 instruction. */
331 #define INSN_4100 0x00040000
332 /* Toshiba R3900 instruction. */
333 #define INSN_3900 0x00080000
334 /* MIPS R10000 instruction. */
335 #define INSN_10000 0x00100000
336 /* Broadcom SB-1 instruction. */
337 #define INSN_SB1 0x00200000
339 /* MIPS ISA defines, use instead of hardcoding ISA level. */
341 #define ISA_UNKNOWN 0 /* Gas internal use. */
342 #define ISA_MIPS1 (INSN_ISA1)
343 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
344 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
345 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
346 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
347 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
348 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
350 /* CPU defines, use instead of hardcoding processor number. Keep this
351 in sync with bfd/archures.c in order for machine selection to work. */
352 #define CPU_UNKNOWN 0 /* Gas internal use. */
353 #define CPU_R2000 2000
354 #define CPU_R3000 3000
355 #define CPU_R3900 3900
356 #define CPU_R4000 4000
357 #define CPU_R4010 4010
358 #define CPU_VR4100 4100
359 #define CPU_R4111 4111
360 #define CPU_R4300 4300
361 #define CPU_R4400 4400
362 #define CPU_R4600 4600
363 #define CPU_R4650 4650
364 #define CPU_R5000 5000
365 #define CPU_R6000 6000
366 #define CPU_R8000 8000
367 #define CPU_R10000 10000
368 #define CPU_R12000 12000
369 #define CPU_MIPS16 16
370 #define CPU_MIPS32 32
372 #define CPU_MIPS64 64
373 #define CPU_SB1 12310201 /* octal 'SB', 01. */
375 /* Test for membership in an ISA including chip specific ISAs. INSN
376 is pointer to an element of the opcode table; ISA is the specified
377 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
378 test, or zero if no CPU specific ISA test is desired. */
380 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
381 (((insn)->membership & isa) != 0 \
382 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
383 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
384 || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \
385 && ((insn)->membership & INSN_4100) != 0) \
386 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
387 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
388 && ((insn)->membership & INSN_10000) != 0) \
389 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
390 || 0) /* Please keep this term for easier source merging. */
392 /* This is a list of macro expanded instructions.
394 _I appended means immediate
395 _A appended means address
396 _AB appended means address with base register
397 _D appended means 64 bit floating point constant
398 _S appended means 32 bit floating point constant. */
617 /* The order of overloaded instructions matters. Label arguments and
618 register arguments look the same. Instructions that can have either
619 for arguments must apear in the correct order in this table for the
620 assembler to pick the right one. In other words, entries with
621 immediate operands must apear after the same instruction with
624 Many instructions are short hand for other instructions (i.e., The
625 jal <register> instruction is short for jalr <register>). */
627 extern const struct mips_opcode mips_builtin_opcodes
[];
628 extern const int bfd_mips_num_builtin_opcodes
;
629 extern struct mips_opcode
*mips_opcodes
;
630 extern int bfd_mips_num_opcodes
;
631 #define NUMOPCODES bfd_mips_num_opcodes
634 /* The rest of this file adds definitions for the mips16 TinyRISC
637 /* These are the bitmasks and shift counts used for the different
638 fields in the instruction formats. Other than OP, no masks are
639 provided for the fixed portions of an instruction, since they are
642 The I format uses IMM11.
644 The RI format uses RX and IMM8.
646 The RR format uses RX, and RY.
648 The RRI format uses RX, RY, and IMM5.
650 The RRR format uses RX, RY, and RZ.
652 The RRI_A format uses RX, RY, and IMM4.
654 The SHIFT format uses RX, RY, and SHAMT.
656 The I8 format uses IMM8.
658 The I8_MOVR32 format uses RY and REGR32.
660 The IR_MOV32R format uses REG32R and MOV32Z.
662 The I64 format uses IMM8.
664 The RI64 format uses RY and IMM5.
667 #define MIPS16OP_MASK_OP 0x1f
668 #define MIPS16OP_SH_OP 11
669 #define MIPS16OP_MASK_IMM11 0x7ff
670 #define MIPS16OP_SH_IMM11 0
671 #define MIPS16OP_MASK_RX 0x7
672 #define MIPS16OP_SH_RX 8
673 #define MIPS16OP_MASK_IMM8 0xff
674 #define MIPS16OP_SH_IMM8 0
675 #define MIPS16OP_MASK_RY 0x7
676 #define MIPS16OP_SH_RY 5
677 #define MIPS16OP_MASK_IMM5 0x1f
678 #define MIPS16OP_SH_IMM5 0
679 #define MIPS16OP_MASK_RZ 0x7
680 #define MIPS16OP_SH_RZ 2
681 #define MIPS16OP_MASK_IMM4 0xf
682 #define MIPS16OP_SH_IMM4 0
683 #define MIPS16OP_MASK_REGR32 0x1f
684 #define MIPS16OP_SH_REGR32 0
685 #define MIPS16OP_MASK_REG32R 0x1f
686 #define MIPS16OP_SH_REG32R 3
687 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
688 #define MIPS16OP_MASK_MOVE32Z 0x7
689 #define MIPS16OP_SH_MOVE32Z 0
690 #define MIPS16OP_MASK_IMM6 0x3f
691 #define MIPS16OP_SH_IMM6 5
693 /* These are the characters which may appears in the args field of an
694 instruction. They appear in the order in which the fields appear
695 when the instruction is used. Commas and parentheses in the args
696 string are ignored when assembling, and written into the output
699 "y" 3 bit register (MIPS16OP_*_RY)
700 "x" 3 bit register (MIPS16OP_*_RX)
701 "z" 3 bit register (MIPS16OP_*_RZ)
702 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
703 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
704 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
705 "0" zero register ($0)
706 "S" stack pointer ($sp or $29)
708 "R" return address register ($ra or $31)
709 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
710 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
711 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
712 "a" 26 bit jump address
713 "e" 11 bit extension value
714 "l" register list for entry instruction
715 "L" register list for exit instruction
717 The remaining codes may be extended. Except as otherwise noted,
718 the full extended operand is a 16 bit signed value.
719 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
720 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
721 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
722 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
723 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
724 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
725 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
726 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
727 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
728 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
729 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
730 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
731 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
732 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
733 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
734 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
735 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
736 "q" 11 bit branch address (MIPS16OP_*_IMM11)
737 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
738 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
739 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
742 /* For the mips16, we use the same opcode table format and a few of
743 the same flags. However, most of the flags are different. */
745 /* Modifies the register in MIPS16OP_*_RX. */
746 #define MIPS16_INSN_WRITE_X 0x00000001
747 /* Modifies the register in MIPS16OP_*_RY. */
748 #define MIPS16_INSN_WRITE_Y 0x00000002
749 /* Modifies the register in MIPS16OP_*_RZ. */
750 #define MIPS16_INSN_WRITE_Z 0x00000004
751 /* Modifies the T ($24) register. */
752 #define MIPS16_INSN_WRITE_T 0x00000008
753 /* Modifies the SP ($29) register. */
754 #define MIPS16_INSN_WRITE_SP 0x00000010
755 /* Modifies the RA ($31) register. */
756 #define MIPS16_INSN_WRITE_31 0x00000020
757 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
758 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
759 /* Reads the register in MIPS16OP_*_RX. */
760 #define MIPS16_INSN_READ_X 0x00000080
761 /* Reads the register in MIPS16OP_*_RY. */
762 #define MIPS16_INSN_READ_Y 0x00000100
763 /* Reads the register in MIPS16OP_*_MOVE32Z. */
764 #define MIPS16_INSN_READ_Z 0x00000200
765 /* Reads the T ($24) register. */
766 #define MIPS16_INSN_READ_T 0x00000400
767 /* Reads the SP ($29) register. */
768 #define MIPS16_INSN_READ_SP 0x00000800
769 /* Reads the RA ($31) register. */
770 #define MIPS16_INSN_READ_31 0x00001000
771 /* Reads the program counter. */
772 #define MIPS16_INSN_READ_PC 0x00002000
773 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
774 #define MIPS16_INSN_READ_GPR_X 0x00004000
775 /* Is a branch insn. */
776 #define MIPS16_INSN_BRANCH 0x00010000
778 /* The following flags have the same value for the mips16 opcode
780 INSN_UNCOND_BRANCH_DELAY
781 INSN_COND_BRANCH_DELAY
782 INSN_COND_BRANCH_LIKELY (never used)
791 extern const struct mips_opcode mips16_opcodes
[];
792 extern const int bfd_mips16_num_opcodes
;
794 #endif /* _MIPS_H_ */