include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 94, 95, 1996 Free Software Foundation, Inc.
   3    Contributed by Ralph Campbell and OSF
   4    Commented and modified by Ian Lance Taylor, Cygnus Support
   5
   6 This file is part of GDB, GAS, and the GNU binutils.
   7
   8 GDB, GAS, and the GNU binutils are free software; you can redistribute
   9 them and/or modify them under the terms of the GNU General Public
  10 License as published by the Free Software Foundation; either version
  11 1, or (at your option) any later version.
  12
  13 GDB, GAS, and the GNU binutils are distributed in the hope that they
  14 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16 the GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with this file; see the file COPYING.  If not, write to the Free
  20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  21
  22 #ifndef _MIPS_H_
  23 #define _MIPS_H_
  24
  25 /* These are bit masks and shift counts to use to access the various
  26    fields of an instruction.  To retrieve the X field of an
  27    instruction, use the expression
  28         (i >> OP_SH_X) & OP_MASK_X
  29    To set the same field (to j), use
  30         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  31
  32    Make sure you use fields that are appropriate for the instruction,
  33    of course.
  34
  35    The 'i' format uses OP, RS, RT and IMMEDIATE.
  36
  37    The 'j' format uses OP and TARGET.
  38
  39    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  40
  41    The 'b' format uses OP, RS, RT and DELTA.
  42
  43    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  44
  45    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  46
  47    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  48    breakpoint instruction are not defined; Kane says the breakpoint
  49    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  50    only use ten bits).
  51
  52    The syscall instruction uses SYSCALL.
  53
  54    The general coprocessor instructions use COPZ.  */
  55
  56 #define OP_MASK_OP              0x3f
  57 #define OP_SH_OP                26
  58 #define OP_MASK_RS              0x1f
  59 #define OP_SH_RS                21
  60 #define OP_MASK_FR              0x1f
  61 #define OP_SH_FR                21
  62 #define OP_MASK_FMT             0x1f
  63 #define OP_SH_FMT               21
  64 #define OP_MASK_BCC             0x7
  65 #define OP_SH_BCC               18
  66 #define OP_MASK_CODE            0x3ff
  67 #define OP_SH_CODE              16
  68 #define OP_MASK_RT              0x1f
  69 #define OP_SH_RT                16
  70 #define OP_MASK_FT              0x1f
  71 #define OP_SH_FT                16
  72 #define OP_MASK_CACHE           0x1f
  73 #define OP_SH_CACHE             16
  74 #define OP_MASK_RD              0x1f
  75 #define OP_SH_RD                11
  76 #define OP_MASK_FS              0x1f
  77 #define OP_SH_FS                11
  78 #define OP_MASK_PREFX           0x1f
  79 #define OP_SH_PREFX             11
  80 #define OP_MASK_CCC             0x7
  81 #define OP_SH_CCC               8
  82 #define OP_MASK_SYSCALL         0xfffff
  83 #define OP_SH_SYSCALL           6
  84 #define OP_MASK_SHAMT           0x1f
  85 #define OP_SH_SHAMT             6
  86 #define OP_MASK_FD              0x1f
  87 #define OP_SH_FD                6
  88 #define OP_MASK_TARGET          0x3ffffff
  89 #define OP_SH_TARGET            0
  90 #define OP_MASK_COPZ            0x1ffffff
  91 #define OP_SH_COPZ              0
  92 #define OP_MASK_IMMEDIATE       0xffff
  93 #define OP_SH_IMMEDIATE         0
  94 #define OP_MASK_DELTA           0xffff
  95 #define OP_SH_DELTA             0
  96 #define OP_MASK_FUNCT           0x3f
  97 #define OP_SH_FUNCT             0
  98 #define OP_MASK_SPEC            0x3f
  99 #define OP_SH_SPEC              0
 100 #define OP_SH_LOCC              8       /* FP condition code */
 101 #define OP_SH_HICC              18      /* FP condition code */
 102 #define OP_MASK_CC              0x7
 103 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding */
 104 #define OP_MASK_COP1NORM        0x1     /* a single bit */
 105 #define OP_SH_COP1SPEC          21      /* COP1 encodings */
 106 #define OP_MASK_COP1SPEC        0xf
 107 #define OP_MASK_COP1SCLR        0x4
 108 #define OP_MASK_COP1CMP         0x3
 109 #define OP_SH_COP1CMP           4
 110 #define OP_SH_FORMAT            21      /* FP short format field */
 111 #define OP_MASK_FORMAT          0x7
 112 #define OP_SH_TRUE              16
 113 #define OP_MASK_TRUE            0x1
 114 #define OP_SH_GE                17
 115 #define OP_MASK_GE              0x01
 116 #define OP_SH_UNSIGNED          16
 117 #define OP_MASK_UNSIGNED        0x1
 118 #define OP_SH_HINT              16
 119 #define OP_MASK_HINT            0x1f
 120 #define OP_SH_MMI               0       /* Multimedia (parallel) op */
 121 #define OP_MASK_MMI             0x3f
 122 #define OP_SH_MMISUB            6
 123 #define OP_MASK_MMISUB          0x1f
 124
 125 /* This structure holds information for a particular instruction.  */
 126
 127 struct mips_opcode
 128 {
 129   /* The name of the instruction.  */
 130   const char *name;
 131   /* A string describing the arguments for this instruction.  */
 132   const char *args;
 133   /* The basic opcode for the instruction.  When assembling, this
 134      opcode is modified by the arguments to produce the actual opcode
 135      that is used.  If pinfo is INSN_MACRO, then this is instead the
 136      ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
 137      etc.).  */
 138   unsigned long match;
 139   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 140      relevant portions of the opcode when disassembling.  If the
 141      actual opcode anded with the match field equals the opcode field,
 142      then we have found the correct instruction.  If pinfo is
 143      INSN_MACRO, then this field is the macro identifier.  */
 144   unsigned long mask;
 145   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 146      of bits describing the instruction, notably any relevant hazard
 147      information.  */
 148   unsigned long pinfo;
 149 };
 150
 151 /* These are the characters which may appears in the args field of an
 152    instruction.  They appear in the order in which the fields appear
 153    when the instruction is used.  Commas and parentheses in the args
 154    string are ignored when assembling, and written into the output
 155    when disassembling.
 156
 157    Each of these characters corresponds to a mask field defined above.
 158
 159    "<" 5 bit shift amount (OP_*_SHAMT)
 160    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 161    "a" 26 bit target address (OP_*_TARGET)
 162    "b" 5 bit base register (OP_*_RS)
 163    "c" 10 bit breakpoint code (OP_*_CODE)
 164    "d" 5 bit destination register specifier (OP_*_RD)
 165    "h" 5 bit prefx hint (OP_*_PREFX)
 166    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 167    "j" 16 bit signed immediate (OP_*_DELTA)
 168    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 169    "o" 16 bit signed offset (OP_*_DELTA)
 170    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 171    "r" 5 bit same register used as both source and target (OP_*_RS)
 172    "s" 5 bit source register specifier (OP_*_RS)
 173    "t" 5 bit target register (OP_*_RT)
 174    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 175    "v" 5 bit same register used as both source and destination (OP_*_RS)
 176    "w" 5 bit same register used as both target and destination (OP_*_RT)
 177    "C" 25 bit coprocessor function code (OP_*_COPZ)
 178    "B" 20 bit syscall function code (OP_*_SYSCALL)
 179    "x" accept and ignore register name
 180    "z" must be zero register
 181
 182    Floating point instructions:
 183    "D" 5 bit destination register (OP_*_FD)
 184    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 185    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 186    "S" 5 bit fs source 1 register (OP_*_FS)
 187    "T" 5 bit ft source 2 register (OP_*_FT)
 188    "R" 5 bit fr source 3 register (OP_*_FR)
 189    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 190    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 191
 192    Coprocessor instructions:
 193    "E" 5 bit target register (OP_*_RT)
 194    "G" 5 bit destination register (OP_*_RD)
 195
 196    Macro instructions:
 197    "A" General 32 bit expression
 198    "I" 32 bit immediate
 199    "F" 64 bit floating point constant in .rdata
 200    "L" 64 bit floating point constant in .lit8
 201    "f" 32 bit floating point constant
 202    "l" 32 bit floating point constant in .lit4
 203 */
 204
 205 /* These are the bits which may be set in the pinfo field of an
 206    instructions, if it is not equal to INSN_MACRO.  */
 207
 208 /* Modifies the general purpose register in OP_*_RD.  */
 209 #define INSN_WRITE_GPR_D            0x00000001
 210 /* Modifies the general purpose register in OP_*_RT.  */
 211 #define INSN_WRITE_GPR_T            0x00000002
 212 /* Modifies general purpose register 31.  */
 213 #define INSN_WRITE_GPR_31           0x00000004
 214 /* Modifies the floating point register in OP_*_FD.  */
 215 #define INSN_WRITE_FPR_D            0x00000008
 216 /* Modifies the floating point register in OP_*_FS.  */
 217 #define INSN_WRITE_FPR_S            0x00000010
 218 /* Modifies the floating point register in OP_*_FT.  */
 219 #define INSN_WRITE_FPR_T            0x00000020
 220 /* Reads the general purpose register in OP_*_RS.  */
 221 #define INSN_READ_GPR_S             0x00000040
 222 /* Reads the general purpose register in OP_*_RT.  */
 223 #define INSN_READ_GPR_T             0x00000080
 224 /* Reads the floating point register in OP_*_FS.  */
 225 #define INSN_READ_FPR_S             0x00000100
 226 /* Reads the floating point register in OP_*_FT.  */
 227 #define INSN_READ_FPR_T             0x00000200
 228 /* Reads the floating point register in OP_*_FR.  */
 229 #define INSN_READ_FPR_R             0x00000400
 230 /* Modifies coprocessor condition code.  */
 231 #define INSN_WRITE_COND_CODE        0x00000800
 232 /* Reads coprocessor condition code.  */
 233 #define INSN_READ_COND_CODE         0x00001000
 234 /* TLB operation.  */
 235 #define INSN_TLB                    0x00002000
 236 /* Reads coprocessor register other than floating point register.  */
 237 #define INSN_COP                    0x00004000
 238 /* Instruction loads value from memory, requiring delay.  */
 239 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 240 /* Instruction loads value from coprocessor, requiring delay.  */
 241 #define INSN_LOAD_COPROC_DELAY      0x00010000
 242 /* Instruction has unconditional branch delay slot.  */
 243 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 244 /* Instruction has conditional branch delay slot.  */
 245 #define INSN_COND_BRANCH_DELAY      0x00040000
 246 /* Conditional branch likely: if branch not taken, insn nullified.  */
 247 #define INSN_COND_BRANCH_LIKELY     0x00080000
 248 /* Moves to coprocessor register, requiring delay.  */
 249 #define INSN_COPROC_MOVE_DELAY      0x00100000
 250 /* Loads coprocessor register from memory, requiring delay.  */
 251 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 252 /* Reads the HI register.  */
 253 #define INSN_READ_HI                0x00400000
 254 /* Reads the LO register.  */
 255 #define INSN_READ_LO                0x00800000
 256 /* Modifies the HI register.  */
 257 #define INSN_WRITE_HI               0x01000000
 258 /* Modifies the LO register.  */
 259 #define INSN_WRITE_LO               0x02000000
 260 /* Takes a trap (easier to keep out of delay slot).  */
 261 #define INSN_TRAP                   0x04000000
 262 /* Instruction stores value into memory.  */
 263 #define INSN_STORE_MEMORY           0x08000000
 264 /* MIPS ISA field--CPU level at which insn is supported.  */
 265 #define INSN_ISA                    0x70000000
 266 /* MIPS ISA 2 instruction (R6000 or R4000).  */
 267 #define INSN_ISA2                   0x10000000
 268 /* MIPS ISA 3 instruction (R4000).  */
 269 #define INSN_ISA3                   0x20000000
 270 /* MIPS R4650 instruction.  */
 271 #define INSN_4650                   0x30000000
 272 /* MIPS ISA 4 instruction (R8000).  */
 273 #define INSN_ISA4                   0x40000000
 274 /* LSI R4010 instruction.  */
 275 #define INSN_4010                   0x50000000
 276 /* NEC VR4100 instruction. */
 277 #define INSN_4100                   0x60000000
 278 /* start-sanitize-r5900 */
 279 /* Toshiba R5900 instruction */
 280 #define INSN_5900                   0x70000000
 281 /* end-sanitize-r5900 */
 282
 283 /* Instruction is actually a macro.  It should be ignored by the
 284    disassembler, and requires special treatment by the assembler.  */
 285 #define INSN_MACRO                  0xffffffff
 286
 287 /* This is a list of macro expanded instructions.
 288  *
 289  * _I appended means immediate
 290  * _A appended means address
 291  * _AB appended means address with base register
 292  * _D appended means 64 bit floating point constant
 293  * _S appended means 32 bit floating point constant
 294  */
 295 enum {
 296     M_ABS,
 297     M_ADD_I,
 298     M_ADDU_I,
 299     M_AND_I,
 300     M_BEQ,
 301     M_BEQ_I,
 302     M_BEQL_I,
 303     M_BGE,
 304     M_BGEL,
 305     M_BGE_I,
 306     M_BGEL_I,
 307     M_BGEU,
 308     M_BGEUL,
 309     M_BGEU_I,
 310     M_BGEUL_I,
 311     M_BGT,
 312     M_BGTL,
 313     M_BGT_I,
 314     M_BGTL_I,
 315     M_BGTU,
 316     M_BGTUL,
 317     M_BGTU_I,
 318     M_BGTUL_I,
 319     M_BLE,
 320     M_BLEL,
 321     M_BLE_I,
 322     M_BLEL_I,
 323     M_BLEU,
 324     M_BLEUL,
 325     M_BLEU_I,
 326     M_BLEUL_I,
 327     M_BLT,
 328     M_BLTL,
 329     M_BLT_I,
 330     M_BLTL_I,
 331     M_BLTU,
 332     M_BLTUL,
 333     M_BLTU_I,
 334     M_BLTUL_I,
 335     M_BNE,
 336     M_BNE_I,
 337     M_BNEL_I,
 338     M_DABS,
 339     M_DADD_I,
 340     M_DADDU_I,
 341     M_DDIV_3,
 342     M_DDIV_3I,
 343     M_DDIVU_3,
 344     M_DDIVU_3I,
 345     M_DIV_3,
 346     M_DIV_3I,
 347     M_DIVU_3,
 348     M_DIVU_3I,
 349     M_DLA_AB,
 350     M_DLI,
 351     M_DMUL,
 352     M_DMUL_I,
 353     M_DMULO,
 354     M_DMULO_I,
 355     M_DMULOU,
 356     M_DMULOU_I,
 357     M_DREM_3,
 358     M_DREM_3I,
 359     M_DREMU_3,
 360     M_DREMU_3I,
 361     M_DSUB_I,
 362     M_DSUBU_I,
 363     M_DSUBU_I_2,
 364     M_J_A,
 365     M_JAL_1,
 366     M_JAL_2,
 367     M_JAL_A,
 368     M_L_DOB,
 369     M_L_DAB,
 370     M_LA_AB,
 371     M_LB_A,
 372     M_LB_AB,
 373     M_LBU_A,
 374     M_LBU_AB,
 375     M_LD_A,
 376     M_LD_OB,
 377     M_LD_AB,
 378     M_LDC1_AB,
 379     M_LDC2_AB,
 380     M_LDC3_AB,
 381     M_LDL_AB,
 382     M_LDR_AB,
 383     M_LH_A,
 384     M_LH_AB,
 385     M_LHU_A,
 386     M_LHU_AB,
 387     M_LI,
 388     M_LI_D,
 389     M_LI_DD,
 390     M_LI_S,
 391     M_LI_SS,
 392     M_LL_AB,
 393     M_LLD_AB,
 394     M_LS_A,
 395     M_LW_A,
 396     M_LW_AB,
 397     M_LWC0_A,
 398     M_LWC0_AB,
 399     M_LWC1_A,
 400     M_LWC1_AB,
 401     M_LWC2_A,
 402     M_LWC2_AB,
 403     M_LWC3_A,
 404     M_LWC3_AB,
 405     M_LWL_A,
 406     M_LWL_AB,
 407     M_LWR_A,
 408     M_LWR_AB,
 409     M_LWU_AB,
 410     M_MUL,
 411     M_MUL_I,
 412     M_MULO,
 413     M_MULO_I,
 414     M_MULOU,
 415     M_MULOU_I,
 416     M_NOR_I,
 417     M_OR_I,
 418     M_REM_3,
 419     M_REM_3I,
 420     M_REMU_3,
 421     M_REMU_3I,
 422     M_ROL,
 423     M_ROL_I,
 424     M_ROR,
 425     M_ROR_I,
 426     M_S_DA,
 427     M_S_DOB,
 428     M_S_DAB,
 429     M_S_S,
 430     M_SC_AB,
 431     M_SCD_AB,
 432     M_SD_A,
 433     M_SD_OB,
 434     M_SD_AB,
 435     M_SDC1_AB,
 436     M_SDC2_AB,
 437     M_SDC3_AB,
 438     M_SDL_AB,
 439     M_SDR_AB,
 440     M_SEQ,
 441     M_SEQ_I,
 442     M_SGE,
 443     M_SGE_I,
 444     M_SGEU,
 445     M_SGEU_I,
 446     M_SGT,
 447     M_SGT_I,
 448     M_SGTU,
 449     M_SGTU_I,
 450     M_SLE,
 451     M_SLE_I,
 452     M_SLEU,
 453     M_SLEU_I,
 454     M_SLT_I,
 455     M_SLTU_I,
 456     M_SNE,
 457     M_SNE_I,
 458     M_SB_A,
 459     M_SB_AB,
 460     M_SH_A,
 461     M_SH_AB,
 462     M_SW_A,
 463     M_SW_AB,
 464     M_SWC0_A,
 465     M_SWC0_AB,
 466     M_SWC1_A,
 467     M_SWC1_AB,
 468     M_SWC2_A,
 469     M_SWC2_AB,
 470     M_SWC3_A,
 471     M_SWC3_AB,
 472     M_SWL_A,
 473     M_SWL_AB,
 474     M_SWR_A,
 475     M_SWR_AB,
 476     M_SUB_I,
 477     M_SUBU_I,
 478     M_SUBU_I_2,
 479     M_TEQ_I,
 480     M_TGE_I,
 481     M_TGEU_I,
 482     M_TLT_I,
 483     M_TLTU_I,
 484     M_TNE_I,
 485     M_TRUNCWD,
 486     M_TRUNCWS,
 487     M_ULD,
 488     M_ULD_A,
 489     M_ULH,
 490     M_ULH_A,
 491     M_ULHU,
 492     M_ULHU_A,
 493     M_ULW,
 494     M_ULW_A,
 495     M_USH,
 496     M_USH_A,
 497     M_USW,
 498     M_USW_A,
 499     M_USD,
 500     M_USD_A,
 501     M_XOR_I,
 502     M_COP0,
 503     M_COP1,
 504     M_COP2,
 505     M_COP3,
 506     M_NUM_MACROS
 507 };
 508
 509
 510 /* The order of overloaded instructions matters.  Label arguments and
 511    register arguments look the same. Instructions that can have either
 512    for arguments must apear in the correct order in this table for the
 513    assembler to pick the right one. In other words, entries with
 514    immediate operands must apear after the same instruction with
 515    registers.
 516
 517    Many instructions are short hand for other instructions (i.e., The
 518    jal <register> instruction is short for jalr <register>).  */
 519
 520 extern const struct mips_opcode mips_builtin_opcodes[];
 521 extern const int bfd_mips_num_builtin_opcodes;
 522 extern struct mips_opcode *mips_opcodes;
 523 extern int bfd_mips_num_opcodes;
 524 #define NUMOPCODES bfd_mips_num_opcodes
 525
 526 \f
 527 /* The rest of this file adds definitions for the mips16 TinyRISC
 528    processor.  */
 529
 530 /* These are the bitmasks and shift counts used for the different
 531    fields in the instruction formats.  Other than OP, no masks are
 532    provided for the fixed portions of an instruction, since they are
 533    not needed.
 534
 535    The I format uses IMM11.
 536
 537    The RI format uses RX and IMM8.
 538
 539    The RR format uses RX, and RY.
 540
 541    The RRI format uses RX, RY, and IMM5.
 542
 543    The RRR format uses RX, RY, and RZ.
 544
 545    The RRI_A format uses RX, RY, and IMM4.
 546
 547    The SHIFT format uses RX, RY, and SHAMT.
 548
 549    The I8 format uses IMM8.
 550
 551    The I8_MOVR32 format uses RY and REGR32.
 552
 553    The IR_MOV32R format uses REG32R and MOV32Z.
 554
 555    The I64 format uses IMM8.
 556
 557    The RI64 format uses RY and IMM5.
 558    */
 559
 560 #define MIPS16OP_MASK_OP        0x1f
 561 #define MIPS16OP_SH_OP          11
 562 #define MIPS16OP_MASK_IMM11     0x7ff
 563 #define MIPS16OP_SH_IMM11       0
 564 #define MIPS16OP_MASK_RX        0x7
 565 #define MIPS16OP_SH_RX          8
 566 #define MIPS16OP_MASK_IMM8      0xff
 567 #define MIPS16OP_SH_IMM8        0
 568 #define MIPS16OP_MASK_RY        0x7
 569 #define MIPS16OP_SH_RY          5
 570 #define MIPS16OP_MASK_IMM5      0x1f
 571 #define MIPS16OP_SH_IMM5        0
 572 #define MIPS16OP_MASK_RZ        0x7
 573 #define MIPS16OP_SH_RZ          2
 574 #define MIPS16OP_MASK_IMM4      0xf
 575 #define MIPS16OP_SH_IMM4        0
 576 #define MIPS16OP_MASK_REGR32    0x1f
 577 #define MIPS16OP_SH_REGR32      0
 578 #define MIPS16OP_MASK_REG32R    0x1f
 579 #define MIPS16OP_SH_REG32R      3
 580 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 581 #define MIPS16OP_MASK_MOVE32Z   0x7
 582 #define MIPS16OP_SH_MOVE32Z     0
 583 #define MIPS16OP_MASK_IMM6      0x3f
 584 #define MIPS16OP_SH_IMM6        5
 585
 586 /* These are the characters which may appears in the args field of an
 587    instruction.  They appear in the order in which the fields appear
 588    when the instruction is used.  Commas and parentheses in the args
 589    string are ignored when assembling, and written into the output
 590    when disassembling.
 591
 592    "y" 3 bit register (MIPS16OP_*_RY)
 593    "x" 3 bit register (MIPS16OP_*_RX)
 594    "z" 3 bit register (MIPS16OP_*_RZ)
 595    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 596    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 597    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 598    "0" zero register ($0)
 599    "S" stack pointer ($sp or $29)
 600    "P" program counter
 601    "R" return address register ($ra or $31)
 602    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 603    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 604    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 605    "a" 26 bit jump address
 606    "e" 11 bit extension value
 607    "l" register list for entry instruction
 608    "L" register list for exit instruction
 609
 610    The remaining codes may be extended.  Except as otherwise noted,
 611    the full extended operand is a 16 bit signed value.
 612    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 613    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 614    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 615    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 616    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 617    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 618    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 619    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 620    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 621    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 622    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 623    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 624    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 625    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 626    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 627    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 628    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 629    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 630    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 631    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 632    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 633    */
 634
 635 /* For the mips16, we use the same opcode table format and a few of
 636    the same flags.  However, most of the flags are different.  */
 637
 638 /* Modifies the register in MIPS16OP_*_RX.  */
 639 #define MIPS16_INSN_WRITE_X                 0x00000001
 640 /* Modifies the register in MIPS16OP_*_RY.  */
 641 #define MIPS16_INSN_WRITE_Y                 0x00000002
 642 /* Modifies the register in MIPS16OP_*_RZ.  */
 643 #define MIPS16_INSN_WRITE_Z                 0x00000004
 644 /* Modifies the T ($24) register.  */
 645 #define MIPS16_INSN_WRITE_T                 0x00000008
 646 /* Modifies the SP ($29) register.  */
 647 #define MIPS16_INSN_WRITE_SP                0x00000010
 648 /* Modifies the RA ($31) register.  */
 649 #define MIPS16_INSN_WRITE_31                0x00000020
 650 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 651 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 652 /* Reads the register in MIPS16OP_*_RX.  */
 653 #define MIPS16_INSN_READ_X                  0x00000080
 654 /* Reads the register in MIPS16OP_*_RY.  */
 655 #define MIPS16_INSN_READ_Y                  0x00000100
 656 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 657 #define MIPS16_INSN_READ_Z                  0x00000200
 658 /* Reads the T ($24) register.  */
 659 #define MIPS16_INSN_READ_T                  0x00000400
 660 /* Reads the SP ($29) register.  */
 661 #define MIPS16_INSN_READ_SP                 0x00000800
 662 /* Reads the RA ($31) register.  */
 663 #define MIPS16_INSN_READ_31                 0x00001000
 664 /* Reads the program counter.  */
 665 #define MIPS16_INSN_READ_PC                 0x00002000
 666 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 667 #define MIPS16_INSN_READ_GPR_X              0x00004000
 668
 669 /* The following flags have the same value for the mips16 opcode
 670    table:
 671    INSN_UNCOND_BRANCH_DELAY
 672    INSN_COND_BRANCH_DELAY
 673    INSN_COND_BRANCH_LIKELY (never used)
 674    INSN_READ_HI
 675    INSN_READ_LO
 676    INSN_WRITE_HI
 677    INSN_WRITE_LO
 678    INSN_TRAP
 679    INSN_ISA3
 680    */
 681
 682 extern const struct mips_opcode mips16_opcodes[];
 683 extern const int bfd_mips16_num_opcodes;
 684
 685 #endif /* _MIPS_H_ */