include/opcode/mips.h

   1 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
   2    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by Ralph Campbell and OSF
   5    Commented and modified by Ian Lance Taylor, Cygnus Support
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 GDB, GAS, and the GNU binutils are free software; you can redistribute
  10 them and/or modify them under the terms of the GNU General Public
  11 License as published by the Free Software Foundation; either version
  12 1, or (at your option) any later version.
  13
  14 GDB, GAS, and the GNU binutils are distributed in the hope that they
  15 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  16 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  17 the GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this file; see the file COPYING.  If not, write to the Free
  21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  22
  23 #ifndef _MIPS_H_
  24 #define _MIPS_H_
  25
  26 /* These are bit masks and shift counts to use to access the various
  27    fields of an instruction.  To retrieve the X field of an
  28    instruction, use the expression
  29         (i >> OP_SH_X) & OP_MASK_X
  30    To set the same field (to j), use
  31         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  32
  33    Make sure you use fields that are appropriate for the instruction,
  34    of course.
  35
  36    The 'i' format uses OP, RS, RT and IMMEDIATE.
  37
  38    The 'j' format uses OP and TARGET.
  39
  40    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  41
  42    The 'b' format uses OP, RS, RT and DELTA.
  43
  44    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  45
  46    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  47
  48    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  49    breakpoint instruction are not defined; Kane says the breakpoint
  50    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  51    only use ten bits).  An optional two-operand form of break/sdbbp
  52    allows the lower ten bits to be set too, and MIPS32 and later
  53    architectures allow 20 bits to be set with a signal operand
  54    (using CODE20).
  55
  56    The syscall instruction uses CODE20.
  57
  58    The general coprocessor instructions use COPZ.  */
  59
  60 #define OP_MASK_OP              0x3f
  61 #define OP_SH_OP                26
  62 #define OP_MASK_RS              0x1f
  63 #define OP_SH_RS                21
  64 #define OP_MASK_FR              0x1f
  65 #define OP_SH_FR                21
  66 #define OP_MASK_FMT             0x1f
  67 #define OP_SH_FMT               21
  68 #define OP_MASK_BCC             0x7
  69 #define OP_SH_BCC               18
  70 #define OP_MASK_CODE            0x3ff
  71 #define OP_SH_CODE              16
  72 #define OP_MASK_CODE2           0x3ff
  73 #define OP_SH_CODE2             6
  74 #define OP_MASK_RT              0x1f
  75 #define OP_SH_RT                16
  76 #define OP_MASK_FT              0x1f
  77 #define OP_SH_FT                16
  78 #define OP_MASK_CACHE           0x1f
  79 #define OP_SH_CACHE             16
  80 #define OP_MASK_RD              0x1f
  81 #define OP_SH_RD                11
  82 #define OP_MASK_FS              0x1f
  83 #define OP_SH_FS                11
  84 #define OP_MASK_PREFX           0x1f
  85 #define OP_SH_PREFX             11
  86 #define OP_MASK_CCC             0x7
  87 #define OP_SH_CCC               8
  88 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
  89 #define OP_SH_CODE20            6
  90 #define OP_MASK_SHAMT           0x1f
  91 #define OP_SH_SHAMT             6
  92 #define OP_MASK_FD              0x1f
  93 #define OP_SH_FD                6
  94 #define OP_MASK_TARGET          0x3ffffff
  95 #define OP_SH_TARGET            0
  96 #define OP_MASK_COPZ            0x1ffffff
  97 #define OP_SH_COPZ              0
  98 #define OP_MASK_IMMEDIATE       0xffff
  99 #define OP_SH_IMMEDIATE         0
 100 #define OP_MASK_DELTA           0xffff
 101 #define OP_SH_DELTA             0
 102 #define OP_MASK_FUNCT           0x3f
 103 #define OP_SH_FUNCT             0
 104 #define OP_MASK_SPEC            0x3f
 105 #define OP_SH_SPEC              0
 106 #define OP_SH_LOCC              8       /* FP condition code.  */
 107 #define OP_SH_HICC              18      /* FP condition code.  */
 108 #define OP_MASK_CC              0x7
 109 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 110 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 111 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 112 #define OP_MASK_COP1SPEC        0xf
 113 #define OP_MASK_COP1SCLR        0x4
 114 #define OP_MASK_COP1CMP         0x3
 115 #define OP_SH_COP1CMP           4
 116 #define OP_SH_FORMAT            21      /* FP short format field.  */
 117 #define OP_MASK_FORMAT          0x7
 118 #define OP_SH_TRUE              16
 119 #define OP_MASK_TRUE            0x1
 120 #define OP_SH_GE                17
 121 #define OP_MASK_GE              0x01
 122 #define OP_SH_UNSIGNED          16
 123 #define OP_MASK_UNSIGNED        0x1
 124 #define OP_SH_HINT              16
 125 #define OP_MASK_HINT            0x1f
 126 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 127 #define OP_MASK_MMI             0x3f
 128 #define OP_SH_MMISUB            6
 129 #define OP_MASK_MMISUB          0x1f
 130 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 131 #define OP_SH_PERFREG           1
 132 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 133 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 134 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 135 #define OP_MASK_CODE19          0x7ffff
 136 #define OP_SH_ALN               21
 137 #define OP_MASK_ALN             0x7
 138 #define OP_SH_VSEL              21
 139 #define OP_MASK_VSEL            0x1f
 140 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 141                                            but 0x8-0xf don't select bytes.  */
 142 #define OP_SH_VECBYTE           22
 143 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 144 #define OP_SH_VECALIGN          21
 145
 146 /* Values in the 'VSEL' field.  */
 147 #define MDMX_FMTSEL_IMM_QH      0x1d
 148 #define MDMX_FMTSEL_IMM_OB      0x1e
 149 #define MDMX_FMTSEL_VEC_QH      0x15
 150 #define MDMX_FMTSEL_VEC_OB      0x16
 151
 152 /* This structure holds information for a particular instruction.  */
 153
 154 struct mips_opcode
 155 {
 156   /* The name of the instruction.  */
 157   const char *name;
 158   /* A string describing the arguments for this instruction.  */
 159   const char *args;
 160   /* The basic opcode for the instruction.  When assembling, this
 161      opcode is modified by the arguments to produce the actual opcode
 162      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 163   unsigned long match;
 164   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 165      relevant portions of the opcode when disassembling.  If the
 166      actual opcode anded with the match field equals the opcode field,
 167      then we have found the correct instruction.  If pinfo is
 168      INSN_MACRO, then this field is the macro identifier.  */
 169   unsigned long mask;
 170   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 171      of bits describing the instruction, notably any relevant hazard
 172      information.  */
 173   unsigned long pinfo;
 174   /* A collection of bits describing the instruction sets of which this
 175      instruction or macro is a member. */
 176   unsigned long membership;
 177 };
 178
 179 /* These are the characters which may appears in the args field of an
 180    instruction.  They appear in the order in which the fields appear
 181    when the instruction is used.  Commas and parentheses in the args
 182    string are ignored when assembling, and written into the output
 183    when disassembling.
 184
 185    Each of these characters corresponds to a mask field defined above.
 186
 187    "<" 5 bit shift amount (OP_*_SHAMT)
 188    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 189    "a" 26 bit target address (OP_*_TARGET)
 190    "b" 5 bit base register (OP_*_RS)
 191    "c" 10 bit breakpoint code (OP_*_CODE)
 192    "d" 5 bit destination register specifier (OP_*_RD)
 193    "h" 5 bit prefx hint (OP_*_PREFX)
 194    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 195    "j" 16 bit signed immediate (OP_*_DELTA)
 196    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 197        Also used for immediate operands in vr5400 vector insns.
 198    "o" 16 bit signed offset (OP_*_DELTA)
 199    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 200    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 201    "r" 5 bit same register used as both source and target (OP_*_RS)
 202    "s" 5 bit source register specifier (OP_*_RS)
 203    "t" 5 bit target register (OP_*_RT)
 204    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 205    "v" 5 bit same register used as both source and destination (OP_*_RS)
 206    "w" 5 bit same register used as both target and destination (OP_*_RT)
 207    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 208        (used by clo and clz)
 209    "C" 25 bit coprocessor function code (OP_*_COPZ)
 210    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 211    "J" 19 bit wait function code (OP_*_CODE19)
 212    "x" accept and ignore register name
 213    "z" must be zero register
 214
 215    Floating point instructions:
 216    "D" 5 bit destination register (OP_*_FD)
 217    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 218    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 219    "S" 5 bit fs source 1 register (OP_*_FS)
 220    "T" 5 bit ft source 2 register (OP_*_FT)
 221    "R" 5 bit fr source 3 register (OP_*_FR)
 222    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 223    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 224
 225    Coprocessor instructions:
 226    "E" 5 bit target register (OP_*_RT)
 227    "G" 5 bit destination register (OP_*_RD)
 228    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 229    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 230    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 231    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 232    see also "k" above
 233
 234    Macro instructions:
 235    "A" General 32 bit expression
 236    "I" 32 bit immediate
 237    "F" 64 bit floating point constant in .rdata
 238    "L" 64 bit floating point constant in .lit8
 239    "f" 32 bit floating point constant
 240    "l" 32 bit floating point constant in .lit4
 241
 242    MDMX instruction operands (note that while these use the FP register
 243    fields, they accept both $fN and $vN names for the registers):
 244    "O"  MDMX alignment offset (OP_*_ALN)
 245    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 246    "X"  MDMX destination register (OP_*_FD)
 247    "Y"  MDMX source register (OP_*_FS)
 248    "Z"  MDMX source register (OP_*_FT)
 249
 250    Other:
 251    "()" parens surrounding optional value
 252    ","  separates operands
 253    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 254
 255    Characters used so far, for quick reference when adding more:
 256    "%[]<>(),"
 257    "ABCDEFGHIJLMNOPQRSTUVWXYZ"
 258    "abcdefhijklopqrstuvwxz"
 259 */
 260
 261 /* These are the bits which may be set in the pinfo field of an
 262    instructions, if it is not equal to INSN_MACRO.  */
 263
 264 /* Modifies the general purpose register in OP_*_RD.  */
 265 #define INSN_WRITE_GPR_D            0x00000001
 266 /* Modifies the general purpose register in OP_*_RT.  */
 267 #define INSN_WRITE_GPR_T            0x00000002
 268 /* Modifies general purpose register 31.  */
 269 #define INSN_WRITE_GPR_31           0x00000004
 270 /* Modifies the floating point register in OP_*_FD.  */
 271 #define INSN_WRITE_FPR_D            0x00000008
 272 /* Modifies the floating point register in OP_*_FS.  */
 273 #define INSN_WRITE_FPR_S            0x00000010
 274 /* Modifies the floating point register in OP_*_FT.  */
 275 #define INSN_WRITE_FPR_T            0x00000020
 276 /* Reads the general purpose register in OP_*_RS.  */
 277 #define INSN_READ_GPR_S             0x00000040
 278 /* Reads the general purpose register in OP_*_RT.  */
 279 #define INSN_READ_GPR_T             0x00000080
 280 /* Reads the floating point register in OP_*_FS.  */
 281 #define INSN_READ_FPR_S             0x00000100
 282 /* Reads the floating point register in OP_*_FT.  */
 283 #define INSN_READ_FPR_T             0x00000200
 284 /* Reads the floating point register in OP_*_FR.  */
 285 #define INSN_READ_FPR_R             0x00000400
 286 /* Modifies coprocessor condition code.  */
 287 #define INSN_WRITE_COND_CODE        0x00000800
 288 /* Reads coprocessor condition code.  */
 289 #define INSN_READ_COND_CODE         0x00001000
 290 /* TLB operation.  */
 291 #define INSN_TLB                    0x00002000
 292 /* Reads coprocessor register other than floating point register.  */
 293 #define INSN_COP                    0x00004000
 294 /* Instruction loads value from memory, requiring delay.  */
 295 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 296 /* Instruction loads value from coprocessor, requiring delay.  */
 297 #define INSN_LOAD_COPROC_DELAY      0x00010000
 298 /* Instruction has unconditional branch delay slot.  */
 299 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 300 /* Instruction has conditional branch delay slot.  */
 301 #define INSN_COND_BRANCH_DELAY      0x00040000
 302 /* Conditional branch likely: if branch not taken, insn nullified.  */
 303 #define INSN_COND_BRANCH_LIKELY     0x00080000
 304 /* Moves to coprocessor register, requiring delay.  */
 305 #define INSN_COPROC_MOVE_DELAY      0x00100000
 306 /* Loads coprocessor register from memory, requiring delay.  */
 307 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 308 /* Reads the HI register.  */
 309 #define INSN_READ_HI                0x00400000
 310 /* Reads the LO register.  */
 311 #define INSN_READ_LO                0x00800000
 312 /* Modifies the HI register.  */
 313 #define INSN_WRITE_HI               0x01000000
 314 /* Modifies the LO register.  */
 315 #define INSN_WRITE_LO               0x02000000
 316 /* Takes a trap (easier to keep out of delay slot).  */
 317 #define INSN_TRAP                   0x04000000
 318 /* Instruction stores value into memory.  */
 319 #define INSN_STORE_MEMORY           0x08000000
 320 /* Instruction uses single precision floating point.  */
 321 #define FP_S                        0x10000000
 322 /* Instruction uses double precision floating point.  */
 323 #define FP_D                        0x20000000
 324 /* Instruction is part of the tx39's integer multiply family.    */
 325 #define INSN_MULT                   0x40000000
 326 /* Instruction synchronize shared memory.  */
 327 #define INSN_SYNC                   0x80000000
 328 /* Instruction reads MDMX accumulator.  XXX FIXME: No bits left!  */
 329 #define INSN_READ_MDMX_ACC          0
 330 /* Instruction writes MDMX accumulator.  XXX FIXME: No bits left!  */
 331 #define INSN_WRITE_MDMX_ACC         0
 332
 333 /* Instruction is actually a macro.  It should be ignored by the
 334    disassembler, and requires special treatment by the assembler.  */
 335 #define INSN_MACRO                  0xffffffff
 336
 337 /* Masks used to mark instructions to indicate which MIPS ISA level
 338    they were introduced in.  ISAs, as defined below, are logical
 339    ORs of these bits, indicatingthat they support the instructions
 340    defined at the given level.  */
 341
 342 #define INSN_ISA_MASK             0x00000fff
 343 #define INSN_ISA1                 0x00000010
 344 #define INSN_ISA2                 0x00000020
 345 #define INSN_ISA3                 0x00000040
 346 #define INSN_ISA4                 0x00000080
 347 #define INSN_ISA5                 0x00000100
 348 #define INSN_ISA32                0x00000200
 349 #define INSN_ISA64                0x00000400
 350
 351 /* Masks used for MIPS-defined ASEs.  */
 352 #define INSN_ASE_MASK             0x0000f000
 353
 354 /* MIPS 16 ASE */
 355 #define INSN_MIPS16               0x00002000
 356 /* MIPS-3D ASE */
 357 #define INSN_MIPS3D               0x00004000
 358 /* MDMX ASE */
 359 #define INSN_MDMX                 0x00008000
 360
 361 /* Chip specific instructions.  These are bitmasks.  */
 362
 363 /* MIPS R4650 instruction.  */
 364 #define INSN_4650                 0x00010000
 365 /* LSI R4010 instruction.  */
 366 #define INSN_4010                 0x00020000
 367 /* NEC VR4100 instruction.  */
 368 #define INSN_4100                 0x00040000
 369 /* Toshiba R3900 instruction.  */
 370 #define INSN_3900                 0x00080000
 371 /* MIPS R10000 instruction.  */
 372 #define INSN_10000                0x00100000
 373 /* Broadcom SB-1 instruction.  */
 374 #define INSN_SB1                  0x00200000
 375 /* NEC VR4111/VR4181 instruction.  */
 376 #define INSN_4111                 0x00400000
 377 /* NEC VR4120 instruction.  */
 378 #define INSN_4120                 0x00800000
 379 /* NEC VR5400 instruction.  */
 380 #define INSN_5400                 0x01000000
 381 /* NEC VR5500 instruction.  */
 382 #define INSN_5500                 0x02000000
 383
 384 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 385
 386 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 387 #define       ISA_MIPS1       (INSN_ISA1)
 388 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 389 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 390 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 391 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 392 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 393 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 394
 395 /* CPU defines, use instead of hardcoding processor number. Keep this
 396    in sync with bfd/archures.c in order for machine selection to work.  */
 397 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 398 #define CPU_R3000       3000
 399 #define CPU_R3900       3900
 400 #define CPU_R4000       4000
 401 #define CPU_R4010       4010
 402 #define CPU_VR4100      4100
 403 #define CPU_R4111       4111
 404 #define CPU_VR4120      4120
 405 #define CPU_R4300       4300
 406 #define CPU_R4400       4400
 407 #define CPU_R4600       4600
 408 #define CPU_R4650       4650
 409 #define CPU_R5000       5000
 410 #define CPU_VR5400      5400
 411 #define CPU_VR5500      5500
 412 #define CPU_R6000       6000
 413 #define CPU_R8000       8000
 414 #define CPU_R10000      10000
 415 #define CPU_R12000      12000
 416 #define CPU_MIPS16      16
 417 #define CPU_MIPS32      32
 418 #define CPU_MIPS5       5
 419 #define CPU_MIPS64      64
 420 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 421
 422 /* Test for membership in an ISA including chip specific ISAs.  INSN
 423    is pointer to an element of the opcode table; ISA is the specified
 424    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 425    test, or zero if no CPU specific ISA test is desired.  */
 426
 427 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 428     (((insn)->membership & isa) != 0                                    \
 429      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 430      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 431      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 432      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 433      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 434          && ((insn)->membership & INSN_10000) != 0)                     \
 435      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 436      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 437      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 438      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 439      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 440      || 0)      /* Please keep this term for easier source merging.  */
 441
 442 /* This is a list of macro expanded instructions.
 443
 444    _I appended means immediate
 445    _A appended means address
 446    _AB appended means address with base register
 447    _D appended means 64 bit floating point constant
 448    _S appended means 32 bit floating point constant.  */
 449
 450 enum
 451 {
 452   M_ABS,
 453   M_ADD_I,
 454   M_ADDU_I,
 455   M_AND_I,
 456   M_BEQ,
 457   M_BEQ_I,
 458   M_BEQL_I,
 459   M_BGE,
 460   M_BGEL,
 461   M_BGE_I,
 462   M_BGEL_I,
 463   M_BGEU,
 464   M_BGEUL,
 465   M_BGEU_I,
 466   M_BGEUL_I,
 467   M_BGT,
 468   M_BGTL,
 469   M_BGT_I,
 470   M_BGTL_I,
 471   M_BGTU,
 472   M_BGTUL,
 473   M_BGTU_I,
 474   M_BGTUL_I,
 475   M_BLE,
 476   M_BLEL,
 477   M_BLE_I,
 478   M_BLEL_I,
 479   M_BLEU,
 480   M_BLEUL,
 481   M_BLEU_I,
 482   M_BLEUL_I,
 483   M_BLT,
 484   M_BLTL,
 485   M_BLT_I,
 486   M_BLTL_I,
 487   M_BLTU,
 488   M_BLTUL,
 489   M_BLTU_I,
 490   M_BLTUL_I,
 491   M_BNE,
 492   M_BNE_I,
 493   M_BNEL_I,
 494   M_DABS,
 495   M_DADD_I,
 496   M_DADDU_I,
 497   M_DDIV_3,
 498   M_DDIV_3I,
 499   M_DDIVU_3,
 500   M_DDIVU_3I,
 501   M_DIV_3,
 502   M_DIV_3I,
 503   M_DIVU_3,
 504   M_DIVU_3I,
 505   M_DLA_AB,
 506   M_DLI,
 507   M_DMUL,
 508   M_DMUL_I,
 509   M_DMULO,
 510   M_DMULO_I,
 511   M_DMULOU,
 512   M_DMULOU_I,
 513   M_DREM_3,
 514   M_DREM_3I,
 515   M_DREMU_3,
 516   M_DREMU_3I,
 517   M_DSUB_I,
 518   M_DSUBU_I,
 519   M_DSUBU_I_2,
 520   M_J_A,
 521   M_JAL_1,
 522   M_JAL_2,
 523   M_JAL_A,
 524   M_L_DOB,
 525   M_L_DAB,
 526   M_LA_AB,
 527   M_LB_A,
 528   M_LB_AB,
 529   M_LBU_A,
 530   M_LBU_AB,
 531   M_LD_A,
 532   M_LD_OB,
 533   M_LD_AB,
 534   M_LDC1_AB,
 535   M_LDC2_AB,
 536   M_LDC3_AB,
 537   M_LDL_AB,
 538   M_LDR_AB,
 539   M_LH_A,
 540   M_LH_AB,
 541   M_LHU_A,
 542   M_LHU_AB,
 543   M_LI,
 544   M_LI_D,
 545   M_LI_DD,
 546   M_LI_S,
 547   M_LI_SS,
 548   M_LL_AB,
 549   M_LLD_AB,
 550   M_LS_A,
 551   M_LW_A,
 552   M_LW_AB,
 553   M_LWC0_A,
 554   M_LWC0_AB,
 555   M_LWC1_A,
 556   M_LWC1_AB,
 557   M_LWC2_A,
 558   M_LWC2_AB,
 559   M_LWC3_A,
 560   M_LWC3_AB,
 561   M_LWL_A,
 562   M_LWL_AB,
 563   M_LWR_A,
 564   M_LWR_AB,
 565   M_LWU_AB,
 566   M_MOVE,
 567   M_MUL,
 568   M_MUL_I,
 569   M_MULO,
 570   M_MULO_I,
 571   M_MULOU,
 572   M_MULOU_I,
 573   M_NOR_I,
 574   M_OR_I,
 575   M_REM_3,
 576   M_REM_3I,
 577   M_REMU_3,
 578   M_REMU_3I,
 579   M_DROL,
 580   M_ROL,
 581   M_DROL_I,
 582   M_ROL_I,
 583   M_DROR,
 584   M_ROR,
 585   M_DROR_I,
 586   M_ROR_I,
 587   M_S_DA,
 588   M_S_DOB,
 589   M_S_DAB,
 590   M_S_S,
 591   M_SC_AB,
 592   M_SCD_AB,
 593   M_SD_A,
 594   M_SD_OB,
 595   M_SD_AB,
 596   M_SDC1_AB,
 597   M_SDC2_AB,
 598   M_SDC3_AB,
 599   M_SDL_AB,
 600   M_SDR_AB,
 601   M_SEQ,
 602   M_SEQ_I,
 603   M_SGE,
 604   M_SGE_I,
 605   M_SGEU,
 606   M_SGEU_I,
 607   M_SGT,
 608   M_SGT_I,
 609   M_SGTU,
 610   M_SGTU_I,
 611   M_SLE,
 612   M_SLE_I,
 613   M_SLEU,
 614   M_SLEU_I,
 615   M_SLT_I,
 616   M_SLTU_I,
 617   M_SNE,
 618   M_SNE_I,
 619   M_SB_A,
 620   M_SB_AB,
 621   M_SH_A,
 622   M_SH_AB,
 623   M_SW_A,
 624   M_SW_AB,
 625   M_SWC0_A,
 626   M_SWC0_AB,
 627   M_SWC1_A,
 628   M_SWC1_AB,
 629   M_SWC2_A,
 630   M_SWC2_AB,
 631   M_SWC3_A,
 632   M_SWC3_AB,
 633   M_SWL_A,
 634   M_SWL_AB,
 635   M_SWR_A,
 636   M_SWR_AB,
 637   M_SUB_I,
 638   M_SUBU_I,
 639   M_SUBU_I_2,
 640   M_TEQ_I,
 641   M_TGE_I,
 642   M_TGEU_I,
 643   M_TLT_I,
 644   M_TLTU_I,
 645   M_TNE_I,
 646   M_TRUNCWD,
 647   M_TRUNCWS,
 648   M_ULD,
 649   M_ULD_A,
 650   M_ULH,
 651   M_ULH_A,
 652   M_ULHU,
 653   M_ULHU_A,
 654   M_ULW,
 655   M_ULW_A,
 656   M_USH,
 657   M_USH_A,
 658   M_USW,
 659   M_USW_A,
 660   M_USD,
 661   M_USD_A,
 662   M_XOR_I,
 663   M_COP0,
 664   M_COP1,
 665   M_COP2,
 666   M_COP3,
 667   M_NUM_MACROS
 668 };
 669
 670
 671 /* The order of overloaded instructions matters.  Label arguments and
 672    register arguments look the same. Instructions that can have either
 673    for arguments must apear in the correct order in this table for the
 674    assembler to pick the right one. In other words, entries with
 675    immediate operands must apear after the same instruction with
 676    registers.
 677
 678    Many instructions are short hand for other instructions (i.e., The
 679    jal <register> instruction is short for jalr <register>).  */
 680
 681 extern const struct mips_opcode mips_builtin_opcodes[];
 682 extern const int bfd_mips_num_builtin_opcodes;
 683 extern struct mips_opcode *mips_opcodes;
 684 extern int bfd_mips_num_opcodes;
 685 #define NUMOPCODES bfd_mips_num_opcodes
 686
 687 \f
 688 /* The rest of this file adds definitions for the mips16 TinyRISC
 689    processor.  */
 690
 691 /* These are the bitmasks and shift counts used for the different
 692    fields in the instruction formats.  Other than OP, no masks are
 693    provided for the fixed portions of an instruction, since they are
 694    not needed.
 695
 696    The I format uses IMM11.
 697
 698    The RI format uses RX and IMM8.
 699
 700    The RR format uses RX, and RY.
 701
 702    The RRI format uses RX, RY, and IMM5.
 703
 704    The RRR format uses RX, RY, and RZ.
 705
 706    The RRI_A format uses RX, RY, and IMM4.
 707
 708    The SHIFT format uses RX, RY, and SHAMT.
 709
 710    The I8 format uses IMM8.
 711
 712    The I8_MOVR32 format uses RY and REGR32.
 713
 714    The IR_MOV32R format uses REG32R and MOV32Z.
 715
 716    The I64 format uses IMM8.
 717
 718    The RI64 format uses RY and IMM5.
 719    */
 720
 721 #define MIPS16OP_MASK_OP        0x1f
 722 #define MIPS16OP_SH_OP          11
 723 #define MIPS16OP_MASK_IMM11     0x7ff
 724 #define MIPS16OP_SH_IMM11       0
 725 #define MIPS16OP_MASK_RX        0x7
 726 #define MIPS16OP_SH_RX          8
 727 #define MIPS16OP_MASK_IMM8      0xff
 728 #define MIPS16OP_SH_IMM8        0
 729 #define MIPS16OP_MASK_RY        0x7
 730 #define MIPS16OP_SH_RY          5
 731 #define MIPS16OP_MASK_IMM5      0x1f
 732 #define MIPS16OP_SH_IMM5        0
 733 #define MIPS16OP_MASK_RZ        0x7
 734 #define MIPS16OP_SH_RZ          2
 735 #define MIPS16OP_MASK_IMM4      0xf
 736 #define MIPS16OP_SH_IMM4        0
 737 #define MIPS16OP_MASK_REGR32    0x1f
 738 #define MIPS16OP_SH_REGR32      0
 739 #define MIPS16OP_MASK_REG32R    0x1f
 740 #define MIPS16OP_SH_REG32R      3
 741 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 742 #define MIPS16OP_MASK_MOVE32Z   0x7
 743 #define MIPS16OP_SH_MOVE32Z     0
 744 #define MIPS16OP_MASK_IMM6      0x3f
 745 #define MIPS16OP_SH_IMM6        5
 746
 747 /* These are the characters which may appears in the args field of an
 748    instruction.  They appear in the order in which the fields appear
 749    when the instruction is used.  Commas and parentheses in the args
 750    string are ignored when assembling, and written into the output
 751    when disassembling.
 752
 753    "y" 3 bit register (MIPS16OP_*_RY)
 754    "x" 3 bit register (MIPS16OP_*_RX)
 755    "z" 3 bit register (MIPS16OP_*_RZ)
 756    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
 757    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
 758    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
 759    "0" zero register ($0)
 760    "S" stack pointer ($sp or $29)
 761    "P" program counter
 762    "R" return address register ($ra or $31)
 763    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
 764    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
 765    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
 766    "a" 26 bit jump address
 767    "e" 11 bit extension value
 768    "l" register list for entry instruction
 769    "L" register list for exit instruction
 770
 771    The remaining codes may be extended.  Except as otherwise noted,
 772    the full extended operand is a 16 bit signed value.
 773    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
 774    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
 775    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
 776    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
 777    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
 778    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
 779    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
 780    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
 781    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
 782    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
 783    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
 784    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
 785    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
 786    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
 787    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
 788    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
 789    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
 790    "q" 11 bit branch address (MIPS16OP_*_IMM11)
 791    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
 792    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
 793    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
 794    */
 795
 796 /* For the mips16, we use the same opcode table format and a few of
 797    the same flags.  However, most of the flags are different.  */
 798
 799 /* Modifies the register in MIPS16OP_*_RX.  */
 800 #define MIPS16_INSN_WRITE_X                 0x00000001
 801 /* Modifies the register in MIPS16OP_*_RY.  */
 802 #define MIPS16_INSN_WRITE_Y                 0x00000002
 803 /* Modifies the register in MIPS16OP_*_RZ.  */
 804 #define MIPS16_INSN_WRITE_Z                 0x00000004
 805 /* Modifies the T ($24) register.  */
 806 #define MIPS16_INSN_WRITE_T                 0x00000008
 807 /* Modifies the SP ($29) register.  */
 808 #define MIPS16_INSN_WRITE_SP                0x00000010
 809 /* Modifies the RA ($31) register.  */
 810 #define MIPS16_INSN_WRITE_31                0x00000020
 811 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
 812 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
 813 /* Reads the register in MIPS16OP_*_RX.  */
 814 #define MIPS16_INSN_READ_X                  0x00000080
 815 /* Reads the register in MIPS16OP_*_RY.  */
 816 #define MIPS16_INSN_READ_Y                  0x00000100
 817 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
 818 #define MIPS16_INSN_READ_Z                  0x00000200
 819 /* Reads the T ($24) register.  */
 820 #define MIPS16_INSN_READ_T                  0x00000400
 821 /* Reads the SP ($29) register.  */
 822 #define MIPS16_INSN_READ_SP                 0x00000800
 823 /* Reads the RA ($31) register.  */
 824 #define MIPS16_INSN_READ_31                 0x00001000
 825 /* Reads the program counter.  */
 826 #define MIPS16_INSN_READ_PC                 0x00002000
 827 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 828 #define MIPS16_INSN_READ_GPR_X              0x00004000
 829 /* Is a branch insn. */
 830 #define MIPS16_INSN_BRANCH                  0x00010000
 831
 832 /* The following flags have the same value for the mips16 opcode
 833    table:
 834    INSN_UNCOND_BRANCH_DELAY
 835    INSN_COND_BRANCH_DELAY
 836    INSN_COND_BRANCH_LIKELY (never used)
 837    INSN_READ_HI
 838    INSN_READ_LO
 839    INSN_WRITE_HI
 840    INSN_WRITE_LO
 841    INSN_TRAP
 842    INSN_ISA3
 843    */
 844
 845 extern const struct mips_opcode mips16_opcodes[];
 846 extern const int bfd_mips16_num_opcodes;
 847
 848 #endif /* _MIPS_H_ */