include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2023 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC instructions.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
  39     return 8;
  40   /* 80- ... 176-bit instructions.  */
  41   if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
  42     return 10 + ((insn >> 11) & 0xe);
  43   /* Maximum value returned by this function.  */
  44 #define RISCV_MAX_INSN_LEN 22
  45   /* Longer instructions not supported at the moment.  */
  46   return 2;
  47 }
  48
  49 #define RVC_JUMP_BITS 11
  50 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  51
  52 #define RVC_BRANCH_BITS 8
  53 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  54
  55 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  56 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  57 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
  58
  59 #define EXTRACT_ITYPE_IMM(x) \
  60   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  61 #define EXTRACT_STYPE_IMM(x) \
  62   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  63 #define EXTRACT_BTYPE_IMM(x) \
  64   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  65 #define EXTRACT_UTYPE_IMM(x) \
  66   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  67 #define EXTRACT_JTYPE_IMM(x) \
  68   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  69 #define EXTRACT_CITYPE_IMM(x) \
  70   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  71 #define EXTRACT_CITYPE_LUI_IMM(x) \
  72   (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
  73 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  74   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  75 #define EXTRACT_CITYPE_LWSP_IMM(x) \
  76   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  77 #define EXTRACT_CITYPE_LDSP_IMM(x) \
  78   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  79 #define EXTRACT_CSSTYPE_IMM(x) \
  80   (RV_X(x, 7, 6) << 0)
  81 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  82   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  83 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  84   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  85 #define EXTRACT_CIWTYPE_IMM(x) \
  86   (RV_X(x, 5, 8))
  87 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  88   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  89 #define EXTRACT_CLTYPE_IMM(x) \
  90   ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
  91 #define EXTRACT_CLTYPE_LW_IMM(x) \
  92   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  93 #define EXTRACT_CLTYPE_LD_IMM(x) \
  94   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
  95 #define EXTRACT_CBTYPE_IMM(x) \
  96   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
  97 #define EXTRACT_CJTYPE_IMM(x) \
  98   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
  99 #define EXTRACT_RVV_VI_IMM(x) \
 100   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 101 #define EXTRACT_RVV_VI_UIMM(x) \
 102   (RV_X(x, 15, 5))
 103 #define EXTRACT_RVV_VI_UIMM6(x) \
 104   (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
 105 #define EXTRACT_RVV_OFFSET(x) \
 106   (RV_X(x, 29, 3))
 107 #define EXTRACT_RVV_VB_IMM(x) \
 108   (RV_X(x, 20, 10))
 109 #define EXTRACT_RVV_VC_IMM(x) \
 110   (RV_X(x, 20, 11))
 111 #define EXTRACT_ZCB_BYTE_UIMM(x) \
 112   (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
 113 #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
 114   (RV_X(x, 5, 1) << 1)
 115
 116 #define ENCODE_ITYPE_IMM(x) \
 117   (RV_X(x, 0, 12) << 20)
 118 #define ENCODE_STYPE_IMM(x) \
 119   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 120 #define ENCODE_BTYPE_IMM(x) \
 121   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 122 #define ENCODE_UTYPE_IMM(x) \
 123   (RV_X(x, 12, 20) << 12)
 124 #define ENCODE_JTYPE_IMM(x) \
 125   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 126 #define ENCODE_CITYPE_IMM(x) \
 127   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 128 #define ENCODE_CITYPE_LUI_IMM(x) \
 129   ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
 130 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \
 131   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 132 #define ENCODE_CITYPE_LWSP_IMM(x) \
 133   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 134 #define ENCODE_CITYPE_LDSP_IMM(x) \
 135   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 136 #define ENCODE_CSSTYPE_IMM(x) \
 137   (RV_X(x, 0, 6) << 7)
 138 #define ENCODE_CSSTYPE_SWSP_IMM(x) \
 139   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 140 #define ENCODE_CSSTYPE_SDSP_IMM(x) \
 141   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 142 #define ENCODE_CIWTYPE_IMM(x) \
 143   (RV_X(x, 0, 8) << 5)
 144 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
 145   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 146 #define ENCODE_CLTYPE_IMM(x) \
 147   ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
 148 #define ENCODE_CLTYPE_LW_IMM(x) \
 149   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 150 #define ENCODE_CLTYPE_LD_IMM(x) \
 151   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 152 #define ENCODE_CBTYPE_IMM(x) \
 153   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 154 #define ENCODE_CJTYPE_IMM(x) \
 155   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 156 #define ENCODE_RVV_VB_IMM(x) \
 157   (RV_X(x, 0, 10) << 20)
 158 #define ENCODE_RVV_VC_IMM(x) \
 159   (RV_X(x, 0, 11) << 20)
 160 #define ENCODE_RVV_VI_UIMM6(x) \
 161   (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
 162 #define ENCODE_ZCB_BYTE_UIMM(x) \
 163   ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
 164 #define ENCODE_ZCB_HALFWORD_UIMM(x) \
 165   (RV_X(x, 1, 1) << 5)
 166
 167 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 168 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 169 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
 170 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 171 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
 172 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
 173 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
 174                                  && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
 175 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
 176                                       && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
 177 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
 178 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
 179 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
 180 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
 181 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
 182 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
 183 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
 184 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
 185 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
 186 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
 187 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
 188 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 189 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
 190 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
 191 #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
 192 #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
 193
 194 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 195   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 196 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 197   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 198 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 199   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 200 #define RISCV_BTYPE(insn, rs1, rs2, target) \
 201   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
 202 #define RISCV_UTYPE(insn, rd, bigimm) \
 203   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 204 #define RISCV_JTYPE(insn, rd, target) \
 205   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
 206
 207 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 208 #define RVC_NOP MATCH_C_ADDI
 209
 210 #define RISCV_CONST_HIGH_PART(VALUE) \
 211   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 212 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 213 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 214 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 215
 216 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 217 #define RISCV_JUMP_ALIGN_BITS 1
 218 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 219 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 220
 221 #define RISCV_IMM_BITS 12
 222 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 223 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 224 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 225 #define RISCV_RVC_IMM_REACH (1LL << 6)
 226 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 227 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 228 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 229 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 230
 231 /* RV fields.  */
 232
 233 #define OP_MASK_OP              0x7f
 234 #define OP_SH_OP                0
 235 #define OP_MASK_RS2             0x1f
 236 #define OP_SH_RS2               20
 237 #define OP_MASK_RS1             0x1f
 238 #define OP_SH_RS1               15
 239 #define OP_MASK_RS3             0x1fU
 240 #define OP_SH_RS3               27
 241 #define OP_MASK_RD              0x1f
 242 #define OP_SH_RD                7
 243 #define OP_MASK_SHAMT           0x3f
 244 #define OP_SH_SHAMT             20
 245 #define OP_MASK_SHAMTW          0x1f
 246 #define OP_SH_SHAMTW            20
 247 #define OP_MASK_RM              0x7
 248 #define OP_SH_RM                12
 249 #define OP_MASK_PRED            0xf
 250 #define OP_SH_PRED              24
 251 #define OP_MASK_SUCC            0xf
 252 #define OP_SH_SUCC              20
 253 #define OP_MASK_AQ              0x1
 254 #define OP_SH_AQ                26
 255 #define OP_MASK_RL              0x1
 256 #define OP_SH_RL                25
 257
 258 #define OP_MASK_CSR             0xfffU
 259 #define OP_SH_CSR               20
 260
 261 #define OP_MASK_FUNCT3          0x7
 262 #define OP_SH_FUNCT3            12
 263 #define OP_MASK_FUNCT7          0x7fU
 264 #define OP_SH_FUNCT7            25
 265 #define OP_MASK_FUNCT2          0x3
 266 #define OP_SH_FUNCT2            25
 267
 268 /* RVC fields.  */
 269
 270 #define OP_MASK_OP2             0x3
 271 #define OP_SH_OP2               0
 272
 273 #define OP_MASK_CRS2            0x1f
 274 #define OP_SH_CRS2              2
 275 #define OP_MASK_CRS1S           0x7
 276 #define OP_SH_CRS1S             7
 277 #define OP_MASK_CRS2S           0x7
 278 #define OP_SH_CRS2S             2
 279
 280 #define OP_MASK_CFUNCT6         0x3f
 281 #define OP_SH_CFUNCT6           10
 282 #define OP_MASK_CFUNCT4         0xf
 283 #define OP_SH_CFUNCT4           12
 284 #define OP_MASK_CFUNCT3         0x7
 285 #define OP_SH_CFUNCT3           13
 286 #define OP_MASK_CFUNCT2         0x3
 287 #define OP_SH_CFUNCT2           5
 288
 289 /* Scalar crypto fields. */
 290
 291 #define OP_SH_BS        30
 292 #define OP_MASK_BS      3
 293 #define OP_SH_RNUM      20
 294 #define OP_MASK_RNUM    0xf
 295
 296 /* RVV fields.  */
 297
 298 #define OP_MASK_VD              0x1f
 299 #define OP_SH_VD                7
 300 #define OP_MASK_VS1             0x1f
 301 #define OP_SH_VS1               15
 302 #define OP_MASK_VS2             0x1f
 303 #define OP_SH_VS2               20
 304 #define OP_MASK_VIMM            0x1f
 305 #define OP_SH_VIMM              15
 306 #define OP_MASK_VMASK           0x1
 307 #define OP_SH_VMASK             25
 308 #define OP_MASK_VFUNCT6         0x3f
 309 #define OP_SH_VFUNCT6           26
 310 #define OP_MASK_VLMUL           0x7
 311 #define OP_SH_VLMUL             0
 312 #define OP_MASK_VSEW            0x7
 313 #define OP_SH_VSEW              3
 314 #define OP_MASK_VTA             0x1
 315 #define OP_SH_VTA               6
 316 #define OP_MASK_VMA             0x1
 317 #define OP_SH_VMA               7
 318 #define OP_MASK_VWD             0x1
 319 #define OP_SH_VWD               26
 320
 321 #define NVECR 32
 322 #define NVECM 1
 323
 324 /* ABI names for selected x-registers.  */
 325
 326 #define X_RA 1
 327 #define X_SP 2
 328 #define X_GP 3
 329 #define X_TP 4
 330 #define X_T0 5
 331 #define X_T1 6
 332 #define X_T2 7
 333 #define X_T3 28
 334
 335 #define NGPR 32
 336 #define NFPR 32
 337
 338 /* These fake label defines are use by both the assembler, and
 339    libopcodes.  The assembler uses this when it needs to generate a fake
 340    label, and libopcodes uses it to hide the fake labels in its output.  */
 341 #define RISCV_FAKE_LABEL_NAME ".L0 "
 342 #define RISCV_FAKE_LABEL_CHAR ' '
 343
 344 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 345    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 346 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 347   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 348               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 349
 350 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 351    SHIFT places.  */
 352 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 353   (((STRUCT) >> (SHIFT)) & (MASK))
 354
 355 /* Extract the operand given by FIELD from integer INSN.  */
 356 #define EXTRACT_OPERAND(FIELD, INSN) \
 357   ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD))
 358
 359 /* Extract an unsigned immediate operand on position s with n bits.  */
 360 #define EXTRACT_U_IMM(n, s, l) \
 361   RV_X (l, s, n)
 362
 363 /* Extract an signed immediate operand on position s with n bits.  */
 364 #define EXTRACT_S_IMM(n, s, l) \
 365   RV_X_SIGNED (l, s, n)
 366
 367 /* Validate that unsigned n-bit immediate is within bounds.  */
 368 #define VALIDATE_U_IMM(v, n) \
 369   ((unsigned long) v < (1UL << n))
 370
 371 /* Validate that signed n-bit immediate is within bounds.  */
 372 #define VALIDATE_S_IMM(v, n) \
 373   (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
 374
 375 /* The maximal number of subset can be required.  */
 376 #define MAX_SUBSET_NUM 4
 377
 378 /* All RISC-V instructions belong to at least one of these classes.  */
 379 enum riscv_insn_class
 380 {
 381   INSN_CLASS_NONE,
 382
 383   INSN_CLASS_I,
 384   INSN_CLASS_C,
 385   INSN_CLASS_A,
 386   INSN_CLASS_M,
 387   INSN_CLASS_F,
 388   INSN_CLASS_D,
 389   INSN_CLASS_Q,
 390   INSN_CLASS_F_AND_C,
 391   INSN_CLASS_D_AND_C,
 392   INSN_CLASS_ZICOND,
 393   INSN_CLASS_ZICSR,
 394   INSN_CLASS_ZIFENCEI,
 395   INSN_CLASS_ZIHINTNTL,
 396   INSN_CLASS_ZIHINTNTL_AND_C,
 397   INSN_CLASS_ZIHINTPAUSE,
 398   INSN_CLASS_ZMMUL,
 399   INSN_CLASS_ZAWRS,
 400   INSN_CLASS_F_INX,
 401   INSN_CLASS_D_INX,
 402   INSN_CLASS_Q_INX,
 403   INSN_CLASS_ZFH_INX,
 404   INSN_CLASS_ZFHMIN,
 405   INSN_CLASS_ZFHMIN_INX,
 406   INSN_CLASS_ZFHMIN_AND_D_INX,
 407   INSN_CLASS_ZFHMIN_AND_Q_INX,
 408   INSN_CLASS_ZFA,
 409   INSN_CLASS_D_AND_ZFA,
 410   INSN_CLASS_Q_AND_ZFA,
 411   INSN_CLASS_ZFH_AND_ZFA,
 412   INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
 413   INSN_CLASS_ZBA,
 414   INSN_CLASS_ZBB,
 415   INSN_CLASS_ZBC,
 416   INSN_CLASS_ZBS,
 417   INSN_CLASS_ZBKB,
 418   INSN_CLASS_ZBKC,
 419   INSN_CLASS_ZBKX,
 420   INSN_CLASS_ZKND,
 421   INSN_CLASS_ZKNE,
 422   INSN_CLASS_ZKNH,
 423   INSN_CLASS_ZKSED,
 424   INSN_CLASS_ZKSH,
 425   INSN_CLASS_ZBB_OR_ZBKB,
 426   INSN_CLASS_ZBC_OR_ZBKC,
 427   INSN_CLASS_ZKND_OR_ZKNE,
 428   INSN_CLASS_V,
 429   INSN_CLASS_ZVEF,
 430   INSN_CLASS_ZVBB,
 431   INSN_CLASS_ZVBC,
 432   INSN_CLASS_ZVKG,
 433   INSN_CLASS_ZVKNED,
 434   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
 435   INSN_CLASS_ZVKSED,
 436   INSN_CLASS_ZVKSH,
 437   INSN_CLASS_ZCB,
 438   INSN_CLASS_ZCB_AND_ZBA,
 439   INSN_CLASS_ZCB_AND_ZBB,
 440   INSN_CLASS_ZCB_AND_ZMMUL,
 441   INSN_CLASS_SVINVAL,
 442   INSN_CLASS_ZICBOM,
 443   INSN_CLASS_ZICBOP,
 444   INSN_CLASS_ZICBOZ,
 445   INSN_CLASS_H,
 446   INSN_CLASS_XTHEADBA,
 447   INSN_CLASS_XTHEADBB,
 448   INSN_CLASS_XTHEADBS,
 449   INSN_CLASS_XTHEADCMO,
 450   INSN_CLASS_XTHEADCONDMOV,
 451   INSN_CLASS_XTHEADFMEMIDX,
 452   INSN_CLASS_XTHEADFMV,
 453   INSN_CLASS_XTHEADINT,
 454   INSN_CLASS_XTHEADMAC,
 455   INSN_CLASS_XTHEADMEMIDX,
 456   INSN_CLASS_XTHEADMEMPAIR,
 457   INSN_CLASS_XTHEADSYNC,
 458   INSN_CLASS_XVENTANACONDOPS,
 459 };
 460
 461 /* This structure holds information for a particular instruction.  */
 462 struct riscv_opcode
 463 {
 464   /* The name of the instruction.  */
 465   const char *name;
 466
 467   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 468   unsigned xlen_requirement;
 469
 470   /* Class to which this instruction belongs.  Used to decide whether or
 471      not this instruction is legal in the current -march context.  */
 472   enum riscv_insn_class insn_class;
 473
 474   /* A string describing the arguments for this instruction.  */
 475   const char *args;
 476
 477   /* The basic opcode for the instruction.  When assembling, this
 478      opcode is modified by the arguments to produce the actual opcode
 479      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 480   insn_t match;
 481
 482   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 483      relevant portions of the opcode when disassembling.  If the
 484      actual opcode anded with the match field equals the opcode field,
 485      then we have found the correct instruction.  If pinfo is
 486      INSN_MACRO, then this field is the macro identifier.  */
 487   insn_t mask;
 488
 489   /* A function to determine if a word corresponds to this instruction.
 490      Usually, this computes ((word & mask) == match).  */
 491   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 492
 493   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 494      of bits describing the instruction, notably any relevant hazard
 495      information.  */
 496   unsigned long pinfo;
 497 };
 498
 499 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 500 #define INSN_ALIAS              0x00000001
 501
 502 /* These are for setting insn_info fields.
 503
 504    Nonbranch is the default.  Noninsn is used only if there is no match.
 505    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 506    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 507 #define INSN_TYPE               0x0000000e
 508
 509 /* Instruction is an unconditional branch.  */
 510 #define INSN_BRANCH             0x00000002
 511 /* Instruction is a conditional branch.  */
 512 #define INSN_CONDBRANCH         0x00000004
 513 /* Instruction is a jump to subroutine.  */
 514 #define INSN_JSR                0x00000006
 515 /* Instruction is a data reference.  */
 516 #define INSN_DREF               0x00000008
 517 /* Instruction is allowed when eew >= 64.  */
 518 #define INSN_V_EEW64            0x10000000
 519
 520 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 521 #define INSN_DATA_SIZE          0x00000070
 522 #define INSN_DATA_SIZE_SHIFT    4
 523 #define INSN_1_BYTE             0x00000010
 524 #define INSN_2_BYTE             0x00000020
 525 #define INSN_4_BYTE             0x00000030
 526 #define INSN_8_BYTE             0x00000040
 527 #define INSN_16_BYTE            0x00000050
 528
 529 /* Instruction is actually a macro.  It should be ignored by the
 530    disassembler, and requires special treatment by the assembler.  */
 531 #define INSN_MACRO              0xffffffff
 532
 533 /* This is a list of macro expanded instructions.  */
 534 enum
 535 {
 536   M_LA,
 537   M_LLA,
 538   M_LGA,
 539   M_LA_TLS_GD,
 540   M_LA_TLS_IE,
 541   M_LB,
 542   M_LBU,
 543   M_LH,
 544   M_LHU,
 545   M_LW,
 546   M_LWU,
 547   M_LD,
 548   M_SB,
 549   M_SH,
 550   M_SW,
 551   M_SD,
 552   M_FLW,
 553   M_FLD,
 554   M_FLQ,
 555   M_FSW,
 556   M_FSD,
 557   M_FSQ,
 558   M_CALL,
 559   M_J,
 560   M_LI,
 561   M_ZEXTH,
 562   M_ZEXTW,
 563   M_SEXTB,
 564   M_SEXTH,
 565   M_VMSGE,
 566   M_FLH,
 567   M_FSH,
 568   M_NUM_MACROS
 569 };
 570
 571 /* The mapping symbol states.  */
 572 enum riscv_seg_mstate
 573 {
 574   MAP_NONE = 0,         /* Must be zero, for seginfo in new sections.  */
 575   MAP_DATA,             /* Data.  */
 576   MAP_INSN,             /* Instructions.  */
 577 };
 578
 579 #define NRC (4 + 1)     /* Max characters in register names, incl nul.  */
 580
 581 extern const char riscv_gpr_names_numeric[NGPR][NRC];
 582 extern const char riscv_gpr_names_abi[NGPR][NRC];
 583 extern const char riscv_fpr_names_numeric[NFPR][NRC];
 584 extern const char riscv_fpr_names_abi[NFPR][NRC];
 585 extern const char * const riscv_rm[8];
 586 extern const char * const riscv_pred_succ[16];
 587 extern const char riscv_vecr_names_numeric[NVECR][NRC];
 588 extern const char riscv_vecm_names_numeric[NVECM][NRC];
 589 extern const char * const riscv_vsew[8];
 590 extern const char * const riscv_vlmul[8];
 591 extern const char * const riscv_vta[2];
 592 extern const char * const riscv_vma[2];
 593 extern const char * const riscv_fli_symval[32];
 594 extern const float riscv_fli_numval[32];
 595
 596 extern const struct riscv_opcode riscv_opcodes[];
 597 extern const struct riscv_opcode riscv_insn_types[];
 598
 599 #endif /* _RISCV_H_ */