include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2021 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC instructions.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
  39     return 8;
  40   /* Longer instructions not supported at the moment.  */
  41   return 2;
  42 }
  43
  44 static const char * const riscv_rm[8] =
  45 {
  46   "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
  47 };
  48
  49 static const char * const riscv_pred_succ[16] =
  50 {
  51   0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
  52   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
  53 };
  54
  55 #define RVC_JUMP_BITS 11
  56 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  57
  58 #define RVC_BRANCH_BITS 8
  59 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  60
  61 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  62 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  63
  64 #define EXTRACT_ITYPE_IMM(x) \
  65   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  66 #define EXTRACT_STYPE_IMM(x) \
  67   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  68 #define EXTRACT_BTYPE_IMM(x) \
  69   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  70 #define EXTRACT_UTYPE_IMM(x) \
  71   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  72 #define EXTRACT_JTYPE_IMM(x) \
  73   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  74 #define EXTRACT_CITYPE_IMM(x) \
  75   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  76 #define EXTRACT_CITYPE_LUI_IMM(x) \
  77   (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
  78 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  79   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  80 #define EXTRACT_CITYPE_LWSP_IMM(x) \
  81   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  82 #define EXTRACT_CITYPE_LDSP_IMM(x) \
  83   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  84 #define EXTRACT_CSSTYPE_IMM(x) \
  85   (RV_X(x, 7, 6) << 0)
  86 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  87   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  88 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  89   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  90 #define EXTRACT_CIWTYPE_IMM(x) \
  91   (RV_X(x, 5, 8))
  92 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  93   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  94 #define EXTRACT_CLTYPE_IMM(x) \
  95   ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
  96 #define EXTRACT_CLTYPE_LW_IMM(x) \
  97   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  98 #define EXTRACT_CLTYPE_LD_IMM(x) \
  99   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
 100 #define EXTRACT_CBTYPE_IMM(x) \
 101   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
 102 #define EXTRACT_CJTYPE_IMM(x) \
 103   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
 104
 105 #define ENCODE_ITYPE_IMM(x) \
 106   (RV_X(x, 0, 12) << 20)
 107 #define ENCODE_STYPE_IMM(x) \
 108   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 109 #define ENCODE_BTYPE_IMM(x) \
 110   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 111 #define ENCODE_UTYPE_IMM(x) \
 112   (RV_X(x, 12, 20) << 12)
 113 #define ENCODE_JTYPE_IMM(x) \
 114   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 115 #define ENCODE_CITYPE_IMM(x) \
 116   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 117 #define ENCODE_CITYPE_LUI_IMM(x) \
 118   ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
 119 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \
 120   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 121 #define ENCODE_CITYPE_LWSP_IMM(x) \
 122   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 123 #define ENCODE_CITYPE_LDSP_IMM(x) \
 124   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 125 #define ENCODE_CSSTYPE_IMM(x) \
 126   (RV_X(x, 0, 6) << 7)
 127 #define ENCODE_CSSTYPE_SWSP_IMM(x) \
 128   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 129 #define ENCODE_CSSTYPE_SDSP_IMM(x) \
 130   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 131 #define ENCODE_CIWTYPE_IMM(x) \
 132   (RV_X(x, 0, 8) << 5)
 133 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
 134   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 135 #define ENCODE_CLTYPE_IMM(x) \
 136   ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
 137 #define ENCODE_CLTYPE_LW_IMM(x) \
 138   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 139 #define ENCODE_CLTYPE_LD_IMM(x) \
 140   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 141 #define ENCODE_CBTYPE_IMM(x) \
 142   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 143 #define ENCODE_CJTYPE_IMM(x) \
 144   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 145
 146 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 147 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 148 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
 149 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 150 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
 151 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
 152 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
 153                                  && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
 154 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
 155                                       && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
 156 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
 157 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
 158 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
 159 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
 160 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
 161 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
 162 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
 163 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
 164 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
 165 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
 166 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
 167 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 168
 169 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 170   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 171 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 172   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 173 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 174   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 175 #define RISCV_BTYPE(insn, rs1, rs2, target) \
 176   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
 177 #define RISCV_UTYPE(insn, rd, bigimm) \
 178   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 179 #define RISCV_JTYPE(insn, rd, target) \
 180   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
 181
 182 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 183 #define RVC_NOP MATCH_C_ADDI
 184
 185 #define RISCV_CONST_HIGH_PART(VALUE) \
 186   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 187 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 188 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 189 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 190
 191 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 192 #define RISCV_JUMP_ALIGN_BITS 1
 193 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 194 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 195
 196 #define RISCV_IMM_BITS 12
 197 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 198 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 199 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 200 #define RISCV_RVC_IMM_REACH (1LL << 6)
 201 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 202 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 203 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 204 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 205
 206 /* RV fields.  */
 207
 208 #define OP_MASK_OP              0x7f
 209 #define OP_SH_OP                0
 210 #define OP_MASK_RS2             0x1f
 211 #define OP_SH_RS2               20
 212 #define OP_MASK_RS1             0x1f
 213 #define OP_SH_RS1               15
 214 #define OP_MASK_RS3             0x1fU
 215 #define OP_SH_RS3               27
 216 #define OP_MASK_RD              0x1f
 217 #define OP_SH_RD                7
 218 #define OP_MASK_SHAMT           0x3f
 219 #define OP_SH_SHAMT             20
 220 #define OP_MASK_SHAMTW          0x1f
 221 #define OP_SH_SHAMTW            20
 222 #define OP_MASK_RM              0x7
 223 #define OP_SH_RM                12
 224 #define OP_MASK_PRED            0xf
 225 #define OP_SH_PRED              24
 226 #define OP_MASK_SUCC            0xf
 227 #define OP_SH_SUCC              20
 228 #define OP_MASK_AQ              0x1
 229 #define OP_SH_AQ                26
 230 #define OP_MASK_RL              0x1
 231 #define OP_SH_RL                25
 232
 233 #define OP_MASK_CSR             0xfffU
 234 #define OP_SH_CSR               20
 235
 236 #define OP_MASK_FUNCT3          0x7
 237 #define OP_SH_FUNCT3            12
 238 #define OP_MASK_FUNCT7          0x7fU
 239 #define OP_SH_FUNCT7            25
 240 #define OP_MASK_FUNCT2          0x3
 241 #define OP_SH_FUNCT2            25
 242
 243 /* RVC fields.  */
 244
 245 #define OP_MASK_OP2             0x3
 246 #define OP_SH_OP2               0
 247
 248 #define OP_MASK_CRS2            0x1f
 249 #define OP_SH_CRS2              2
 250 #define OP_MASK_CRS1S           0x7
 251 #define OP_SH_CRS1S             7
 252 #define OP_MASK_CRS2S           0x7
 253 #define OP_SH_CRS2S             2
 254
 255 #define OP_MASK_CFUNCT6         0x3f
 256 #define OP_SH_CFUNCT6           10
 257 #define OP_MASK_CFUNCT4         0xf
 258 #define OP_SH_CFUNCT4           12
 259 #define OP_MASK_CFUNCT3         0x7
 260 #define OP_SH_CFUNCT3           13
 261 #define OP_MASK_CFUNCT2         0x3
 262 #define OP_SH_CFUNCT2           5
 263
 264 /* ABI names for selected x-registers.  */
 265
 266 #define X_RA 1
 267 #define X_SP 2
 268 #define X_GP 3
 269 #define X_TP 4
 270 #define X_T0 5
 271 #define X_T1 6
 272 #define X_T2 7
 273 #define X_T3 28
 274
 275 #define NGPR 32
 276 #define NFPR 32
 277
 278 /* These fake label defines are use by both the assembler, and
 279    libopcodes.  The assembler uses this when it needs to generate a fake
 280    label, and libopcodes uses it to hide the fake labels in its output.  */
 281 #define RISCV_FAKE_LABEL_NAME ".L0 "
 282 #define RISCV_FAKE_LABEL_CHAR ' '
 283
 284 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 285    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 286 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 287   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 288               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 289
 290 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 291    SHIFT places.  */
 292 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 293   (((STRUCT) >> (SHIFT)) & (MASK))
 294
 295 /* Extract the operand given by FIELD from integer INSN.  */
 296 #define EXTRACT_OPERAND(FIELD, INSN) \
 297   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 298
 299 /* The maximal number of subset can be required.  */
 300 #define MAX_SUBSET_NUM 4
 301
 302 /* All RISC-V instructions belong to at least one of these classes.  */
 303 enum riscv_insn_class
 304 {
 305   INSN_CLASS_NONE,
 306
 307   INSN_CLASS_I,
 308   INSN_CLASS_C,
 309   INSN_CLASS_A,
 310   INSN_CLASS_M,
 311   INSN_CLASS_F,
 312   INSN_CLASS_D,
 313   INSN_CLASS_Q,
 314   INSN_CLASS_F_AND_C,
 315   INSN_CLASS_D_AND_C,
 316   INSN_CLASS_ZICSR,
 317   INSN_CLASS_ZIFENCEI,
 318   INSN_CLASS_ZIHINTPAUSE,
 319   INSN_CLASS_ZBA,
 320   INSN_CLASS_ZBB,
 321   INSN_CLASS_ZBC,
 322 };
 323
 324 /* This structure holds information for a particular instruction.  */
 325 struct riscv_opcode
 326 {
 327   /* The name of the instruction.  */
 328   const char *name;
 329
 330   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 331   unsigned xlen_requirement;
 332
 333   /* Class to which this instruction belongs.  Used to decide whether or
 334      not this instruction is legal in the current -march context.  */
 335   enum riscv_insn_class insn_class;
 336
 337   /* A string describing the arguments for this instruction.  */
 338   const char *args;
 339
 340   /* The basic opcode for the instruction.  When assembling, this
 341      opcode is modified by the arguments to produce the actual opcode
 342      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 343   insn_t match;
 344
 345   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 346      relevant portions of the opcode when disassembling.  If the
 347      actual opcode anded with the match field equals the opcode field,
 348      then we have found the correct instruction.  If pinfo is
 349      INSN_MACRO, then this field is the macro identifier.  */
 350   insn_t mask;
 351
 352   /* A function to determine if a word corresponds to this instruction.
 353      Usually, this computes ((word & mask) == match).  */
 354   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 355
 356   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 357      of bits describing the instruction, notably any relevant hazard
 358      information.  */
 359   unsigned long pinfo;
 360 };
 361
 362 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 363 #define INSN_ALIAS              0x00000001
 364
 365 /* These are for setting insn_info fields.
 366
 367    Nonbranch is the default.  Noninsn is used only if there is no match.
 368    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 369    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 370 #define INSN_TYPE               0x0000000e
 371
 372 /* Instruction is an unconditional branch.  */
 373 #define INSN_BRANCH             0x00000002
 374 /* Instruction is a conditional branch.  */
 375 #define INSN_CONDBRANCH         0x00000004
 376 /* Instruction is a jump to subroutine.  */
 377 #define INSN_JSR                0x00000006
 378 /* Instruction is a data reference.  */
 379 #define INSN_DREF               0x00000008
 380
 381 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 382 #define INSN_DATA_SIZE          0x00000070
 383 #define INSN_DATA_SIZE_SHIFT    4
 384 #define INSN_1_BYTE             0x00000010
 385 #define INSN_2_BYTE             0x00000020
 386 #define INSN_4_BYTE             0x00000030
 387 #define INSN_8_BYTE             0x00000040
 388 #define INSN_16_BYTE            0x00000050
 389
 390 /* Instruction is actually a macro.  It should be ignored by the
 391    disassembler, and requires special treatment by the assembler.  */
 392 #define INSN_MACRO              0xffffffff
 393
 394 /* This is a list of macro expanded instructions.  */
 395 enum
 396 {
 397   M_LA,
 398   M_LLA,
 399   M_LA_TLS_GD,
 400   M_LA_TLS_IE,
 401   M_LB,
 402   M_LBU,
 403   M_LH,
 404   M_LHU,
 405   M_LW,
 406   M_LWU,
 407   M_LD,
 408   M_SB,
 409   M_SH,
 410   M_SW,
 411   M_SD,
 412   M_FLW,
 413   M_FLD,
 414   M_FLQ,
 415   M_FSW,
 416   M_FSD,
 417   M_FSQ,
 418   M_CALL,
 419   M_J,
 420   M_LI,
 421   M_ZEXTH,
 422   M_ZEXTW,
 423   M_SEXTB,
 424   M_SEXTH,
 425   M_NUM_MACROS
 426 };
 427
 428
 429 extern const char * const riscv_gpr_names_numeric[NGPR];
 430 extern const char * const riscv_gpr_names_abi[NGPR];
 431 extern const char * const riscv_fpr_names_numeric[NFPR];
 432 extern const char * const riscv_fpr_names_abi[NFPR];
 433
 434 extern const struct riscv_opcode riscv_opcodes[];
 435 extern const struct riscv_opcode riscv_insn_types[];
 436
 437 #endif /* _RISCV_H_ */