include/opcode/sparc.h

   1 /* Definitions for opcode table for the sparc.
   2         Copyright 1989, 1991, 1992 Free Software Foundation, Inc.
   3
   4 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   5 the GNU Binutils.
   6
   7
   8 GAS/GDB is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GAS/GDB is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.    See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GAS or GDB; see the file COPYING.    If not, write to
  20 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.   */
  21
  22 /* The SPARC opcode table (and other related data) is defined in
  23    the opcodes library in sparc-opc.c.  If you change anything here, make
  24    sure you fix up that file, and vice versa.  */
  25
  26  /* FIXME-someday: perhaps the ,a's and such should be embedded in the
  27     instruction's name rather than the args.  This would make gas faster, pinsn
  28     slower, but would mess up some macros a bit.  xoxorich. */
  29
  30 #define sparc_architecture      bfd_sparc_architecture
  31 #define architecture_pname      bfd_sparc_architecture_pname
  32 #define sparc_opcode            bfd_sparc_opcode
  33 #define sparc_opcodes           bfd_sparc_opcodes
  34
  35 /*
  36  * Structure of an opcode table entry.
  37  * This enumerator must parallel the architecture_pname array
  38  * in bfd/opc-sparc.c.
  39  */
  40 enum sparc_architecture {
  41         v6 = 0,
  42         v7,
  43         v8,
  44         sparclite,
  45         v9
  46 };
  47
  48 extern const char *architecture_pname[];
  49
  50 /* Sparclite and v9 are both supersets of v8; we can't bump between them.  */
  51
  52 #define ARCHITECTURES_CONFLICT_P(ARCH1, ARCH2) ((ARCH1) == sparclite && (ARCH2) == v9)
  53
  54 struct sparc_opcode {
  55         const char *name;
  56         unsigned long match;    /* Bits that must be set. */
  57         unsigned long lose;     /* Bits that must not be set. */
  58         const char *args;
  59  /* This was called "delayed" in versions before the flags. */
  60         char flags;
  61         enum sparc_architecture architecture;
  62 };
  63
  64 #define F_DELAYED       1       /* Delayed branch */
  65 #define F_ALIAS         2       /* Alias for a "real" instruction */
  66 #define F_UNBR          4       /* Unconditional branch */
  67 #define F_CONDBR        8       /* Conditional branch */
  68 #define F_JSR           16      /* Subroutine call */
  69 /* FIXME: Add F_ANACHRONISTIC flag for v9.  */
  70 /* FIXME: Add F_OBSOLETE flag for v9, for instructions that no longer exist? */
  71
  72 /*
  73
  74 All sparc opcodes are 32 bits, except for the `set' instruction (really a
  75 macro), which is 64 bits. It is handled as a special case.
  76
  77 The match component is a mask saying which bits must match a particular
  78 opcode in order for an instruction to be an instance of that opcode.
  79
  80 The args component is a string containing one character for each operand of the
  81 instruction.
  82
  83 Kinds of operands:
  84         #       Number used by optimizer.       It is ignored.
  85         1       rs1 register.
  86         2       rs2 register.
  87         d       rd register.
  88         e       frs1 floating point register.
  89         v       frs1 floating point register (double/even).
  90         V       frs1 floating point register (quad/multiple of 4).
  91         f       frs2 floating point register.
  92         B       frs2 floating point register (double/even).
  93         R       frs2 floating point register (quad/multiple of 4).
  94         g       frsd floating point register.
  95         H       frsd floating point register (double/even).
  96         J       frsd floating point register (quad/multiple of 4).
  97         b       crs1 coprocessor register
  98         c       crs2 coprocessor register
  99         D       crsd coprocessor register
 100         m       alternate space register (asr) in rd
 101         M       alternate space register (asr) in rs1
 102         h       22 high bits.
 103         K       MEMBAR mask (7 bits). (v9)
 104         j       10 bit Immediate. (v9)
 105         I       11 bit Immediate. (v9)
 106         i       13 bit Immediate.
 107         n       22 bit immediate.
 108         k       2+14 bit PC relative immediate. (v9)
 109         G       19 bit PC relative immediate. (v9)
 110         l       22 bit PC relative immediate.
 111         L       30 bit PC relative immediate.
 112         a       Annul.  The annul bit is set.
 113         A       Alternate address space. Stored as 8 bits.
 114         C       Coprocessor state register.
 115         F       floating point state register.
 116         p       Processor state register.
 117         N       Branch predict clear ",pn" (v9)
 118         T       Branch predict set ",pt" (v9)
 119         z       %icc. (v9)
 120         Z       %xcc. (v9)
 121         q       Floating point queue.
 122         r       Single register that is both rs1 and rsd.
 123         Q       Coprocessor queue.
 124         S       Special case.
 125         t       Trap base register.
 126         w       Window invalid mask register.
 127         y       Y register.
 128         E       %ccr. (v9)
 129         s       %fprs. (v9)
 130         P       %pc.  (v9)
 131         W       %tick.  (v9)
 132         o       %asi. (v9)
 133         6       %fcc0. (v9)
 134         7       %fcc1. (v9)
 135         8       %fcc2. (v9)
 136         9       %fcc3. (v9)
 137         !       Privileged Register in rd (v9)
 138         ?       Privileged Register in rs1 (v9)
 139         *       Prefetch function constant. (v9)
 140         x       OPF field (v9 impdep).
 141
 142 The following chars are unused: (note: ,[] are used as punctuation)
 143 [uxOUXY3450]
 144
 145 */
 146
 147 #define OP2(x)          (((x)&0x7) << 22) /* op2 field of format2 insns */
 148 #define OP3(x)          (((x)&0x3f) << 19) /* op3 field of format3 insns */
 149 #define OP(x)           ((unsigned)((x)&0x3) << 30) /* op field of all insns */
 150 #define OPF(x)          (((x)&0x1ff) << 5) /* opf field of float insns */
 151 #define OPF_LOW5(x)     OPF((x)&0x1f) /* v9 */
 152 #define F3F(x, y, z)    (OP(x) | OP3(y) | OPF(z)) /* format3 float insns */
 153 #define F3I(x)          (((x)&0x1) << 13) /* immediate field of format 3 insns */
 154 #define F2(x, y)        (OP(x) | OP2(y)) /* format 2 insns */
 155 #define F3(x, y, z)     (OP(x) | OP3(y) | F3I(z)) /* format3 insns */
 156 #define F1(x)           (OP(x))
 157 #define DISP30(x)       ((x)&0x3fffffff)
 158 #define ASI(x)          (((x)&0xff) << 5) /* asi field of format3 insns */
 159 #define RS2(x)          ((x)&0x1f) /* rs2 field */
 160 #define SIMM13(x)       ((x)&0x1fff) /* simm13 field */
 161 #define RD(x)           (((x)&0x1f) << 25) /* destination register field */
 162 #define RS1(x)          (((x)&0x1f) << 14) /* rs1 field */
 163 #define ASI_RS2(x)      (SIMM13(x))
 164
 165 #define ANNUL   (1<<29)
 166 #define BPRED   (1<<19) /* v9 */
 167 #define IMMED   F3I(1)
 168 #define RD_G0   RD(~0)
 169 #define RS1_G0  RS1(~0)
 170 #define RS2_G0  RS2(~0)
 171
 172 extern struct sparc_opcode sparc_opcodes[];
 173 extern const int bfd_sparc_num_opcodes;
 174
 175 #define NUMOPCODES bfd_sparc_num_opcodes
 176
 177 /*
 178  * Local Variables:
 179  * fill-column: 131
 180  * comment-column: 0
 181  * End:
 182  */
 183
 184 /* end of sparc.h */