1 # Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
3 The Libre-SoC project is an effort to develop an completely
4 SoC that is libre to the bedrock.
6 Libre has a very specific meaning and guarantees, where "open" does not.
7 See <https://www.gnu.org/philosophy/open-source-misses-the-point.html>
8 for an explanation of the distinction, and for additional examples:
9 <https://wiki.opensourceecology.org/wiki/Fake_Open_Source>
11 This is a publicly editable wiki.
13 All wikis are supposed to have a [[SandBox]], so this one does too.
15 This wiki is powered by [[ikiwiki]].
17 This is the sitemap: [[sitemap]]
23 The main contact point is the
24 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev).
25 If you need to contact the sysadmin please use webmaster@libre-riscv.org
27 # Joining/Onboarding Process
29 This process probably needs some improvement: the basic
31 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
32 introduce yourself, and read through
33 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
36 The next thing you should do is read through the [bugs
37 list](http://bugs.libre-riscv.org) and see if there are any bugs that
40 We do have funding available (see [[nlnet]]) upon completion of issues -
41 we are also working on procuring more funding which gets the project to
42 nanometre scale tapeout.
44 After all this, if you feel that Libre-SoC is a good cause that
45 you would like to contribute to, add yourself to the [[current_members]]
46 page and fill in some information about yourself.
50 Most labor is currently being applied to developing the GPU portion of
53 The highest priority needed at the moment is a c++ engineer to work on
54 a MESA 3D driver. This will begin life as similar to SwiftShader however
55 retaining the vectorisation and predication intrinsics.
57 Medium to long-term we need HDL engineers. Particularly those familiar
58 with nMigen or just python. Most of the techniques being used require
59 software engineering skills (OO design, polymorphism) than they do more
60 traditional HDL programming skills. Basically if you have experience in 2
61 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
62 design. See [[HDL_workflow]]
64 Also, individuals with experience in formal mathematical verification
67 TODO: add a list of upcoming project tasks/milestones (link to
72 * Mailing Lists <http://lists.libre-riscv.org> -
73 Archives at <http://lists.libre-riscv.org/pipermail>
74 * Git repositories <http://git.libre-riscv.org>
75 may be cloned publicly with
76 git clone https://git.libre-riscv.org/git/repositoryname.git
77 * Bugzilla at <http://bugs.libre-riscv.org/>
78 * Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
79 * Further Information [[resources]]
83 * Libre-SoC [[charter]]
88 * [[simple_v_extension]]
91 * [[simple_v_extension/specification/mv.x]]
92 * [[simple_v_extension/specification/ld.x]]
93 * Specifications and [[resources]]
96 * [Set-Up Instructions][1]
98 [1]: https://libre-riscv.org/3d_gpu/spike_sv/