index.mdwn

   1 # Welcome to Libre-SoC(formerly Libre-RISCV)!
   2
   3 The Libre-SoC project is an effort to develop an completely
   4 SOC that is libre to the bedrock.
   5
   6 Libre has a very specific meaning and guarantees, where "open" does not.
   7 See <https://www.gnu.org/philosophy/open-source-misses-the-point.html>
   8 for an explanation of the distinction, and for additional examples:
   9 <https://wiki.opensourceecology.org/wiki/Fake_Open_Source>
  10
  11 This is a publicly editable wiki.
  12
  13 All wikis are supposed to have a [[SandBox]], so this one does too.
  14
  15 This wiki is powered by [[ikiwiki]].
  16
  17 This is the sitemap: [[sitemap]]
  18
  19 ----
  20
  21 # Joining/Onboarding Process
  22
  23 This process probably needs some improvement, but the basic
  24 idea is to join the
  25 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
  26 introduce yourself, and read through
  27 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
  28 and the [[charter]].
  29
  30 The next thing you should do is read through the [bugs
  31 list](http://bugs.libre-riscv.org) and see if there are any bugs that
  32 pique your interest.
  33
  34 We do have funding available (see [[nlnet]]) upon completion of issues -
  35 we are also working on procuring more funding which gets the project to
  36 nanometre scale tapeout.
  37
  38 After all this, if you feel that Libre-SOC is a good cause that
  39 you would like to contribute to, add yourself to the [[current_members]]
  40 page and fill in some information about yourself.
  41
  42 ## Needed Skills
  43
  44 Most labor is currently being applied to developing the GPU portion of
  45 the LibreSOC.
  46
  47 The highest priority needed at the moment is a c++ engineer to work on
  48 a MESA 3D driver. This will begin life as similar to SwiftShader however
  49 retaining the vectorisation and predication intrinsics.
  50
  51 Medium to long-term we need HDL engineers. Particularly those familiar
  52 with nMigen or just python.  Most of the techniques being used require
  53 software engineering skills (OO design, polymorphism) than they do more
  54 traditional HDL programming skills. Basically if you have experience in 2
  55 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
  56 design. See [[HDL_workflow]]
  57
  58 Also, individuals with experience in formal mathematical verification
  59 are quite welcome.
  60
  61 TODO: add a list of upcoming project tasks/milestones (link to
  62 bugtracker).
  63
  64 # Resources
  65
  66 * Mailing Lists <http://lists.libre-riscv.org> -
  67   Archives at <http://lists.libre-riscv.org/pipermail>
  68 * Git repositories <http://git.libre-riscv.org>
  69   may be cloned publicly with
  70   git clone https://git.libre-riscv.org/git/repositoryname.git
  71 * Bugzilla at <http://bugs.libre-riscv.org/>
  72 * Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
  73 * Further Information [[resources]]
  74
  75 # Main Pages
  76
  77 * Libre-SoC [[charter]]
  78 * [[shakti/m_class]]
  79 * [[alt_rvp]]
  80 * [[3d_gpu]]
  81 * [[vpu]]
  82 * [[simple_v_extension]]
  83 * [[zfpacc_proposal]]
  84 * [[ztrans_proposal]]
  85 * [[simple_v_extension/specification/mv.x]]
  86 * [[simple_v_extension/specification/ld.x]]
  87 * Specifications and [[resources]]
  88
  89 # Spike Emulator
  90 * [Set-Up Instructions][1]
  91
  92 [1]: https://libre-riscv.org/3d_gpu/spike_sv/
  93
  94 # Current Members
  95
  96 [[current_members]]