3 > We're building a chip. A fast chip. A safe chip. A trusted chip.
5 > A chip with lots of peripherals. And a gpu. And an AI accelerator...
7 > Oh and here, have the source code...
9 Sounds cool? Learn more [here](who_we_are)
11 # Join us in Realizing the First Market Ready LibreSOC!
14 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
15 introduce yourself, and read through
16 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
19 2. The next thing you should do is read through the [bugs
20 list](http://bugs.libre-riscv.org) and see if there are any bugs that
23 3. After that, go ahead and take a look at the resources section below.
24 Try and clone a repository with ``git clone https://git.libre-riscv.org/git/repositoryname.git``
26 4. If you plan to do HDL work, you should familiarize yourself with our [[HDL_workflow]].
28 5. We do have funding available (see [[nlnet]]) upon completion of issues -
29 we are also working on procuring more funding which gets the project to
30 nanometre scale tapeout.
32 6. After all this, if you feel that Libre-SoC is a good cause that
33 you would like to contribute to, add yourself to the [[current_members]]
34 page, fill in some information about yourself, and join the mailing list
37 Also note that you can edit this wiki. See the last section of this page.
41 Most labor is currently being applied to developing the GPU portion of
44 The highest priority needed at the moment is a c++ engineer to work on
45 a MESA 3D driver. This will begin life similar to SwiftShader however
46 retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks)
48 Medium to long-term we need HDL engineers. Particularly those familiar
49 with nMigen or just python. Most of the techniques being used require
50 software engineering skills (OO design, polymorphism) than they do more
51 traditional HDL programming skills. Basically if you have experience in 2
52 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
53 design. See [[HDL_workflow]]
55 Also, individuals with experience in formal mathematical verification
58 TODO: add a list of upcoming project tasks/milestones (link to
65 | Bugs and Tasks | <http://bugs.libre-riscv.org/> |
66 | Mailing Lists | <http://lists.libre-riscv.org> |
67 | Archives | <http://lists.libre-riscv.org/pipermail> |
68 | Git repositories | <http://git.libre-riscv.org> |
69 | Kazan (Vulkan driver) | <https://salsa.debian.org/Kazan-team/kazan> |
70 | Further Information | [[resources]] |
74 * Libre-SoC [[charter]]
79 * [[simple_v_extension]]
82 * [[simple_v_extension/specification/mv.x]]
83 * [[simple_v_extension/specification/ld.x]]
84 * Specifications and [[resources]]
87 * [Set-Up Instructions][1]
89 [1]: https://libre-riscv.org/3d_gpu/spike_sv/
97 This is a publicly editable wiki.
99 All wikis are supposed to have a [[SandBox]], so this one does too.
101 This wiki is powered by [[ikiwiki]].
103 This is the sitemap: [[sitemap]]