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1 # Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
2 ## Why a Libre SOC?
3
4 Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com):
5
6 There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline(this doesn’t even consider out of order execution).
7
8 Given the fact that [high performing]bug free processors don’t exist anymore, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
9
10 Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc.
11
12 ## What we Do
13 LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to study, modify, and redistribute the SOC source from HDL to VLSI.
14
15 Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
16
17 ## But Why do I need a LibreSOC?
18 Its entirely possible that you're OK with the fact that modern processors have
19 [backdoors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html) that bad actors
20 regularly exploit.
21
22 But beyond the contemporary ever increasing cry for privacy, is a very real need for reliable safety critical processors.
23 LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access
24 to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they
25 expect. An ISA level simulator is no longer satisfactory.
26
27 Refer to this [paper](https://ieeexplore.ieee.org/document/4519604) authored by Cyberphysical System expert Ed-Lee for more details.
28
29 ## Still Got Questions?
30 Read about the business and practical benefits of a LibreSOC below.
31
32 [[why_a_libresoc]]
33
34
35 # Join us in Realizing the First Market Ready LibreSOC!
36
37 First. join the
38 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
39 introduce yourself, and read through
40 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
41 and the [[charter]].
42
43 The next thing you should do is read through the [bugs
44 list](http://bugs.libre-riscv.org) and see if there are any bugs that
45 pique your interest.
46
47 We do have funding available (see [[nlnet]]) upon completion of issues -
48 we are also working on procuring more funding which gets the project to
49 nanometre scale tapeout.
50
51 After all this, if you feel that Libre-SoC is a good cause that
52 you would like to contribute to, add yourself to the [[current_members]]
53 page, fill in some information about yourself, and join the mailing list
54 and say hello.
55
56 Also note that you can edit this wiki. See the last section of this page.
57
58 ## Needed Skills
59
60 Most labor is currently being applied to developing the GPU portion of
61 the Libre-SoC.
62
63 The highest priority needed at the moment is a c++ engineer to work on
64 a MESA 3D driver. This will begin life similar to SwiftShader however
65 retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks)
66
67 Medium to long-term we need HDL engineers. Particularly those familiar
68 with nMigen or just python. Most of the techniques being used require
69 software engineering skills (OO design, polymorphism) than they do more
70 traditional HDL programming skills. Basically if you have experience in 2
71 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
72 design. See [[HDL_workflow]]
73
74 Also, individuals with experience in formal mathematical verification
75 are quite welcome.
76
77 TODO: add a list of upcoming project tasks/milestones (link to
78 bugtracker).
79
80 # Resources
81
82 * Mailing Lists <http://lists.libre-riscv.org> -
83 Archives at <http://lists.libre-riscv.org/pipermail>
84 * Git repositories <http://git.libre-riscv.org>
85 may be cloned publicly with
86 git clone https://git.libre-riscv.org/git/repositoryname.git
87 * Bugzilla at <http://bugs.libre-riscv.org/>
88 * Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
89 * Further Information [[resources]]
90
91 # Main Pages
92
93 * Libre-SoC [[charter]]
94 * [[shakti/m_class]]
95 * [[alt_rvp]]
96 * [[3d_gpu]]
97 * [[vpu]]
98 * [[simple_v_extension]]
99 * [[zfpacc_proposal]]
100 * [[ztrans_proposal]]
101 * [[simple_v_extension/specification/mv.x]]
102 * [[simple_v_extension/specification/ld.x]]
103 * Specifications and [[resources]]
104
105 # Spike Emulator
106 * [Set-Up Instructions][1]
107
108 [1]: https://libre-riscv.org/3d_gpu/spike_sv/
109
110 # Current Members
111
112 [[current_members]]
113
114 # Wiki Structure
115
116 This is a publicly editable wiki.
117
118 All wikis are supposed to have a [[SandBox]], so this one does too.
119
120 This wiki is powered by [[ikiwiki]].
121
122 This is the sitemap: [[sitemap]]