index.mdwn

   1 # Welcome to Libre-SoC ([provisionally renamed](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-January/003580.html) from Libre-RISCV)!
   2
   3 LibreSOC strives to deliver a fully capable and competitive Libre integrated System on Chip. We want to maximize the degree of trust a customer can place in his or her processor. We do this by providing the customer the freedom to  study, modify, and redistribute the SOC source from HDL to VLSI.
   4
   5 Right now, we're targeting a (quad core, 800mhz, dual issue, GPU, VPU, [and later an ML inference core] ) SOC.
   6
   7 ## Why a Libre SOC?
   8
   9 Its quite hard to guarantee that a performant processors(think pipelined, out-of-order) are functionally perfectly correct. In fact, it often turns out that they [aren’t](https://meltdownattack.com).
  10
  11 There are entire [dissertations](http://www.kroening.com/diss/diss-kroe.pdf) dedicated to the subject matter of merely functionally verifying a pipeline(this doesn’t even consider out of order execution).
  12
  13 Given the fact that performant bug-free processors no longer exist, how can you trust your processor? The next best thing is to have access to a processor’s design files. Not only have access to them, you must have the freedom to study and improve them.
  14
  15 Such a processor is referred to as a Libre processor. However, processors themselves are only a part of the picture. Nowadays, most contemporary computing tasks involve artificial intelligence, media consumption, wireless connectivity, etc... Thus, we must deliver an entire LibreSOC.
  16
  17 ## Benefits: Privacy, Safety-Critical, Peace of Mind...
  18 Our LibreSOC will not have backdoors that plague modern [processors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html).
  19
  20 There is a very real need for reliable safety critical processors(think airplane, smart car, pacemaker...).
  21 LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access
  22 to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they
  23 expect. An ISA level simulator is no longer satisfactory.
  24
  25 Refer to this [IEEE article](https://ieeexplore.ieee.org/document/4519604) by Cyberphysical System expert Ed-Lee for more details.
  26
  27 ## Still Have Questions?
  28 Read about the business and practical benefits of a LibreSOC below.
  29
  30 [[why_a_libresoc]]
  31
  32
  33 # Join us in Realizing the First Market Ready LibreSOC!
  34
  35 First. join the
  36 [mailing list](http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev),
  37 introduce yourself, and read through
  38 [recent posts](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/)
  39 and the [[charter]].
  40
  41 The next thing you should do is read through the [bugs
  42 list](http://bugs.libre-riscv.org) and see if there are any bugs that
  43 pique your interest.
  44
  45 We do have funding available (see [[nlnet]]) upon completion of issues -
  46 we are also working on procuring more funding which gets the project to
  47 nanometre scale tapeout.
  48
  49 After all this, if you feel that Libre-SoC is a good cause that
  50 you would like to contribute to, add yourself to the [[current_members]]
  51 page, fill in some information about yourself, and join the mailing list
  52 and say hello.
  53
  54 Also note that you can edit this wiki. See the last section of this page.
  55
  56 ## Needed Skills
  57
  58 Most labor is currently being applied to developing the GPU portion of
  59 the Libre-SoC.
  60
  61 The highest priority needed at the moment is a c++ engineer to work on
  62 a MESA 3D driver. This will begin life similar to SwiftShader however
  63 retaining the vectorisation and predication intrinsics as well as hardware accelerated opcodes (all of which SwiftShader lacks)
  64
  65 Medium to long-term we need HDL engineers. Particularly those familiar
  66 with nMigen or just python.  Most of the techniques being used require
  67 software engineering skills (OO design, polymorphism) than they do more
  68 traditional HDL programming skills. Basically if you have experience in 2
  69 of the following you'll do fine: python, nmigen, verilog/VHDL/gate-level
  70 design. See [[HDL_workflow]]
  71
  72 Also, individuals with experience in formal mathematical verification
  73 are quite welcome.
  74
  75 TODO: add a list of upcoming project tasks/milestones (link to
  76 bugtracker).
  77
  78 # Resources
  79
  80 * Mailing Lists <http://lists.libre-riscv.org> -
  81   Archives at <http://lists.libre-riscv.org/pipermail>
  82 * Git repositories <http://git.libre-riscv.org>
  83   may be cloned publicly with
  84   git clone https://git.libre-riscv.org/git/repositoryname.git
  85 * Bugzilla at <http://bugs.libre-riscv.org/>
  86 * Kazan (Vulkan driver) at <https://salsa.debian.org/Kazan-team/kazan>
  87 * Further Information [[resources]]
  88
  89 # Main Pages
  90
  91 * Libre-SoC [[charter]]
  92 * [[shakti/m_class]]
  93 * [[alt_rvp]]
  94 * [[3d_gpu]]
  95 * [[vpu]]
  96 * [[simple_v_extension]]
  97 * [[zfpacc_proposal]]
  98 * [[ztrans_proposal]]
  99 * [[simple_v_extension/specification/mv.x]]
 100 * [[simple_v_extension/specification/ld.x]]
 101 * Specifications and [[resources]]
 102
 103 # Spike Emulator
 104 * [Set-Up Instructions][1]
 105
 106 [1]: https://libre-riscv.org/3d_gpu/spike_sv/
 107
 108 # Current Members
 109
 110 [[current_members]]
 111
 112 # Wiki Structure
 113
 114 This is a publicly editable wiki.
 115
 116 All wikis are supposed to have a [[SandBox]], so this one does too.
 117
 118 This wiki is powered by [[ikiwiki]].
 119
 120 This is the sitemap: [[sitemap]]