1 # See LICENSE for license details.
3 #*****************************************************************************
5 #-----------------------------------------------------------------------------
7 # Test VM referenced and dirty bits.
10 #include "riscv_test.h"
11 #include "test_macros.h"
17 li a0, (SPTBR_MODE & ~(SPTBR_MODE<<1)) * SPTBR_MODE_SV39
19 srl a1, a1, RISCV_PGSHIFT
24 # Set up MPRV with MPP=S, so loads and stores use S-mode
25 li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_MPRV
28 # Try a faulting store to make sure dirty bit is not set
31 sw t2, dummy - DRAM_BASE, a0
33 # Set SUM=1 so user memory access is permitted
35 li a1, ((MSTATUS_MPP & ~(MSTATUS_MPP<<1)) * PRV_S) | MSTATUS_SUM
38 # Make sure SUM=1 works
39 lw t0, dummy - DRAM_BASE
42 # Try a non-faulting store to make sure dirty bit is set
43 sw t2, dummy - DRAM_BASE, a0
45 # Make sure it succeeded
46 lw t0, dummy - DRAM_BASE
53 # Make sure D bit is set
63 # Make sure that superpage entries trap when PPN LSBs are set.
65 lw a0, page_table_1 - DRAM_BASE
66 or a0, a0, 1 << PTE_PPN_SHIFT
67 sw a0, page_table_1 - DRAM_BASE, t0
69 sw a0, page_table_1 - DRAM_BASE, t0
79 add t0, t0, -CAUSE_STORE_PAGE_FAULT
84 # Make sure D bit is clear
97 # The implementation doesn't appear to set D bits in HW.
98 # Make sure the D bit really is clear.
104 sw t0, page_table_1, t1
125 page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_W | PTE_X | PTE_A