1 # Note-form on ISAMUX (aka "ISANS")
3 A fixed number of additional (hidden) bits, conceptually a "namespace", that go directly and non-optionally
4 into the instruction decode phase, extending (in each implementation) the
5 opcode length to 16+N, 32+N, 48+N, where N is a hard fixed quantity on
6 a per-implementor basis.
8 Where the opcode is normally loaded from the location at the PC, the extra
9 bits, set via a CSR, are mandatorially appended to every instruction: hence why they are described as "hidden" opcode bits, and as a "namespace".
11 The parallels with c++ "using namespace" are direct and clear.
15 Note that this is a hypothetical format, yet TBD, where particular attention
16 needs to be paid to the fact that there is an "immediate" version of CSRRW
17 (with 5 bits of immediate) that could save a lot of space in binaries.
21 |1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0|
22 |------------------------------ |-------|---------------------|-|
23 |reserved reserved reserved reserved reserved | foreignarch |1|
24 |custom | reserved | official|B| rvcpage |0|
29 * when bit 0 is 0, "RV" mode is selected.
30 * in RV mode, bits 1 thru 5 provide up to 16 possible alternative meanings (namespaces) for 16 Bit opcodes. "pages" if you will. The top bit indicates custom meanings. When set to 0, the top bit is for official usage.
31 * Bits 15 thru 23 are reserved.
32 * Bits 24 thru 31 are for custom usage.
33 * bit 6 ("B") is LE/BE
37 * 0b0000 STANDARD (2019) RVC
42 * 0b1000 custom 16 bit opcode meanings 1
43 * 0b1001 custom 16 bit opcode meanings 2
48 * when bit 0 is 1, "Foreign arch" mode is selected.
49 * Bits 1 thru 7 are a table of foreign arches.
50 * when the MSB is 1, this is for custom use.
51 * when the MSB is 0, bits 1 thru 6 are reserved for 64 possible official foreign archs.
53 Foreign archs could be (examples):
60 * 0b0010000 Java Bytecode
61 * 0b0010001 N.E.Other Bytecode
63 * 0b1000000 custom foreign arch 1
64 * 0b1000001 custom foreign arch 2
67 Note that "official" foreign archs have a binary value where the MSB is zero,
68 and custom foreign archs have a binary value where the MSB is 1.
70 # Namespaces are permitted to swap to new state <a name="stateswap"></a>
72 In each privilege level, on a change of ISANS (whether through manual setting of ISANS or through trap entry or exit changing the ISANS CSR), an implementation is permitted to completely and arbitrarily switch not only the instruction set, it is permitted to switch to a new bank of CSRs (or a subset of the same), and even to switch to a new PC.
74 This to occur immediately and atomically at the point at which the change in ISANS occurs.
76 The most obvious application of this is for Foreign Archs, which may have their own completely separate PC. Thus, foreign assembly code and RISCV assembly code need not be mixed in the same binary.
78 Further use-cases may be envisaged however great care needs to be taken to not cause massive complications for JIT emulation, as the RV ISANS is unary encoded (2^31 permutations).
80 In addition, the state information of *all* namespaces has to be saved and restored on a context-switch (unless the SP is also switched as part of the state!) which is quite severely burdensome and getting exceptionally complex.
82 Switching CSR, PC (and potentially SP) and other state on a NS change in the RISCV unary NS therefore needs to be done wisely and responsibly, i.e. minimised!
84 To be discussed. Context <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/x-uFZDXiOxY/27QDW5KvBQAJ>
86 # Privileged Modes / Traps <a name="privtraps"></a>
88 An additional WLRL CSR per priv-level named "LAST-ISANS" is required, and
89 another called "TRAP-ISANS"
90 These mirrors the ISANS CSR, and, on a trap, the current ISANS in
91 that privilege level is atomically
92 transferred into LAST-ISANS by the hardware, and ISANS in that trap
93 is set to TRAP-ISANS. Hardware is *only then* permitted to modify the PC to
94 begin execution of the trap.
96 On exit from the trap, LAST-ISANS is copied into the ISANS CSR, and
97 LAST-ISANS is set to TRAP-ISANS. *Only then* is the hardware permitted
98 to modify the PC to begin execution where the trap left off.
100 This is identical to how xepc is handled.
102 Note 1: in the case of Supervisor Mode (context switches in particular),
103 saving and changing of LAST-ISANS (to and from the stack) must be done
104 atomically and under the protection of the SIE bit. Failure to do so
105 could result in corruption of LAST-ISANS when multiple traps occur in
106 the same privilege level.
108 Note 2: question - should the trap due to illegal (unsupported) values
109 written into LAST-ISANS occur when the *software* writes to LAST-ISANS,
110 or when the *trap* (on exit) writes into LAST-ISANS? this latter seems
111 fraught: a trap, on exit, causing another trap??
113 Per-privilege-level pseudocode (there exists UISANS, UTRAPISANS, ULASTISANS,
114 MISANS, MTRAPISANS, MLASTISANS and so on):
120 LAST-ISANS = ISANS // record the old NS
121 ISANS = TRAP_ISANS // traps are executed in "trap" NS
129 LAST-ISANS = TRAP_ISANS
134 # Why not have TRAP-ISANS as a vector table, matching mtvec? <a name="trap-isans-vec"></a>
136 Use case to be determined. Rather than be a global per-priv-level value,
137 TRAP-ISANS is a table of length exactly equal to the mtvec/utvec/stvec table,
138 with corresponding entries that specify the assembly-code namespace in which
139 the trap handler routine is written.
141 Open question: see <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IAhyOqEZoWA/BM0G3J2zBgAJ>
147 LAST-ISANS = ISANS // record the old NS
148 ISANS = TRAP_ISANS_VEC[xcause] // traps are executed in "trap" NS
156 LAST-ISANS = TRAP_ISANS_VEC[x_cause]
161 # Is this like MISA? <a name="misa"></a>
165 * MISA's space is entirely taken up (and running out).
166 * There is no allocation (provision) for custom extensions.
167 * MISA switches on and off entire extensions: ISAMUX/NS may be used to switch multiple opcodes (present and future), to alternate meanings.
168 * MISA is WARL and is inaccessible from everything but M-Mode (not even readable).
170 MISA is therefore wholly unsuited to U-Mode usage; ISANS is specifically permitted to be called by userspace to switch (with no stalling) between namespaces, repeatedly and in quick succession.
172 # What happens if this scheme is not adopted? Why is it better than leaving things well alone? <a name="laissezfaire"></a>
174 At the first sign of an emergency non-backwards compatible and unavoidable
175 change to the *frozen* RISCV *official* Standards, the entire RISCV
176 community is fragmented and divided into two:
178 * Those vendors that are hardware compatible with the legacy standard.
179 * Those that are compatible with the new standard.
181 *These two communities would be mutually exclusively incompatible*. If
182 a second emergency occurs, RISCV becomes even less tenable.
184 Hardware that wished to be "compatible" with either flavour would require
185 JIT or offline static binary recompilation. No vendor would willingly
186 accept this as a condition of the standards divergence in the first place,
187 locking up decision making to the detriment of RISCV as a whole.
189 By providing a "safety valve" in the form of a hidden namespace, at least
190 newer hardware has the option to implement both (or more) variations,
191 *and still apply for Certification*.
193 However to also allow "legacy" hardware to at least be JIT soft
194 compatible, some very strict rules *must* be adhered to, that appear at
195 first sight not to make any sense.
197 It's complicated in other words!
199 # Surely it's okay to just tell people to use 48-bit encodings? <a name="use48bit"></a>
201 Short answer: it doesn't help resolve conflicts, and costs hardware and
202 redesigns to do so. Softcores in cost-sensitive embedded applications may
203 even not actually be able to fit the required 48 bit instruction decode engine
204 into a (small, ICE40) FPGA. 48-bit instruction decoding is much more complex
205 than straight 32-bit decoding, requiring a queue.
207 Second answer: conflicts can still occur in the (unregulated, custom) 48-bit
208 space, which *could* be resolved by ISAMUX/ISANS as applied to the *48* bit
209 space in exactly the same way. And the 64-bit space.
211 # Why not leave this to individual custom vendors to solve on a case by case basis? <a name="case-by-case"></a>
213 The suggestion was raised that a custom extension vendor could create
214 their own CSR that selects between conflicting namespaces that resolve
215 the meaning of the exact same opcode. This to be done by all and any
216 vendors, as they see fit, with little to no collaboration or coordination
217 towards standardisation in any form.
219 The problems with this approach are numerous, when presented to a
220 worldwide context that the UNIX Platform, in particular, has to face
221 (where the embedded platform does not)
223 First: lack of coordination, in the proliferation of arbitrary solutions,
224 has to primarily be borne by gcc, binutils, LLVM and other compilers.
226 Secondly: CSR space is precious. With each vendor likely needing only one
227 or two bits to express the namespace collision avoidance, if they make
228 even a token effort to use worldwide unique CSRs (an effort that would
229 benefit compiler writers), the CSR register space is quickly exhausted.
231 Thirdly: JIT Emulation of such an unregulated space becomes just as
232 much hell as it is for compiler writers. In addition, if two vendors
233 use conflicting CSR addresses, the only sane way to tell the emulator
234 what to do is to give the emulator a runtime commandline argument.
236 Fourthly: with each vendor coming up with their own way of handling
237 conflicts, not only are the chances of mistakes higher, it is against the
238 very principles of collaboration and cooperation that save vendors money
239 on development and ongoing maintenance. Each custom vendor will have
240 to maintain their own separate hard fork of the toolchain and software,
241 which is well known to result in security vulnerabilities.
243 By coordinating and managing the allocation of namespace bits (unary
244 or binary) the above issues are solved. CSR space is no longer wasted,
245 compiler and JIT software writers have an easier time, clashes are
246 avoided, and RISCV is stabilised and has a trustable long term future.
248 # Why ISAMUX / ISANS has to be WLRL and mandatory trap on illegal writes <a name="wlrlmandatorytrap"></a>
250 The namespaces, set by bits in the CSR, are functionally directly
251 equivalent to c++ namespaces, even down to the use of braces.
253 WARL, by allowing implementors to choose the value, prevents and prohibits
254 the critical and necessary raising of an exception that would begin the
255 JIT process in the case of ongoing standards evolution.
257 Without this opportunity, an implementation has no reliable guaranteed way of knowing
258 when to drop into full JIT mode,
259 which is the only guaranteed way to distinguish
260 any given conflicting opcode. It is as if the c++
261 standard was given a similar optional
262 opportunity to completely ignore the
263 "using namespace" prefix!
267 Ok so I trust it's now clear why WLRL (thanks Allen) is needed.
269 When Dan raised the WARL concern initially a situation was masked by
270 the conflict, that if gone unnoticed would jeapordise ISAMUX/ISANS
271 entirely. Actually, two separate errors. So thank you for raising the
274 The situation arises when foreign archs are to be given their own NS
275 bit. MIPS is allocated bit 8, x86 bit 9, whilst LE/BE is given bit 0,
276 RVCv2 bit 1 andso on. All of this potential rather than actual, clearly.
278 Imagine then that software tries to write and set not just bit 8 and
279 bit 9, it also tries to set bit 0 and 1 as well.
281 This *IS* on the face of it a legitimate reason to make ISAMUX/ISANS WARL.
283 However it masks a fundamental flaw that has to be addressed, which
284 brings us back much closer to the original design of 18 months ago,
285 and it's highlighted thus:
287 x86 and simultaneous RVCv2 modes are total nonsense in the first place!
289 The solution instead is to have a NS bit (bit0) that SPECIFICALLY
290 determines if the arch is RV or not. If 0, the rest of the ISAMUX/ISANS
291 is very specifically RV *only*, and if 1, the ISAMUX/ISANS is a *binary*
292 table of foreign architectures and foreign architectures only.
294 Exactly how many bits are used for the foreign arch table, is to
295 be determined. 7 bits, one of which is reserved for custom usage,
296 leaving a whopping 64 possible "official" foreign instruction sets to
297 be hardware-supported/JIT-emulated seems to be sufficiently gratuitous,
300 One of those could even be Java Bytecode!
302 Now, it could *hypothetically* be argued that the permutation of setting
303 LE/BE and MIPS for example is desirable. A simple analysis shows this
304 not to be the case: once in the MIPS foreign NS, it is the MIPS hardware
305 implementation that should have its own way of setting and managing its
306 LE/BE mode, because to do otherwise drastically interferes with MIPS
307 binary compatibility.
309 Thus, it is officially Not Our Problem: only flipping into one foreign
310 arch at a time makes sense, thus this has to be reflected in the
311 ISAMUX/ISANS CSR itself, completely side-stepping the (apparent) need
312 to make the NS CSR WARL (which would not work anyway, as previously
315 So, thank you, again, Dan, for raising this. It would have completely
316 jeapordised ISAMUX/NS if not spotted.
318 The second issue is: how does any hardware system, whether it support
319 ISANS or not, and whether any future hardware supports some Namespaces
320 and, in a transitive fashion, has to support *more* future namespaces,
321 through JIT emulation, if this is not planned properly in advance?
323 Let us take the simple case first: a current 2019 RISCV fully compliant
324 RV64GC UNIX capable system (with mandatory traps on all unsupported CSRs).
326 Fast forward 20 years, there are now 5 ISAMUX/NS unary bits, and 3
327 foreign arch binary table entries.
329 Such a system is perfectly possible of software JIT emulating ALL of these
330 options because the write to the (illegal, for that system) ISAMUX/NS
331 CSR generates the trap that is needed for that system ti begin JIT mode.
333 (This again emphasises exactly why the trap is mandatory).
335 Now let us take the case of a hypothetical system from say 2021 that
336 implements RVCv2 at the hardware level.
338 Fast forward 20 years: if the CSR were made WARL, that system would be
339 absolutely screwed. The implementor would be under the false impression
340 that ignoring setting of "illegal" bits was acceptable, making the
341 transition to JIT mode flat-out impossible to detect.
343 When this is considered transitively, considering all future additions to
344 the NS, and all permutations, it can be logically deduced that there is
345 a need to reserve a *full* set of bits in the ISAMUX/NS CSR *in advance*.
347 i.e. that *right now*, in the year 2019, the entire ISAMUX/NS CSR cannot
348 be added to piecemeal, the full 32 (or 64) bits *has* to be reserved,
349 and reserved bits set at zero.
351 Furthermore, if any software attempts to write to those reserved bits,
352 it *must* be treated just as if those bits were distinct and nonexistent
353 CSRs, and a trap raised.
355 It makes more sense to consider each NS as having its own completely
356 separate CSR, which, if it does not exist, clearly it should be obvious
357 that, as an unsupported CSR, a trap should be raised (and JIT emulation
360 However given that only the one bit is needed (in RV NS Mode, not
361 Foreign NS Mode), it would be terribly wasteful of the CSRs to do this,
362 despite it being technically correct and much easier to understand why
363 trap raising is so essential (mandatory).
365 This again should emphasise how to mentally get one's head round this
366 mind-bendingly complex problem space: think of each NS bit as its own
367 totally separate CSR that every implementor is free and clear to implement
368 (or leave to JIT Emulation) as they see fit.
370 Only then does the mandatory need to trap on write really start to hit
371 home, as does the need to preallocate a full set of reserved zero values
374 Lastly, I *think* it's ok to only reserve say 32 bits, and, in 50 years
375 time if that genuinely is not enough, start the process all over again
376 with a new CSR. ISAMUX2/NS2.
378 Subdivision of the RV NS (support for RVCv3/4/5/RV16 without wasting
379 precious CSR bits) best left for discussion another time, the above is
380 a heck of a lot to absorb, already.
382 # Alternative RVC 16 Bit Opcode meanings
384 Ok, here is appropriate to raise an idea how to cover RVC and future
385 variants, including RV16.
387 Just as with foreign archs, and you quite rightly highlight above, it
388 makes absolutely no sense to try to select both RVCv1, v2, v3 and so on,
389 all simultaneously. An unary bit vector for RVC modes, changing the 16
390 BIT opcode space meaning, is wasteful and again has us believe that WARL
393 The correct thing to do is, again, just like with foreign archs, to
394 treat RVCs as a *binary* namespace selector. Bits 1 thru 3 would give
395 8 possible completely new alternative meanings, just like how the Z80
396 and the 286 and 386 used to do bank switching.
398 All zeros is clearly reserved for the present RVC. 0b001 for RVCv2. 0b010
399 for RV16 (look it up) and there should definitely be room reserved here
400 for custom reencodings of the 16 bit opcode space.
402 # Why WARL will not work and why WLRL is required
404 WARL requires a follow-up read of the CSR to ascertain what heuristic
405 the hardware *might* have applied, and if that procedure is followed in
406 this proposal, performance even on hardware would be severely compromised.
408 In addition when switching to foreign architectures, the switch has to
409 be done atomically and guaranteed to occur.
411 In the case of JIT emulation, the WARL "detection" code will be in an
412 assembly language that is alien to hardware.
414 Support for both assembly languages immediately after the CSR write
415 is clearly impossible, this leaves no other option but to have the CSR
416 be WLRL (on all platforms) and for traps to be mandatory (on the UNIX
419 # Is it strictly necessary for foreign archs to switch back? <a name="foreignswitch"></a>
421 No, because LAST-ISANS handles the setting and unsetting of the ISANS CSR
422 in a completely transparent fashion as far as the foreign arch is concerned.
423 Supervisor or Hypervisor traps take care of the context switch in a way
424 that the user mode (or guest) need not be aware of, in any way.
426 Thus, in e.g. Hypervisor Mode, the foreign guest arch has no knowledge
427 or need to know that the hypervisor is flipping back to RV at the time of
430 Note however that this is **not** the same as the foreign arch executing
431 *foreign* traps! Foreign architecture trap and interrupt handling mechanisms
432 are **out of scope** of this document and MUST be handled by the foreign
433 architecture implementation in a completely transparent fashion that in
434 no way interacts or interferes with this proposal.
436 # Can we have dynamic declaration and runtime declaration of capabilities? <a name="dynamic"></a>
438 Answer: don't know (yet). Quoted from Rogier:
440 > "A SOC may have several devices that one may want to directly control
441 > with custom instructions. If independent vendors use the same opcodes you
442 > either have to change the encodings for every different chip (not very
443 > nice for software) or you can give the device an ID which is defined in
444 > some device tree or something like that and use that."
446 dynamic detection wasn't originally planned: static
447 compilation was envisaged to solve the need, with a table of
448 mvendorid-marchid-isamux/isans being maintained inside gcc / binutils /
449 llvm (or separate library?) that, like the linux kernel ARCH table,
450 requires a world-wide atomic "git commit" to add globally-unique
451 registered entries that map functionality to actual namespaces.
453 where that goes wrong is if there is ever a pair (or more) of vendors
454 that use the exact same custom feature that maps to different opcodes,
455 a statically-compiled binary has no hope of executing natively on both
458 at that point: yes, something akin to device-tree would be needed.
460 # Open Questions <a name="open-questions"></a>
462 This section from a post by Rogier Bruisse
463 <http://hands.com/~lkcl/gmail_re_isadev_isamux.html>
465 ## is the ISANS CSR a 32 or XLEN bit value? <a name="isans-32-or-xlen"></a>
467 This is partly answered in another FAQ above: if 32 bits is not enough
468 for a full suite of official, custom-with-atomic-registration and custom-without
469 then a second CSR group (ISANS2) may be added at a future date (10-20 years
472 32 bits would not inconvenience RV32, and implementors wishing to
473 make significant altnernative modifications to opcodes in the RV32 ISA space
474 could do so without the burden of having to support a split 32/LO 32/HI
475 CSR across two locations.
477 ## is the ISANS a flat number space or should some bits be reserved for use as flags?
479 See 16-bit RV namespace "page" concept, above. Some bits have to be unary
480 (multiple simultaneous features such as LE/BE in one bit, and augmented
481 Floating-point rounding / clipping in another), whilst others definitely
482 need to be binary (the most obvious one being "paging" in the space currently
485 ## should the ISANS space be partitioned between reserved, custom with registration guaranteed non clashing, custom, very likely non clashing?
489 ## should only compiler visible/generated constant setting with CSRRWI and/or using a clearly recognisable LI/LUI be accommodated or should dynamic setting be accommodated as well?
491 This is almost certainly a software design issue, not so much a hardware
494 ## How should the ISANS be (re)stored in a trap and in context switch?
496 See section above on privilege mode: LAST-ISANS has been introduced that
497 mirrors (x)CAUSE and (x)EPC pretty much exactly. Context switches change
498 uepc just before exit from the trap, in order to change the user-mode PC
499 to switch to a new process, and ulast-isans can - must - be treated in
500 exactly the same way. When the context switch sets ulast-isans (and uepc),
501 the hardware flips both ulast-isans into uisans and uepc into pc (atomically):
502 both the new NS and the new PC activate immediately, on return to usermode.
506 ## Should the mechanism accommodate "foreign ISA's" and if so how does one restore the ISA.
508 See section above on LAST-ISANS. With the introduction of LAST-ISANS, the
509 change is entirely transparent, and handled by the Supervisor (or Hypervisor)
510 trap, in a fashion that the foreign ISA need not even know of the existence
513 ## Where is the default ISA stored and what is responsible for what it is after
518 * calling into a dynamically linked library
520 * changing privilege levels
522 These first four are entirely at the discretion of (and the
523 responsibility of) the software. There is precedent for most of these
524 having been implemented, historically, at some point, in relation to
525 LE/BE mode CSRs in other hardware (MIPSEL vs MIPS distros for example).
527 Traps are responsible for saving LAST-ISANS on the stack, exactly as they
528 are also responsible for saving other context-sensitive information such
529 as the registers and xEPC.
531 The hardware is responsible for atomically switching out ISANS into the
532 relevant xLAST-ISANS (and back again on exit). See Privileged Traps,
535 ## If the ISANS is just bits of an instruction that are to be prefixed by the cpu, can those bits contain immediates? Register numbers?
537 The concept of a CSR containing an immediate makes no sense. The concept
538 of a CSR containing a register number, the contents of which would, presumably,
539 be inserted into the NS, would immediately make that register a permanent
540 and irrevocably reserved register that could not be utilised for any other
543 This is what the CSRs are supposed to be for!
545 It would be better just to have a second CSR - ISANS2 - potentially even ISANS3
546 in 60+ years time, rather than try to use a GPR for the purposes for which CSRs
549 ## How does the system indicate a namespace is not recognised? Does it trap or can/must a recoverable mechanism be provided?
551 It doesn't "indicate" that a namespace is not recognised. WLRL fields only
552 hold supported values. If the hardware cannot hold the value, a trap
553 **MUST** be thrown (in the UNIX platform), and at that point it becomes the
554 responsibility of software to deal with it.
556 ## What are the security implications? Can some ISA namespaces be set by user space?
558 Of course they can. It becomes the responsibility of the Supervisor Mode
559 (the kernel) to treat ISANS in a fashion orthogonal to the PC. If the OS
560 is not capable of properly context-switching securely by setting the right
561 PC, it's not going to be capable of properly looking after changes to ISANS.
563 ## Does the validity of an ISA namespace depend on privilege level? If so how?
565 The question does not exactly make sense, and may need a re-reading of the
566 section on how Privilege Modes, above. In RISC-V, privilege modes do not
567 actually change very much state of the system: the absolute minimum changes
568 are made (swapped out) - xEPC, xSTATUS and so on - and the privilege mode
569 is expected to handle the context switching (or other actions) itself.
571 ISANS - through LAST-ISANS - is absolutely no different. The trap and the
572 kernel (Supervisor or Hypervisor) are provided the *mechanism* by which
573 ISA Namespace *may* be set: it is up to the software to use that mechanism
574 correctly, just as the software is expected to use the mechanisms provided
575 to correctly implement context-switching by saving and restoring register
576 files, the PC, and other state. The NS effectively becomes just another