1 # Note-form on ISAMUX (aka "ISANS")
3 A fixed number of additional (hidden) bits, conceptually a "namespace", that go directly and non-optionally
4 into the instruction decode phase, extending (in each implementation) the
5 opcode length to 16+N, 32+N, 48+N, where N is a hard fixed quantity on
6 a per-implementor basis.
8 Where the opcode is normally loaded from the location at the PC, the extra
9 bits, set via a CSR, are mandatorially appended to every instruction: hence why they are described as "hidden" opcode bits, and as a "namespace".
11 The parallels with c++ "using namespace" are direct and clear.
12 Alternative conceptual ways to understand this concept include
15 TODO: reserve some bits which permit the namespace (escape-sequence) to
16 be relevant for a fixed number of instructions at a time. Caveat:
17 allowing such a countdown to cross branch-points is unwise (illegal
20 An example of a pre-existing "namespace" switch that has been in
21 prevalent use for several decades (SPARC and other architectures):
22 dynamic runtime selectability of littel-endian / big-endian "meaning"
23 of instructions by way of a "mode switch" instruction (of some kind).
25 That "switch" is in effect a 33rd (hidden) bit that is part of the opcode,
26 going directly into the mux / decode phase of instruction decode, and
27 thus qualifies categorically as a "namespace". This proposal both formalises
28 and generalises that concept.
32 Note that this is a hypothetical format, yet TBD, where particular attention
33 needs to be paid to the fact that there is an "immediate" version of CSRRW
34 (with 5 bits of immediate) that could save a lot of space in binaries.
38 |1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0|
39 |------------------------------ |-------|---------------------|-|
40 |1 custom custom custom custom custom | foreignarch |1|
41 |0 reserved reserved reserved reserved reserved | foreignarch |1|
42 |custom | reserved | official|B| rvcpage |0|
47 * when bit 0 is 0, "RV" mode is selected.
48 * in RV mode, bits 1 thru 5 provide up to 16 possible alternative meanings (namespaces) for 16 Bit opcodes. "pages" if you will. The top bit indicates custom meanings. When set to 0, the top bit is for official usage.
49 * Bits 15 thru 23 are reserved.
50 * Bits 24 thru 31 are for custom usage.
51 * bit 6 ("B") is LE/BE
55 * 0b0000 STANDARD (2019) RVC
60 * 0b1000 custom 16 bit opcode meanings 1
61 * 0b1001 custom 16 bit opcode meanings 2
66 * when bit 0 is 1, "Foreign arch" mode is selected.
67 * Bits 1 thru 7 are a table of foreign arches.
68 * when the MSB is 1, this is for custom use.
69 * when the MSB is 0, bits 1 thru 6 are reserved for 64 possible official foreign archs.
71 Foreign archs could be (examples):
78 * 0b0010000 Java Bytecode
79 * 0b0010001 N.E.Other Bytecode
81 * 0b1000000 custom foreign arch 1
82 * 0b1000001 custom foreign arch 2
85 Note that "official" foreign archs have a binary value where the MSB is zero,
86 and custom foreign archs have a binary value where the MSB is 1.
88 # Namespaces are permitted to swap to new state <a name="stateswap"></a>
90 In each privilege level, on a change of ISANS (whether through manual setting of ISANS or through trap entry or exit changing the ISANS CSR), an implementation is permitted to completely and arbitrarily switch not only the instruction set, it is permitted to switch to a new bank of CSRs (or a subset of the same), and even to switch to a new PC.
92 This to occur immediately and atomically at the point at which the change in ISANS occurs.
94 The most obvious application of this is for Foreign Archs, which may have their own completely separate PC. Thus, foreign assembly code and RISCV assembly code need not be mixed in the same binary.
96 Further use-cases may be envisaged however great care needs to be taken to not cause massive complications for JIT emulation, as the RV ISANS is unary encoded (2^31 permutations).
98 In addition, the state information of *all* namespaces has to be saved and restored on a context-switch (unless the SP is also switched as part of the state!) which is quite severely burdensome and getting exceptionally complex.
100 Switching CSR, PC (and potentially SP) and other state on a NS change in the RISCV unary NS therefore needs to be done wisely and responsibly, i.e. minimised!
102 To be discussed. Context <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/x-uFZDXiOxY/27QDW5KvBQAJ>
104 # Privileged Modes / Traps <a name="privtraps"></a>
106 An additional WLRL CSR per priv-level named "LAST-ISANS" is required, and
107 another called "TRAP-ISANS"
108 These mirrors the ISANS CSR, and, on a trap, the current ISANS in
109 that privilege level is atomically
110 transferred into LAST-ISANS by the hardware, and ISANS in that trap
111 is set to TRAP-ISANS. Hardware is *only then* permitted to modify the PC to
112 begin execution of the trap.
114 On exit from the trap, LAST-ISANS is copied into the ISANS CSR, and
115 LAST-ISANS is set to TRAP-ISANS. *Only then* is the hardware permitted
116 to modify the PC to begin execution where the trap left off.
118 This is identical to how xepc is handled.
120 Note 1: in the case of Supervisor Mode (context switches in particular),
121 saving and changing of LAST-ISANS (to and from the stack) must be done
122 atomically and under the protection of the SIE bit. Failure to do so
123 could result in corruption of LAST-ISANS when multiple traps occur in
124 the same privilege level.
126 Note 2: question - should the trap due to illegal (unsupported) values
127 written into LAST-ISANS occur when the *software* writes to LAST-ISANS,
128 or when the *trap* (on exit) writes into LAST-ISANS? this latter seems
129 fraught: a trap, on exit, causing another trap??
131 Per-privilege-level pseudocode (there exists UISANS, UTRAPISANS, ULASTISANS,
132 MISANS, MTRAPISANS, MLASTISANS and so on):
137 LAST-ISANS = ISANS // record the old NS
138 ISANS = TRAP_ISANS // traps are executed in "trap" NS
146 LAST-ISANS = TRAP_ISANS
150 # Alternative RVC 16 Bit Opcode meanings
152 Here is appropriate to raise an idea how to cover RVC and future
153 variants, including RV16.
155 Just as with foreign archs, and you quite rightly highlight above, it
156 makes absolutely no sense to try to select both RVCv1, v2, v3 and so on,
157 all simultaneously. An unary bit vector for RVC modes, changing the 16
158 BIT opcode space meaning, is wasteful and again has us believe that WARL
161 The correct thing to do is, again, just like with foreign archs, to
162 treat RVCs as a *binary* namespace selector. Bits 1 thru 3 would give
163 8 possible completely new alternative meanings, just like how the Z80
164 and the 286 and 386 used to do bank switching.
166 All zeros is clearly reserved for the present RVC. 0b001 for RVCv2. 0b010
167 for RV16 (look it up) and there should definitely be room reserved here
168 for custom reencodings of the 16 bit opcode space.
172 ## Why not have TRAP-ISANS as a vector table, matching mtvec? <a name="trap-isans-vec"></a>
174 Use case to be determined. Rather than be a global per-priv-level value,
175 TRAP-ISANS is a table of length exactly equal to the mtvec/utvec/stvec table,
176 with corresponding entries that specify the assembly-code namespace in which
177 the trap handler routine is written.
179 Open question: see <https://groups.google.com/a/groups.riscv.org/d/msg/isa-dev/IAhyOqEZoWA/BM0G3J2zBgAJ>
184 LAST-ISANS = ISANS // record the old NS
185 ISANS = TRAP_ISANS_VEC[xcause] // traps are executed in "trap" NS
193 LAST-ISANS = TRAP_ISANS_VEC[x_cause]
197 ## Is this like MISA? <a name="misa"></a>
201 * MISA's space is entirely taken up (and running out).
202 * There is no allocation (provision) for custom extensions.
203 * MISA switches on and off entire extensions: ISAMUX/NS may be used to switch multiple opcodes (present and future), to alternate meanings.
204 * MISA is WARL and is inaccessible from everything but M-Mode (not even readable).
206 MISA is therefore wholly unsuited to U-Mode usage; ISANS is specifically permitted to be called by userspace to switch (with no stalling) between namespaces, repeatedly and in quick succession.
208 ## What happens if this scheme is not adopted? Why is it better than leaving things well alone? <a name="laissezfaire"></a>
210 At the first sign of an emergency non-backwards compatible and unavoidable
211 change to the *frozen* RISCV *official* Standards, the entire RISCV
212 community is fragmented and divided into two:
214 * Those vendors that are hardware compatible with the legacy standard.
215 * Those that are compatible with the new standard.
217 *These two communities would be mutually exclusively incompatible*. If
218 a second emergency occurs, RISCV becomes even less tenable.
220 Hardware that wished to be "compatible" with either flavour would require
221 JIT or offline static binary recompilation. No vendor would willingly
222 accept this as a condition of the standards divergence in the first place,
223 locking up decision making to the detriment of RISCV as a whole.
225 By providing a "safety valve" in the form of a hidden namespace, at least
226 newer hardware has the option to implement both (or more) variations,
227 *and still apply for Certification*.
229 However to also allow "legacy" hardware to at least be JIT soft
230 compatible, some very strict rules *must* be adhered to, that appear at
231 first sight not to make any sense.
233 It's complicated in other words!
235 ## Surely it's okay to just tell people to use 48-bit encodings? <a name="use48bit"></a>
237 Short answer: it doesn't help resolve conflicts, and costs hardware and
238 redesigns to do so. Softcores in cost-sensitive embedded applications may
239 even not actually be able to fit the required 48 bit instruction decode engine
240 into a (small, ICE40) FPGA. 48-bit instruction decoding is much more complex
241 than straight 32-bit decoding, requiring a queue.
243 Second answer: conflicts can still occur in the (unregulated, custom) 48-bit
244 space, which *could* be resolved by ISAMUX/ISANS as applied to the *48* bit
245 space in exactly the same way. And the 64-bit space.
247 ## Why not leave this to individual custom vendors to solve on a case by case basis? <a name="case-by-case"></a>
249 The suggestion was raised that a custom extension vendor could create
250 their own CSR that selects between conflicting namespaces that resolve
251 the meaning of the exact same opcode. This to be done by all and any
252 vendors, as they see fit, with little to no collaboration or coordination
253 towards standardisation in any form.
255 The problems with this approach are numerous, when presented to a
256 worldwide context that the UNIX Platform, in particular, has to face
257 (where the embedded platform does not)
259 First: lack of coordination, in the proliferation of arbitrary solutions,
260 has to primarily be borne by gcc, binutils, LLVM and other compilers.
262 Secondly: CSR space is precious. With each vendor likely needing only one
263 or two bits to express the namespace collision avoidance, if they make
264 even a token effort to use worldwide unique CSRs (an effort that would
265 benefit compiler writers), the CSR register space is quickly exhausted.
267 Thirdly: JIT Emulation of such an unregulated space becomes just as
268 much hell as it is for compiler writers. In addition, if two vendors
269 use conflicting CSR addresses, the only sane way to tell the emulator
270 what to do is to give the emulator a runtime commandline argument.
272 Fourthly: with each vendor coming up with their own way of handling
273 conflicts, not only are the chances of mistakes higher, it is against the
274 very principles of collaboration and cooperation that save vendors money
275 on development and ongoing maintenance. Each custom vendor will have
276 to maintain their own separate hard fork of the toolchain and software,
277 which is well known to result in security vulnerabilities.
279 By coordinating and managing the allocation of namespace bits (unary
280 or binary) the above issues are solved. CSR space is no longer wasted,
281 compiler and JIT software writers have an easier time, clashes are
282 avoided, and RISCV is stabilised and has a trustable long term future.
284 ## Why ISAMUX / ISANS has to be WLRL and mandatory trap on illegal writes <a name="wlrlmandatorytrap"></a>
286 The namespaces, set by bits in the CSR, are functionally directly
287 equivalent to c++ namespaces, even down to the use of braces.
289 WARL, by allowing implementors to choose the value, prevents and prohibits
290 the critical and necessary raising of an exception that would begin the
291 JIT process in the case of ongoing standards evolution.
293 Without this opportunity, an implementation has no reliable guaranteed way of knowing
294 when to drop into full JIT mode,
295 which is the only guaranteed way to distinguish
296 any given conflicting opcode. It is as if the c++
297 standard was given a similar optional
298 opportunity to completely ignore the
299 "using namespace" prefix!
303 Ok so I trust it's now clear why WLRL (thanks Allen) is needed.
305 When Dan raised the WARL concern initially a situation was masked by
306 the conflict, that if gone unnoticed would jeapordise ISAMUX/ISANS
307 entirely. Actually, two separate errors. So thank you for raising the
310 The situation arises when foreign archs are to be given their own NS
311 bit. MIPS is allocated bit 8, x86 bit 9, whilst LE/BE is given bit 0,
312 RVCv2 bit 1 andso on. All of this potential rather than actual, clearly.
314 Imagine then that software tries to write and set not just bit 8 and
315 bit 9, it also tries to set bit 0 and 1 as well.
317 This *IS* on the face of it a legitimate reason to make ISAMUX/ISANS WARL.
319 However it masks a fundamental flaw that has to be addressed, which
320 brings us back much closer to the original design of 18 months ago,
321 and it's highlighted thus:
323 x86 and simultaneous RVCv2 modes are total nonsense in the first place!
325 The solution instead is to have a NS bit (bit0) that SPECIFICALLY
326 determines if the arch is RV or not. If 0, the rest of the ISAMUX/ISANS
327 is very specifically RV *only*, and if 1, the ISAMUX/ISANS is a *binary*
328 table of foreign architectures and foreign architectures only.
330 Exactly how many bits are used for the foreign arch table, is to
331 be determined. 7 bits, one of which is reserved for custom usage,
332 leaving a whopping 64 possible "official" foreign instruction sets to
333 be hardware-supported/JIT-emulated seems to be sufficiently gratuitous,
336 One of those could even be Java Bytecode!
338 Now, it could *hypothetically* be argued that the permutation of setting
339 LE/BE and MIPS for example is desirable. A simple analysis shows this
340 not to be the case: once in the MIPS foreign NS, it is the MIPS hardware
341 implementation that should have its own way of setting and managing its
342 LE/BE mode, because to do otherwise drastically interferes with MIPS
343 binary compatibility.
345 Thus, it is officially Not Our Problem: only flipping into one foreign
346 arch at a time makes sense, thus this has to be reflected in the
347 ISAMUX/ISANS CSR itself, completely side-stepping the (apparent) need
348 to make the NS CSR WARL (which would not work anyway, as previously
351 So, thank you, again, Dan, for raising this. It would have completely
352 jeapordised ISAMUX/NS if not spotted.
354 The second issue is: how does any hardware system, whether it support
355 ISANS or not, and whether any future hardware supports some Namespaces
356 and, in a transitive fashion, has to support *more* future namespaces,
357 through JIT emulation, if this is not planned properly in advance?
359 Let us take the simple case first: a current 2019 RISCV fully compliant
360 RV64GC UNIX capable system (with mandatory traps on all unsupported CSRs).
362 Fast forward 20 years, there are now 5 ISAMUX/NS unary bits, and 3
363 foreign arch binary table entries.
365 Such a system is perfectly possible of software JIT emulating ALL of these
366 options because the write to the (illegal, for that system) ISAMUX/NS
367 CSR generates the trap that is needed for that system ti begin JIT mode.
369 (This again emphasises exactly why the trap is mandatory).
371 Now let us take the case of a hypothetical system from say 2021 that
372 implements RVCv2 at the hardware level.
374 Fast forward 20 years: if the CSR were made WARL, that system would be
375 absolutely screwed. The implementor would be under the false impression
376 that ignoring setting of "illegal" bits was acceptable, making the
377 transition to JIT mode flat-out impossible to detect.
379 When this is considered transitively, considering all future additions to
380 the NS, and all permutations, it can be logically deduced that there is
381 a need to reserve a *full* set of bits in the ISAMUX/NS CSR *in advance*.
383 i.e. that *right now*, in the year 2019, the entire ISAMUX/NS CSR cannot
384 be added to piecemeal, the full 32 (or 64) bits *has* to be reserved,
385 and reserved bits set at zero.
387 Furthermore, if any software attempts to write to those reserved bits,
388 it *must* be treated just as if those bits were distinct and nonexistent
389 CSRs, and a trap raised.
391 It makes more sense to consider each NS as having its own completely
392 separate CSR, which, if it does not exist, clearly it should be obvious
393 that, as an unsupported CSR, a trap should be raised (and JIT emulation
396 However given that only the one bit is needed (in RV NS Mode, not
397 Foreign NS Mode), it would be terribly wasteful of the CSRs to do this,
398 despite it being technically correct and much easier to understand why
399 trap raising is so essential (mandatory).
401 This again should emphasise how to mentally get one's head round this
402 mind-bendingly complex problem space: think of each NS bit as its own
403 totally separate CSR that every implementor is free and clear to implement
404 (or leave to JIT Emulation) as they see fit.
406 Only then does the mandatory need to trap on write really start to hit
407 home, as does the need to preallocate a full set of reserved zero values
410 Lastly, I *think* it's ok to only reserve say 32 bits, and, in 50 years
411 time if that genuinely is not enough, start the process all over again
412 with a new CSR. ISAMUX2/NS2.
414 Subdivision of the RV NS (support for RVCv3/4/5/RV16 without wasting
415 precious CSR bits) best left for discussion another time, the above is
416 a heck of a lot to absorb, already.
418 ## Why WARL will not work and why WLRL is required
420 WARL requires a follow-up read of the CSR to ascertain what heuristic
421 the hardware *might* have applied, and if that procedure is followed in
422 this proposal, performance even on hardware would be severely compromised.
424 In addition when switching to foreign architectures, the switch has to
425 be done atomically and guaranteed to occur.
427 In the case of JIT emulation, the WARL "detection" code will be in an
428 assembly language that is alien to hardware.
430 Support for both assembly languages immediately after the CSR write
431 is clearly impossible, this leaves no other option but to have the CSR
432 be WLRL (on all platforms) and for traps to be mandatory (on the UNIX
435 ## Is it strictly necessary for foreign archs to switch back? <a name="foreignswitch"></a>
437 No, because LAST-ISANS handles the setting and unsetting of the ISANS CSR
438 in a completely transparent fashion as far as the foreign arch is concerned.
439 Supervisor or Hypervisor traps take care of the context switch in a way
440 that the user mode (or guest) need not be aware of, in any way.
442 Thus, in e.g. Hypervisor Mode, the foreign guest arch has no knowledge
443 or need to know that the hypervisor is flipping back to RV at the time of
446 Note however that this is **not** the same as the foreign arch executing
447 *foreign* traps! Foreign architecture trap and interrupt handling mechanisms
448 are **out of scope** of this document and MUST be handled by the foreign
449 architecture implementation in a completely transparent fashion that in
450 no way interacts or interferes with this proposal.
452 ## Can we have dynamic declaration and runtime declaration of capabilities? <a name="dynamic"></a>
454 Answer: don't know (yet). Quoted from Rogier:
456 > "A SOC may have several devices that one may want to directly control
457 > with custom instructions. If independent vendors use the same opcodes you
458 > either have to change the encodings for every different chip (not very
459 > nice for software) or you can give the device an ID which is defined in
460 > some device tree or something like that and use that."
462 dynamic detection wasn't originally planned: static
463 compilation was envisaged to solve the need, with a table of
464 mvendorid-marchid-isamux/isans being maintained inside gcc / binutils /
465 llvm (or separate library?) that, like the linux kernel ARCH table,
466 requires a world-wide atomic "git commit" to add globally-unique
467 registered entries that map functionality to actual namespaces.
469 where that goes wrong is if there is ever a pair (or more) of vendors
470 that use the exact same custom feature that maps to different opcodes,
471 a statically-compiled binary has no hope of executing natively on both
474 at that point: yes, something akin to device-tree would be needed.
476 # Open Questions <a name="open-questions"></a>
478 This section from a post by Rogier Bruisse
479 <http://hands.com/~lkcl/gmail_re_isadev_isamux.html>
481 ## is the ISANS CSR a 32 or XLEN bit value? <a name="isans-32-or-xlen"></a>
483 This is partly answered in another FAQ above: if 32 bits is not enough
484 for a full suite of official, custom-with-atomic-registration and custom-without
485 then a second CSR group (ISANS2) may be added at a future date (10-20 years
488 32 bits would not inconvenience RV32, and implementors wishing to
489 make significant altnernative modifications to opcodes in the RV32 ISA space
490 could do so without the burden of having to support a split 32/LO 32/HI
491 CSR across two locations.
493 ## is the ISANS a flat number space or should some bits be reserved for use as flags?
495 See 16-bit RV namespace "page" concept, above. Some bits have to be unary
496 (multiple simultaneous features such as LE/BE in one bit, and augmented
497 Floating-point rounding / clipping in another), whilst others definitely
498 need to be binary (the most obvious one being "paging" in the space currently
501 ## should the ISANS space be partitioned between reserved, custom with registration guaranteed non clashing, custom, very likely non clashing?
505 ## should only compiler visible/generated constant setting with CSRRWI and/or using a clearly recognisable LI/LUI be accommodated or should dynamic setting be accommodated as well?
507 This is almost certainly a software design issue, not so much a hardware
510 ## How should the ISANS be (re)stored in a trap and in context switch?
512 See section above on privilege mode: LAST-ISANS has been introduced that
513 mirrors (x)CAUSE and (x)EPC pretty much exactly. Context switches change
514 uepc just before exit from the trap, in order to change the user-mode PC
515 to switch to a new process, and ulast-isans can - must - be treated in
516 exactly the same way. When the context switch sets ulast-isans (and uepc),
517 the hardware flips both ulast-isans into uisans and uepc into pc (atomically):
518 both the new NS and the new PC activate immediately, on return to usermode.
522 ## Should the mechanism accommodate "foreign ISA's" and if so how does one restore the ISA.
524 See section above on LAST-ISANS. With the introduction of LAST-ISANS, the
525 change is entirely transparent, and handled by the Supervisor (or Hypervisor)
526 trap, in a fashion that the foreign ISA need not even know of the existence
529 ## Where is the default ISA stored and what is responsible for what it is after
534 * calling into a dynamically linked library
536 * changing privilege levels
538 These first four are entirely at the discretion of (and the
539 responsibility of) the software. There is precedent for most of these
540 having been implemented, historically, at some point, in relation to
541 LE/BE mode CSRs in other hardware (MIPSEL vs MIPS distros for example).
543 Traps are responsible for saving LAST-ISANS on the stack, exactly as they
544 are also responsible for saving other context-sensitive information such
545 as the registers and xEPC.
547 The hardware is responsible for atomically switching out ISANS into the
548 relevant xLAST-ISANS (and back again on exit). See Privileged Traps,
551 ## If the ISANS is just bits of an instruction that are to be prefixed by the cpu, can those bits contain immediates? Register numbers?
553 The concept of a CSR containing an immediate makes no sense. The concept
554 of a CSR containing a register number, the contents of which would, presumably,
555 be inserted into the NS, would immediately make that register a permanent
556 and irrevocably reserved register that could not be utilised for any other
559 This is what the CSRs are supposed to be for!
561 It would be better just to have a second CSR - ISANS2 - potentially even ISANS3
562 in 60+ years time, rather than try to use a GPR for the purposes for which CSRs
565 ## How does the system indicate a namespace is not recognised? Does it trap or can/must a recoverable mechanism be provided?
567 It doesn't "indicate" that a namespace is not recognised. WLRL fields only
568 hold supported values. If the hardware cannot hold the value, a trap
569 **MUST** be thrown (in the UNIX platform), and at that point it becomes the
570 responsibility of software to deal with it.
572 ## What are the security implications? Can some ISA namespaces be set by user space?
574 Of course they can. It becomes the responsibility of the Supervisor Mode
575 (the kernel) to treat ISANS in a fashion orthogonal to the PC. If the OS
576 is not capable of properly context-switching securely by setting the right
577 PC, it's not going to be capable of properly looking after changes to ISANS.
579 ## Does the validity of an ISA namespace depend on privilege level? If so how?
581 The question does not exactly make sense, and may need a re-reading of the
582 section on how Privilege Modes, above. In RISC-V, privilege modes do not
583 actually change very much state of the system: the absolute minimum changes
584 are made (swapped out) - xEPC, xSTATUS and so on - and the privilege mode
585 is expected to handle the context switching (or other actions) itself.
587 ISANS - through LAST-ISANS - is absolutely no different. The trap and the
588 kernel (Supervisor or Hypervisor) are provided the *mechanism* by which
589 ISA Namespace *may* be set: it is up to the software to use that mechanism
590 correctly, just as the software is expected to use the mechanisms provided
591 to correctly implement context-switching by saving and restoring register
592 files, the PC, and other state. The NS effectively becomes just another