Merge m5read@m5.eecs.umich.edu:/bk/m5
[gem5.git] / kern / system_events.cc
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include "encumbered/cpu/full/cpu.hh"
30 #include "kern/kernel_stats.hh"
31
32 void
33 SkipFuncEvent::process(ExecContext *xc)
34 {
35 Addr newpc = xc->regs.intRegFile[ReturnAddressReg];
36
37 DPRINTF(PCEvent, "skipping %s: pc=%x, newpc=%x\n", description,
38 xc->regs.pc, newpc);
39
40 xc->regs.pc = newpc;
41 xc->regs.npc = xc->regs.pc + sizeof(MachInst);
42
43 BranchPred *bp = xc->cpu->getBranchPred();
44 if (bp != NULL) {
45 bp->popRAS(xc->thread_num);
46 }
47 }
48
49
50 FnEvent::FnEvent(PCEventQueue *q, const std::string &desc, Stats::MainBin *bin)
51 : PCEvent(q, desc), _name(desc), mybin(bin)
52 {
53 }
54
55 void
56 FnEvent::process(ExecContext *xc)
57 {
58 if (xc->misspeculating())
59 return;
60
61 xc->system->kernelBinning->call(xc, mybin);
62 }
63
64 void
65 IdleStartEvent::process(ExecContext *xc)
66 {
67 xc->kernelStats->setIdleProcess(xc->regs.ipr[AlphaISA::IPR_PALtemp23]);
68 remove();
69 }
70
71 void
72 InterruptStartEvent::process(ExecContext *xc)
73 {
74 xc->kernelStats->mode(Kernel::interrupt);
75 }
76
77 void
78 InterruptEndEvent::process(ExecContext *xc)
79 {
80 // We go back to kernel, if we are user, inside the rti
81 // pal code we will get switched to user because of the ICM write
82 xc->kernelStats->mode(Kernel::kernel);
83 }