kernel/calc.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 // [[CITE]] Power-Modulus Algorithm
  21 // Schneier, Bruce (1996). Applied Cryptography: Protocols, Algorithms, and Source Code in C,
  22 // Second Edition (2nd ed.). Wiley. ISBN 978-0-471-11709-4, page 244
  23
  24 #include "kernel/log.h"
  25 #include "kernel/rtlil.h"
  26 #include "libs/bigint/BigIntegerLibrary.hh"
  27 #include <assert.h>
  28
  29 static void extend(RTLIL::Const &arg, int width, bool is_signed)
  30 {
  31         RTLIL::State padding = RTLIL::State::S0;
  32
  33         if (arg.bits.size() > 0 && (is_signed || arg.bits.back() > RTLIL::State::S1))
  34                 padding = arg.bits.back();
  35
  36         while (int(arg.bits.size()) < width)
  37                 arg.bits.push_back(padding);
  38 }
  39
  40 static void extend_u0(RTLIL::Const &arg, int width, bool is_signed)
  41 {
  42         RTLIL::State padding = RTLIL::State::S0;
  43
  44         if (arg.bits.size() > 0 && is_signed)
  45                 padding = arg.bits.back();
  46
  47         while (int(arg.bits.size()) < width)
  48                 arg.bits.push_back(padding);
  49 }
  50
  51 static BigInteger const2big(const RTLIL::Const &val, bool as_signed, int &undef_bit_pos)
  52 {
  53         BigInteger result = 0, this_bit = 1;
  54         for (size_t i = 0; i < val.bits.size(); i++) {
  55                 if (val.bits[i] == RTLIL::State::S1) {
  56                         if (as_signed && i+1 == val.bits.size())
  57                                 result -= this_bit;
  58                         else
  59                                 result += this_bit;
  60                 }
  61                 else if (val.bits[i] != RTLIL::State::S0) {
  62                         if (undef_bit_pos < 0)
  63                                 undef_bit_pos = i;
  64                 }
  65                 this_bit *= 2;
  66         }
  67         return result;
  68 }
  69
  70 static RTLIL::Const big2const(const BigInteger &val, int result_len, int undef_bit_pos)
  71 {
  72         BigUnsigned mag = val.getMagnitude();
  73         RTLIL::Const result(0, result_len);
  74
  75         if (!mag.isZero())
  76         {
  77                 if (val.getSign() < 0)
  78                 {
  79                         mag--;
  80                         for (int i = 0; i < result_len; i++)
  81                                 result.bits[i] = mag.getBit(i) ? RTLIL::State::S0 : RTLIL::State::S1;
  82                 }
  83                 else
  84                 {
  85                         for (int i = 0; i < result_len; i++)
  86                                 result.bits[i] = mag.getBit(i) ? RTLIL::State::S1 : RTLIL::State::S0;
  87                 }
  88         }
  89
  90         if (undef_bit_pos >= 0)
  91                 for (int i = undef_bit_pos; i < result_len; i++)
  92                         result.bits[i] = RTLIL::State::Sx;
  93
  94         return result;
  95 }
  96
  97 static RTLIL::State logic_and(RTLIL::State a, RTLIL::State b)
  98 {
  99         if (a == RTLIL::State::S0) return RTLIL::State::S0;
 100         if (b == RTLIL::State::S0) return RTLIL::State::S0;
 101         if (a != RTLIL::State::S1) return RTLIL::State::Sx;
 102         if (b != RTLIL::State::S1) return RTLIL::State::Sx;
 103         return RTLIL::State::S1;
 104 }
 105
 106 static RTLIL::State logic_or(RTLIL::State a, RTLIL::State b)
 107 {
 108         if (a == RTLIL::State::S1) return RTLIL::State::S1;
 109         if (b == RTLIL::State::S1) return RTLIL::State::S1;
 110         if (a != RTLIL::State::S0) return RTLIL::State::Sx;
 111         if (b != RTLIL::State::S0) return RTLIL::State::Sx;
 112         return RTLIL::State::S0;
 113 }
 114
 115 static RTLIL::State logic_xor(RTLIL::State a, RTLIL::State b)
 116 {
 117         if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx;
 118         if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx;
 119         return a != b ? RTLIL::State::S1 : RTLIL::State::S0;
 120 }
 121
 122 static RTLIL::State logic_xnor(RTLIL::State a, RTLIL::State b)
 123 {
 124         if (a != RTLIL::State::S0 && a != RTLIL::State::S1) return RTLIL::State::Sx;
 125         if (b != RTLIL::State::S0 && b != RTLIL::State::S1) return RTLIL::State::Sx;
 126         return a == b ? RTLIL::State::S1 : RTLIL::State::S0;
 127 }
 128
 129 RTLIL::Const RTLIL::const_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 130 {
 131         if (result_len < 0)
 132                 result_len = arg1.bits.size();
 133
 134         RTLIL::Const arg1_ext = arg1;
 135         extend_u0(arg1_ext, result_len, signed1);
 136
 137         RTLIL::Const result(RTLIL::State::Sx, result_len);
 138         for (size_t i = 0; i < size_t(result_len); i++) {
 139                 if (i >= arg1_ext.bits.size())
 140                         result.bits[i] = RTLIL::State::S0;
 141                 else if (arg1_ext.bits[i] == RTLIL::State::S0)
 142                         result.bits[i] = RTLIL::State::S1;
 143                 else if (arg1_ext.bits[i] == RTLIL::State::S1)
 144                         result.bits[i] = RTLIL::State::S0;
 145         }
 146
 147         return result;
 148 }
 149
 150 static RTLIL::Const logic_wrapper(RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State),
 151                 RTLIL::Const arg1, RTLIL::Const arg2, bool signed1, bool signed2, int result_len = -1)
 152 {
 153         if (result_len < 0)
 154                 result_len = std::max(arg1.bits.size(), arg2.bits.size());
 155
 156         extend_u0(arg1, result_len, signed1);
 157         extend_u0(arg2, result_len, signed2);
 158
 159         RTLIL::Const result(RTLIL::State::Sx, result_len);
 160         for (size_t i = 0; i < size_t(result_len); i++) {
 161                 RTLIL::State a = i < arg1.bits.size() ? arg1.bits[i] : RTLIL::State::S0;
 162                 RTLIL::State b = i < arg2.bits.size() ? arg2.bits[i] : RTLIL::State::S0;
 163                 result.bits[i] = logic_func(a, b);
 164         }
 165
 166         return result;
 167 }
 168
 169 RTLIL::Const RTLIL::const_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 170 {
 171         return logic_wrapper(logic_and, arg1, arg2, signed1, signed2, result_len);
 172 }
 173
 174 RTLIL::Const RTLIL::const_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 175 {
 176         return logic_wrapper(logic_or, arg1, arg2, signed1, signed2, result_len);
 177 }
 178
 179 RTLIL::Const RTLIL::const_xor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 180 {
 181         return logic_wrapper(logic_xor, arg1, arg2, signed1, signed2, result_len);
 182 }
 183
 184 RTLIL::Const RTLIL::const_xnor(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 185 {
 186         return logic_wrapper(logic_xnor, arg1, arg2, signed1, signed2, result_len);
 187 }
 188
 189 static RTLIL::Const logic_reduce_wrapper(RTLIL::State initial, RTLIL::State(*logic_func)(RTLIL::State, RTLIL::State), const RTLIL::Const &arg1, int result_len)
 190 {
 191         RTLIL::State temp = initial;
 192
 193         for (size_t i = 0; i < arg1.bits.size(); i++)
 194                 temp = logic_func(temp, arg1.bits[i]);
 195
 196         RTLIL::Const result(temp);
 197         while (int(result.bits.size()) < result_len)
 198                 result.bits.push_back(RTLIL::State::S0);
 199         return result;
 200 }
 201
 202 RTLIL::Const RTLIL::const_reduce_and(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
 203 {
 204         return logic_reduce_wrapper(RTLIL::State::S1, logic_and, arg1, result_len);
 205 }
 206
 207 RTLIL::Const RTLIL::const_reduce_or(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
 208 {
 209         return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1, result_len);
 210 }
 211
 212 RTLIL::Const RTLIL::const_reduce_xor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
 213 {
 214         return logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
 215 }
 216
 217 RTLIL::Const RTLIL::const_reduce_xnor(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
 218 {
 219         RTLIL::Const buffer = logic_reduce_wrapper(RTLIL::State::S0, logic_xor, arg1, result_len);
 220         if (!buffer.bits.empty()) {
 221                 if (buffer.bits.front() == RTLIL::State::S0)
 222                         buffer.bits.front() = RTLIL::State::S1;
 223                 else if (buffer.bits.front() == RTLIL::State::S1)
 224                         buffer.bits.front() = RTLIL::State::S0;
 225         }
 226         return buffer;
 227 }
 228
 229 RTLIL::Const RTLIL::const_reduce_bool(const RTLIL::Const &arg1, const RTLIL::Const&, bool, bool, int result_len)
 230 {
 231         return logic_reduce_wrapper(RTLIL::State::S0, logic_or, arg1, result_len);
 232 }
 233
 234 RTLIL::Const RTLIL::const_logic_not(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 235 {
 236         int undef_bit_pos_a = -1;
 237         BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
 238         RTLIL::Const result(a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S1 : RTLIL::State::S0);
 239
 240         while (int(result.bits.size()) < result_len)
 241                 result.bits.push_back(RTLIL::State::S0);
 242         return result;
 243 }
 244
 245 RTLIL::Const RTLIL::const_logic_and(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 246 {
 247         int undef_bit_pos_a = -1, undef_bit_pos_b = -1;
 248         BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
 249         BigInteger b = const2big(arg2, signed2, undef_bit_pos_b);
 250
 251         RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 252         RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 253         RTLIL::Const result(logic_and(bit_a, bit_b));
 254
 255         while (int(result.bits.size()) < result_len)
 256                 result.bits.push_back(RTLIL::State::S0);
 257         return result;
 258 }
 259
 260 RTLIL::Const RTLIL::const_logic_or(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 261 {
 262         int undef_bit_pos_a = -1, undef_bit_pos_b = -1;
 263         BigInteger a = const2big(arg1, signed1, undef_bit_pos_a);
 264         BigInteger b = const2big(arg2, signed2, undef_bit_pos_b);
 265
 266         RTLIL::State bit_a = a.isZero() ? undef_bit_pos_a >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 267         RTLIL::State bit_b = b.isZero() ? undef_bit_pos_b >= 0 ? RTLIL::State::Sx : RTLIL::State::S0 : RTLIL::State::S1;
 268         RTLIL::Const result(logic_or(bit_a, bit_b));
 269
 270         while (int(result.bits.size()) < result_len)
 271                 result.bits.push_back(RTLIL::State::S0);
 272         return result;
 273 }
 274
 275 static RTLIL::Const const_shift(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool sign_ext, int direction, int result_len)
 276 {
 277         int undef_bit_pos = -1;
 278         BigInteger offset = const2big(arg2, false, undef_bit_pos) * direction;
 279
 280         if (result_len < 0)
 281                 result_len = arg1.bits.size();
 282
 283         RTLIL::Const result(RTLIL::State::Sx, result_len);
 284         if (undef_bit_pos >= 0)
 285                 return result;
 286
 287         for (int i = 0; i < result_len; i++) {
 288                 BigInteger pos = BigInteger(i) + offset;
 289                 if (pos < 0)
 290                         result.bits[i] = RTLIL::State::S0;
 291                 else if (pos >= arg1.bits.size())
 292                         result.bits[i] = sign_ext ? arg1.bits.back() : RTLIL::State::S0;
 293                 else
 294                         result.bits[i] = arg1.bits[pos.toInt()];
 295         }
 296
 297         return result;
 298 }
 299
 300 RTLIL::Const RTLIL::const_shl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
 301 {
 302         RTLIL::Const arg1_ext = arg1;
 303         extend(arg1_ext, result_len, signed1);
 304         return const_shift(arg1_ext, arg2, false, -1, result_len);
 305 }
 306
 307 RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
 308 {
 309         RTLIL::Const arg1_ext = arg1;
 310         extend(arg1_ext, result_len, signed1);
 311         return const_shift(arg1_ext, arg2, false, +1, result_len);
 312 }
 313
 314 RTLIL::Const RTLIL::const_sshl(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 315 {
 316         if (!signed1)
 317                 return const_shl(arg1, arg2, signed1, signed2, result_len);
 318         return const_shift(arg1, arg2, true, -1, result_len);
 319 }
 320
 321 RTLIL::Const RTLIL::const_sshr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 322 {
 323         if (!signed1)
 324                 return const_shr(arg1, arg2, signed1, signed2, result_len);
 325         return const_shift(arg1, arg2, true, +1, result_len);
 326 }
 327
 328 RTLIL::Const RTLIL::const_lt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 329 {
 330         int undef_bit_pos = -1;
 331         bool y = const2big(arg1, signed1, undef_bit_pos) < const2big(arg2, signed2, undef_bit_pos);
 332         RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
 333
 334         while (int(result.bits.size()) < result_len)
 335                 result.bits.push_back(RTLIL::State::S0);
 336         return result;
 337 }
 338
 339 RTLIL::Const RTLIL::const_le(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 340 {
 341         int undef_bit_pos = -1;
 342         bool y = const2big(arg1, signed1, undef_bit_pos) <= const2big(arg2, signed2, undef_bit_pos);
 343         RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
 344
 345         while (int(result.bits.size()) < result_len)
 346                 result.bits.push_back(RTLIL::State::S0);
 347         return result;
 348 }
 349
 350 RTLIL::Const RTLIL::const_eq(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 351 {
 352         RTLIL::Const arg1_ext = arg1;
 353         RTLIL::Const arg2_ext = arg2;
 354         RTLIL::Const result(RTLIL::State::S0, result_len);
 355
 356         int width = std::max(arg1_ext.bits.size(), arg2_ext.bits.size());
 357         extend_u0(arg1_ext, width, signed1 && signed2);
 358         extend_u0(arg2_ext, width, signed1 && signed2);
 359
 360         RTLIL::State matched_status = RTLIL::State::S1;
 361         for (size_t i = 0; i < arg1_ext.bits.size(); i++) {
 362                 if (arg1_ext.bits.at(i) == RTLIL::State::S0 && arg2_ext.bits.at(i) == RTLIL::State::S1)
 363                         return result;
 364                 if (arg1_ext.bits.at(i) == RTLIL::State::S1 && arg2_ext.bits.at(i) == RTLIL::State::S0)
 365                         return result;
 366                 if (arg1_ext.bits.at(i) > RTLIL::State::S1 || arg2_ext.bits.at(i) > RTLIL::State::S1)
 367                         matched_status = RTLIL::State::Sx;
 368         }
 369
 370         result.bits.front() = matched_status;
 371         return result;
 372 }
 373
 374 RTLIL::Const RTLIL::const_ne(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 375 {
 376         RTLIL::Const result = RTLIL::const_eq(arg1, arg2, signed1, signed2, result_len);
 377         if (result.bits.front() == RTLIL::State::S0)
 378                 result.bits.front() = RTLIL::State::S1;
 379         else if (result.bits.front() == RTLIL::State::S1)
 380                 result.bits.front() = RTLIL::State::S0;
 381         return result;
 382 }
 383
 384 RTLIL::Const RTLIL::const_ge(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 385 {
 386         int undef_bit_pos = -1;
 387         bool y = const2big(arg1, signed1, undef_bit_pos) >= const2big(arg2, signed2, undef_bit_pos);
 388         RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
 389
 390         while (int(result.bits.size()) < result_len)
 391                 result.bits.push_back(RTLIL::State::S0);
 392         return result;
 393 }
 394
 395 RTLIL::Const RTLIL::const_gt(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 396 {
 397         int undef_bit_pos = -1;
 398         bool y = const2big(arg1, signed1, undef_bit_pos) > const2big(arg2, signed2, undef_bit_pos);
 399         RTLIL::Const result(undef_bit_pos >= 0 ? RTLIL::State::Sx : y ? RTLIL::State::S1 : RTLIL::State::S0);
 400
 401         while (int(result.bits.size()) < result_len)
 402                 result.bits.push_back(RTLIL::State::S0);
 403         return result;
 404 }
 405
 406 RTLIL::Const RTLIL::const_add(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 407 {
 408         int undef_bit_pos = -1;
 409         BigInteger y = const2big(arg1, signed1, undef_bit_pos) + const2big(arg2, signed2, undef_bit_pos);
 410         return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
 411 }
 412
 413 RTLIL::Const RTLIL::const_sub(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 414 {
 415         int undef_bit_pos = -1;
 416         BigInteger y = const2big(arg1, signed1, undef_bit_pos) - const2big(arg2, signed2, undef_bit_pos);
 417         return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), undef_bit_pos);
 418 }
 419
 420 RTLIL::Const RTLIL::const_mul(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 421 {
 422         int undef_bit_pos = -1;
 423         BigInteger y = const2big(arg1, signed1, undef_bit_pos) * const2big(arg2, signed2, undef_bit_pos);
 424         return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
 425 }
 426
 427 RTLIL::Const RTLIL::const_div(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 428 {
 429         int undef_bit_pos = -1;
 430         BigInteger a = const2big(arg1, signed1, undef_bit_pos);
 431         BigInteger b = const2big(arg2, signed2, undef_bit_pos);
 432         if (b.isZero())
 433                 return RTLIL::Const(RTLIL::State::Sx, result_len);
 434         bool result_neg = (a.getSign() == BigInteger::negative) != (b.getSign() == BigInteger::negative);
 435         a = a.getSign() == BigInteger::negative ? -a : a;
 436         b = b.getSign() == BigInteger::negative ? -b : b;
 437         return big2const(result_neg ? -(a / b) : (a / b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
 438 }
 439
 440 RTLIL::Const RTLIL::const_mod(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 441 {
 442         int undef_bit_pos = -1;
 443         BigInteger a = const2big(arg1, signed1, undef_bit_pos);
 444         BigInteger b = const2big(arg2, signed2, undef_bit_pos);
 445         if (b.isZero())
 446                 return RTLIL::Const(RTLIL::State::Sx, result_len);
 447         bool result_neg = a.getSign() == BigInteger::negative;
 448         a = a.getSign() == BigInteger::negative ? -a : a;
 449         b = b.getSign() == BigInteger::negative ? -b : b;
 450         return big2const(result_neg ? -(a % b) : (a % b), result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
 451 }
 452
 453 RTLIL::Const RTLIL::const_pow(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 454 {
 455         int undef_bit_pos = -1;
 456
 457         log("--POW--\n");
 458         BigInteger a = const2big(arg1, signed1, undef_bit_pos);
 459         BigInteger b = const2big(arg2, signed2, undef_bit_pos);
 460         BigInteger y = 1;
 461
 462         if (a == 0 && b < 0)
 463                 return RTLIL::Const(RTLIL::State::Sx, result_len);
 464
 465         if (a == 0 && b > 0)
 466                 return RTLIL::Const(RTLIL::State::S0, result_len);
 467
 468         if (b < 0)
 469         {
 470                 if (a < -1 || a > 1)
 471                         y = 0;
 472                 if (a == -1)
 473                         y = (-b % 2) == 0 ? 1 : -1;
 474         }
 475
 476         if (b > 0)
 477         {
 478                 // Power-modulo with 2^result_len as modulus
 479                 BigInteger modulus = 1;
 480                 int modulus_bits = (result_len >= 0 ? result_len : 1024);
 481                 for (int i = 0; i < modulus_bits; i++)
 482                         modulus *= 2;
 483
 484                 bool flip_result_sign = false;
 485                 if (a < 0) {
 486                         a *= -1;
 487                         if (b % 2 == 1)
 488                                 flip_result_sign = true;
 489                 }
 490
 491                 while (b > 0) {
 492                         if (b % 2 == 1)
 493                                 y = (y * a) % modulus;
 494                         b = b / 2;
 495                         a = (a * a) % modulus;
 496                 }
 497
 498                 if (flip_result_sign)
 499                         y *= -1;
 500         }
 501
 502         return big2const(y, result_len >= 0 ? result_len : std::max(arg1.bits.size(), arg2.bits.size()), std::min(undef_bit_pos, 0));
 503 }
 504
 505 RTLIL::Const RTLIL::const_pos(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 506 {
 507         RTLIL::Const arg1_ext = arg1;
 508         extend(arg1_ext, result_len, signed1);
 509
 510         return arg1_ext;
 511 }
 512
 513 RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
 514 {
 515         RTLIL::Const arg1_ext = arg1;
 516         extend(arg1_ext, result_len, signed1);
 517
 518         RTLIL::Const zero(RTLIL::State::S0, 1);
 519         return RTLIL::const_sub(zero, arg1_ext, false, signed1, result_len);
 520 }
 521