kernel/cellaigs.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef CELLAIGS_H
  21 #define CELLAIGS_H
  22
  23 #include "kernel/yosys.h"
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 struct AigNode
  28 {
  29         IdString portname;
  30         int portbit;
  31         bool inverter;
  32         int left_parent, right_parent;
  33         vector<pair<IdString, int>> outports;
  34
  35         bool operator==(const AigNode &other) const;
  36         unsigned int hash() const;
  37 };
  38
  39 struct Aig
  40 {
  41         string name;
  42         vector<AigNode> nodes;
  43         Aig(Cell *cell);
  44
  45         bool operator==(const Aig &other) const;
  46         unsigned int hash() const;
  47 };
  48
  49 YOSYS_NAMESPACE_END
  50
  51 #endif