kernel/celledges.h

   1 /* -*- c++ -*-
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef CELLEDGES_H
  21 #define CELLEDGES_H
  22
  23 #include "kernel/yosys.h"
  24 #include "kernel/sigtools.h"
  25
  26 YOSYS_NAMESPACE_BEGIN
  27
  28 struct AbstractCellEdgesDatabase
  29 {
  30         virtual ~AbstractCellEdgesDatabase() { }
  31         virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int delay) = 0;
  32         bool add_edges_from_cell(RTLIL::Cell *cell);
  33 };
  34
  35 struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase
  36 {
  37         SigMap &sigmap;
  38         dict<SigBit, pool<SigBit>> db;
  39         FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
  40
  41         void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
  42                 SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
  43                 SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
  44                 db[from_sigbit].insert(to_sigbit);
  45         }
  46 };
  47
  48 struct RevCellEdgesDatabase : AbstractCellEdgesDatabase
  49 {
  50         SigMap &sigmap;
  51         dict<SigBit, pool<SigBit>> db;
  52         RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { }
  53
  54         void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override {
  55                 SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]);
  56                 SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]);
  57                 db[to_sigbit].insert(from_sigbit);
  58         }
  59 };
  60
  61 YOSYS_NAMESPACE_END
  62
  63 #endif