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Merge pull request #2188 from antmicro/missing-operators
[yosys.git] / kernel / celltypes.h
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 #ifndef CELLTYPES_H
21 #define CELLTYPES_H
22
23 #include "kernel/yosys.h"
24
25 YOSYS_NAMESPACE_BEGIN
26
27 struct CellType
28 {
29 RTLIL::IdString type;
30 pool<RTLIL::IdString> inputs, outputs;
31 bool is_evaluable;
32 };
33
34 struct CellTypes
35 {
36 dict<RTLIL::IdString, CellType> cell_types;
37
38 CellTypes()
39 {
40 }
41
42 CellTypes(RTLIL::Design *design)
43 {
44 setup(design);
45 }
46
47 void setup(RTLIL::Design *design = NULL)
48 {
49 if (design)
50 setup_design(design);
51
52 setup_internals();
53 setup_internals_mem();
54 setup_stdcells();
55 setup_stdcells_mem();
56 }
57
58 void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
59 {
60 CellType ct = {type, inputs, outputs, is_evaluable};
61 cell_types[ct.type] = ct;
62 }
63
64 void setup_module(RTLIL::Module *module)
65 {
66 pool<RTLIL::IdString> inputs, outputs;
67 for (RTLIL::IdString wire_name : module->ports) {
68 RTLIL::Wire *wire = module->wire(wire_name);
69 if (wire->port_input)
70 inputs.insert(wire->name);
71 if (wire->port_output)
72 outputs.insert(wire->name);
73 }
74 setup_type(module->name, inputs, outputs);
75 }
76
77 void setup_design(RTLIL::Design *design)
78 {
79 for (auto module : design->modules())
80 setup_module(module);
81 }
82
83 void setup_internals()
84 {
85 setup_internals_eval();
86
87 setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
88
89 setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
90 setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
91 setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
92 setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
93 setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
94 setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
95 setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
96 setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
97 setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
98 setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
99 setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
100 setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
101 setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
102 setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
103 }
104
105 void setup_internals_eval()
106 {
107 std::vector<RTLIL::IdString> unary_ops = {
108 ID($not), ID($pos), ID($neg),
109 ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
110 ID($logic_not), ID($slice), ID($lut), ID($sop)
111 };
112
113 std::vector<RTLIL::IdString> binary_ops = {
114 ID($and), ID($or), ID($xor), ID($xnor),
115 ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
116 ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
117 ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow),
118 ID($logic_and), ID($logic_or), ID($concat), ID($macc)
119 };
120
121 for (auto type : unary_ops)
122 setup_type(type, {ID::A}, {ID::Y}, true);
123
124 for (auto type : binary_ops)
125 setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
126
127 for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
128 setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
129
130 setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
131 setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
132 setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
133 }
134
135 void setup_internals_ff()
136 {
137 setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
138 setup_type(ID($ff), {ID::D}, {ID::Q});
139 setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
140 setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
141 setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
142 setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::E}, {ID::Q});
143 setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
144 setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::E}, {ID::Q});
145 setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
146 setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
147 setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::E}, {ID::Q});
148 setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
149 setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
150 setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
151 }
152
153 void setup_internals_mem()
154 {
155 setup_internals_ff();
156
157 setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
158 setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
159 setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
160 setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
161
162 setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
163 }
164
165 void setup_stdcells()
166 {
167 setup_stdcells_eval();
168
169 setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
170 }
171
172 void setup_stdcells_eval()
173 {
174 setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
175 setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
176 setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
177 setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
178 setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
179 setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
180 setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
181 setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
182 setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
183 setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
184 setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
185 setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
186 setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
187 setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
188 setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
189 setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
190 setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
191 setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
192 setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
193 }
194
195 void setup_stdcells_mem()
196 {
197 std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
198
199 for (auto c1 : list_np)
200 for (auto c2 : list_np)
201 setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
202
203 setup_type(ID($_FF_), {ID::D}, {ID::Q});
204
205 for (auto c1 : list_np)
206 setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
207
208 for (auto c1 : list_np)
209 for (auto c2 : list_np)
210 setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
211
212 for (auto c1 : list_np)
213 for (auto c2 : list_np)
214 for (auto c3 : list_01)
215 setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
216
217 for (auto c1 : list_np)
218 for (auto c2 : list_np)
219 for (auto c3 : list_01)
220 for (auto c4 : list_np)
221 setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
222
223 for (auto c1 : list_np)
224 for (auto c2 : list_np)
225 for (auto c3 : list_np)
226 setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
227
228 for (auto c1 : list_np)
229 for (auto c2 : list_np)
230 for (auto c3 : list_np)
231 for (auto c4 : list_np)
232 setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
233
234 for (auto c1 : list_np)
235 for (auto c2 : list_np)
236 for (auto c3 : list_01)
237 setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
238
239 for (auto c1 : list_np)
240 for (auto c2 : list_np)
241 for (auto c3 : list_01)
242 for (auto c4 : list_np)
243 setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
244
245 for (auto c1 : list_np)
246 for (auto c2 : list_np)
247 for (auto c3 : list_01)
248 for (auto c4 : list_np)
249 setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
250
251 for (auto c1 : list_np)
252 setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
253
254 for (auto c1 : list_np)
255 for (auto c2 : list_np)
256 for (auto c3 : list_01)
257 setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
258
259 for (auto c1 : list_np)
260 for (auto c2 : list_np)
261 for (auto c3 : list_np)
262 setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
263 }
264
265 void clear()
266 {
267 cell_types.clear();
268 }
269
270 bool cell_known(RTLIL::IdString type) const
271 {
272 return cell_types.count(type) != 0;
273 }
274
275 bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
276 {
277 auto it = cell_types.find(type);
278 return it != cell_types.end() && it->second.outputs.count(port) != 0;
279 }
280
281 bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
282 {
283 auto it = cell_types.find(type);
284 return it != cell_types.end() && it->second.inputs.count(port) != 0;
285 }
286
287 bool cell_evaluable(RTLIL::IdString type) const
288 {
289 auto it = cell_types.find(type);
290 return it != cell_types.end() && it->second.is_evaluable;
291 }
292
293 static RTLIL::Const eval_not(RTLIL::Const v)
294 {
295 for (auto &bit : v.bits)
296 if (bit == State::S0) bit = State::S1;
297 else if (bit == State::S1) bit = State::S0;
298 return v;
299 }
300
301 static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
302 {
303 if (type == ID($sshr) && !signed1)
304 type = ID($shr);
305 if (type == ID($sshl) && !signed1)
306 type = ID($shl);
307
308 if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
309 type != ID($pos) && type != ID($neg) && type != ID($not)) {
310 if (!signed1 || !signed2)
311 signed1 = false, signed2 = false;
312 }
313
314 #define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
315 HANDLE_CELL_TYPE(not)
316 HANDLE_CELL_TYPE(and)
317 HANDLE_CELL_TYPE(or)
318 HANDLE_CELL_TYPE(xor)
319 HANDLE_CELL_TYPE(xnor)
320 HANDLE_CELL_TYPE(reduce_and)
321 HANDLE_CELL_TYPE(reduce_or)
322 HANDLE_CELL_TYPE(reduce_xor)
323 HANDLE_CELL_TYPE(reduce_xnor)
324 HANDLE_CELL_TYPE(reduce_bool)
325 HANDLE_CELL_TYPE(logic_not)
326 HANDLE_CELL_TYPE(logic_and)
327 HANDLE_CELL_TYPE(logic_or)
328 HANDLE_CELL_TYPE(shl)
329 HANDLE_CELL_TYPE(shr)
330 HANDLE_CELL_TYPE(sshl)
331 HANDLE_CELL_TYPE(sshr)
332 HANDLE_CELL_TYPE(shift)
333 HANDLE_CELL_TYPE(shiftx)
334 HANDLE_CELL_TYPE(lt)
335 HANDLE_CELL_TYPE(le)
336 HANDLE_CELL_TYPE(eq)
337 HANDLE_CELL_TYPE(ne)
338 HANDLE_CELL_TYPE(eqx)
339 HANDLE_CELL_TYPE(nex)
340 HANDLE_CELL_TYPE(ge)
341 HANDLE_CELL_TYPE(gt)
342 HANDLE_CELL_TYPE(add)
343 HANDLE_CELL_TYPE(sub)
344 HANDLE_CELL_TYPE(mul)
345 HANDLE_CELL_TYPE(div)
346 HANDLE_CELL_TYPE(mod)
347 HANDLE_CELL_TYPE(divfloor)
348 HANDLE_CELL_TYPE(modfloor)
349 HANDLE_CELL_TYPE(pow)
350 HANDLE_CELL_TYPE(pos)
351 HANDLE_CELL_TYPE(neg)
352 #undef HANDLE_CELL_TYPE
353
354 if (type == ID($_BUF_))
355 return arg1;
356 if (type == ID($_NOT_))
357 return eval_not(arg1);
358 if (type == ID($_AND_))
359 return const_and(arg1, arg2, false, false, 1);
360 if (type == ID($_NAND_))
361 return eval_not(const_and(arg1, arg2, false, false, 1));
362 if (type == ID($_OR_))
363 return const_or(arg1, arg2, false, false, 1);
364 if (type == ID($_NOR_))
365 return eval_not(const_or(arg1, arg2, false, false, 1));
366 if (type == ID($_XOR_))
367 return const_xor(arg1, arg2, false, false, 1);
368 if (type == ID($_XNOR_))
369 return const_xnor(arg1, arg2, false, false, 1);
370 if (type == ID($_ANDNOT_))
371 return const_and(arg1, eval_not(arg2), false, false, 1);
372 if (type == ID($_ORNOT_))
373 return const_or(arg1, eval_not(arg2), false, false, 1);
374
375 if (errp != nullptr) {
376 *errp = true;
377 return State::Sm;
378 }
379
380 log_abort();
381 }
382
383 static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
384 {
385 if (cell->type == ID($slice)) {
386 RTLIL::Const ret;
387 int width = cell->parameters.at(ID::Y_WIDTH).as_int();
388 int offset = cell->parameters.at(ID::OFFSET).as_int();
389 ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
390 return ret;
391 }
392
393 if (cell->type == ID($concat)) {
394 RTLIL::Const ret = arg1;
395 ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
396 return ret;
397 }
398
399 if (cell->type == ID($lut))
400 {
401 int width = cell->parameters.at(ID::WIDTH).as_int();
402
403 std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
404 while (GetSize(t) < (1 << width))
405 t.push_back(State::S0);
406 t.resize(1 << width);
407
408 for (int i = width-1; i >= 0; i--) {
409 RTLIL::State sel = arg1.bits.at(i);
410 std::vector<RTLIL::State> new_t;
411 if (sel == State::S0)
412 new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
413 else if (sel == State::S1)
414 new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
415 else
416 for (int j = 0; j < GetSize(t)/2; j++)
417 new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
418 t.swap(new_t);
419 }
420
421 log_assert(GetSize(t) == 1);
422 return t;
423 }
424
425 if (cell->type == ID($sop))
426 {
427 int width = cell->parameters.at(ID::WIDTH).as_int();
428 int depth = cell->parameters.at(ID::DEPTH).as_int();
429 std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
430
431 while (GetSize(t) < width*depth*2)
432 t.push_back(State::S0);
433
434 RTLIL::State default_ret = State::S0;
435
436 for (int i = 0; i < depth; i++)
437 {
438 bool match = true;
439 bool match_x = true;
440
441 for (int j = 0; j < width; j++) {
442 RTLIL::State a = arg1.bits.at(j);
443 if (t.at(2*width*i + 2*j + 0) == State::S1) {
444 if (a == State::S1) match_x = false;
445 if (a != State::S0) match = false;
446 }
447 if (t.at(2*width*i + 2*j + 1) == State::S1) {
448 if (a == State::S0) match_x = false;
449 if (a != State::S1) match = false;
450 }
451 }
452
453 if (match)
454 return State::S1;
455
456 if (match_x)
457 default_ret = State::Sx;
458 }
459
460 return default_ret;
461 }
462
463 bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
464 bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
465 int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
466 return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
467 }
468
469 static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
470 {
471 if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
472 RTLIL::Const ret = arg1;
473 for (size_t i = 0; i < arg3.bits.size(); i++)
474 if (arg3.bits[i] == RTLIL::State::S1) {
475 std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
476 ret = RTLIL::Const(bits);
477 }
478 return ret;
479 }
480
481 if (cell->type == ID($_AOI3_))
482 return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
483 if (cell->type == ID($_OAI3_))
484 return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
485
486 log_assert(arg3.bits.size() == 0);
487 return eval(cell, arg1, arg2, errp);
488 }
489
490 static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
491 {
492 if (cell->type == ID($_AOI4_))
493 return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
494 if (cell->type == ID($_OAI4_))
495 return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
496
497 log_assert(arg4.bits.size() == 0);
498 return eval(cell, arg1, arg2, arg3, errp);
499 }
500 };
501
502 // initialized by yosys_setup()
503 extern CellTypes yosys_celltypes;
504
505 YOSYS_NAMESPACE_END
506
507 #endif