kernel/celltypes.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef CELLTYPES_H
  21 #define CELLTYPES_H
  22
  23 #include "kernel/yosys.h"
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 struct CellType
  28 {
  29         RTLIL::IdString type;
  30         pool<RTLIL::IdString> inputs, outputs;
  31         bool is_evaluable;
  32 };
  33
  34 struct CellTypes
  35 {
  36         dict<RTLIL::IdString, CellType> cell_types;
  37
  38         CellTypes()
  39         {
  40         }
  41
  42         CellTypes(RTLIL::Design *design)
  43         {
  44                 setup(design);
  45         }
  46
  47         void setup(RTLIL::Design *design = NULL)
  48         {
  49                 if (design)
  50                         setup_design(design);
  51
  52                 setup_internals();
  53                 setup_internals_mem();
  54                 setup_stdcells();
  55                 setup_stdcells_mem();
  56         }
  57
  58         void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
  59         {
  60                 CellType ct = {type, inputs, outputs, is_evaluable};
  61                 cell_types[ct.type] = ct;
  62         }
  63
  64         void setup_module(RTLIL::Module *module)
  65         {
  66                 pool<RTLIL::IdString> inputs, outputs;
  67                 for (RTLIL::IdString wire_name : module->ports) {
  68                         RTLIL::Wire *wire = module->wire(wire_name);
  69                         if (wire->port_input)
  70                                 inputs.insert(wire->name);
  71                         if (wire->port_output)
  72                                 outputs.insert(wire->name);
  73                 }
  74                 setup_type(module->name, inputs, outputs);
  75         }
  76
  77         void setup_design(RTLIL::Design *design)
  78         {
  79                 for (auto module : design->modules())
  80                         setup_module(module);
  81         }
  82
  83         void setup_internals()
  84         {
  85                 setup_internals_eval();
  86
  87                 setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y}, true);
  88
  89                 setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
  90                 setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
  91                 setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
  92                 setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
  93                 setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>(), true);
  94                 setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y}, true);
  95                 setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y}, true);
  96                 setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y}, true);
  97                 setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y}, true);
  98                 setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y}, true);
  99                 setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y}, true);
 100                 setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
 101                 setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>(), true);
 102                 setup_type(ID($specrule), {ID::EN_SRC, ID::EN_DST, ID::SRC, ID::DST}, pool<RTLIL::IdString>(), true);
 103         }
 104
 105         void setup_internals_eval()
 106         {
 107                 std::vector<RTLIL::IdString> unary_ops = {
 108                         ID($not), ID($pos), ID($neg),
 109                         ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
 110                         ID($logic_not), ID($slice), ID($lut), ID($sop)
 111                 };
 112
 113                 std::vector<RTLIL::IdString> binary_ops = {
 114                         ID($and), ID($or), ID($xor), ID($xnor),
 115                         ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx),
 116                         ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
 117                         ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow),
 118                         ID($logic_and), ID($logic_or), ID($concat), ID($macc)
 119                 };
 120
 121                 for (auto type : unary_ops)
 122                         setup_type(type, {ID::A}, {ID::Y}, true);
 123
 124                 for (auto type : binary_ops)
 125                         setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
 126
 127                 for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux)}))
 128                         setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
 129
 130                 setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
 131                 setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
 132                 setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
 133         }
 134
 135         void setup_internals_ff()
 136         {
 137                 setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
 138                 setup_type(ID($ff), {ID::D}, {ID::Q});
 139                 setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
 140                 setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
 141                 setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
 142                 setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
 143                 setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
 144                 setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
 145         }
 146
 147         void setup_internals_mem()
 148         {
 149                 setup_internals_ff();
 150
 151                 setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
 152                 setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
 153                 setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
 154                 setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
 155
 156                 setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
 157         }
 158
 159         void setup_stdcells()
 160         {
 161                 setup_stdcells_eval();
 162
 163                 setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y}, true);
 164         }
 165
 166         void setup_stdcells_eval()
 167         {
 168                 setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
 169                 setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
 170                 setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
 171                 setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
 172                 setup_type(ID($_OR_),  {ID::A, ID::B}, {ID::Y}, true);
 173                 setup_type(ID($_NOR_),  {ID::A, ID::B}, {ID::Y}, true);
 174                 setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
 175                 setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
 176                 setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
 177                 setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
 178                 setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
 179                 setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
 180                 setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
 181                 setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
 182                 setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
 183                 setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
 184                 setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
 185                 setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
 186                 setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
 187         }
 188
 189         void setup_stdcells_mem()
 190         {
 191                 std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
 192
 193                 for (auto c1 : list_np)
 194                 for (auto c2 : list_np)
 195                         setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
 196
 197                 setup_type(ID($_FF_), {ID::D}, {ID::Q});
 198
 199                 for (auto c1 : list_np)
 200                         setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
 201
 202                 for (auto c1 : list_np)
 203                 for (auto c2 : list_np)
 204                         setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
 205
 206                 for (auto c1 : list_np)
 207                 for (auto c2 : list_np)
 208                 for (auto c3 : list_01)
 209                         setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
 210
 211                 for (auto c1 : list_np)
 212                 for (auto c2 : list_np)
 213                 for (auto c3 : list_np)
 214                         setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
 215
 216                 for (auto c1 : list_np)
 217                         setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
 218
 219                 for (auto c1 : list_np)
 220                 for (auto c2 : list_np)
 221                 for (auto c3 : list_np)
 222                         setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
 223         }
 224
 225         void clear()
 226         {
 227                 cell_types.clear();
 228         }
 229
 230         bool cell_known(RTLIL::IdString type) const
 231         {
 232                 return cell_types.count(type) != 0;
 233         }
 234
 235         bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
 236         {
 237                 auto it = cell_types.find(type);
 238                 return it != cell_types.end() && it->second.outputs.count(port) != 0;
 239         }
 240
 241         bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
 242         {
 243                 auto it = cell_types.find(type);
 244                 return it != cell_types.end() && it->second.inputs.count(port) != 0;
 245         }
 246
 247         bool cell_evaluable(RTLIL::IdString type) const
 248         {
 249                 auto it = cell_types.find(type);
 250                 return it != cell_types.end() && it->second.is_evaluable;
 251         }
 252
 253         static RTLIL::Const eval_not(RTLIL::Const v)
 254         {
 255                 for (auto &bit : v.bits)
 256                         if (bit == State::S0) bit = State::S1;
 257                         else if (bit == State::S1) bit = State::S0;
 258                 return v;
 259         }
 260
 261         static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len, bool *errp = nullptr)
 262         {
 263                 if (type == ID($sshr) && !signed1)
 264                         type = ID($shr);
 265                 if (type == ID($sshl) && !signed1)
 266                         type = ID($shl);
 267
 268                 if (type != ID($sshr) && type != ID($sshl) && type != ID($shr) && type != ID($shl) && type != ID($shift) && type != ID($shiftx) &&
 269                                 type != ID($pos) && type != ID($neg) && type != ID($not)) {
 270                         if (!signed1 || !signed2)
 271                                 signed1 = false, signed2 = false;
 272                 }
 273
 274 #define HANDLE_CELL_TYPE(_t) if (type == ID($##_t)) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
 275                 HANDLE_CELL_TYPE(not)
 276                 HANDLE_CELL_TYPE(and)
 277                 HANDLE_CELL_TYPE(or)
 278                 HANDLE_CELL_TYPE(xor)
 279                 HANDLE_CELL_TYPE(xnor)
 280                 HANDLE_CELL_TYPE(reduce_and)
 281                 HANDLE_CELL_TYPE(reduce_or)
 282                 HANDLE_CELL_TYPE(reduce_xor)
 283                 HANDLE_CELL_TYPE(reduce_xnor)
 284                 HANDLE_CELL_TYPE(reduce_bool)
 285                 HANDLE_CELL_TYPE(logic_not)
 286                 HANDLE_CELL_TYPE(logic_and)
 287                 HANDLE_CELL_TYPE(logic_or)
 288                 HANDLE_CELL_TYPE(shl)
 289                 HANDLE_CELL_TYPE(shr)
 290                 HANDLE_CELL_TYPE(sshl)
 291                 HANDLE_CELL_TYPE(sshr)
 292                 HANDLE_CELL_TYPE(shift)
 293                 HANDLE_CELL_TYPE(shiftx)
 294                 HANDLE_CELL_TYPE(lt)
 295                 HANDLE_CELL_TYPE(le)
 296                 HANDLE_CELL_TYPE(eq)
 297                 HANDLE_CELL_TYPE(ne)
 298                 HANDLE_CELL_TYPE(eqx)
 299                 HANDLE_CELL_TYPE(nex)
 300                 HANDLE_CELL_TYPE(ge)
 301                 HANDLE_CELL_TYPE(gt)
 302                 HANDLE_CELL_TYPE(add)
 303                 HANDLE_CELL_TYPE(sub)
 304                 HANDLE_CELL_TYPE(mul)
 305                 HANDLE_CELL_TYPE(div)
 306                 HANDLE_CELL_TYPE(mod)
 307                 HANDLE_CELL_TYPE(pow)
 308                 HANDLE_CELL_TYPE(pos)
 309                 HANDLE_CELL_TYPE(neg)
 310 #undef HANDLE_CELL_TYPE
 311
 312                 if (type == ID($_BUF_))
 313                         return arg1;
 314                 if (type == ID($_NOT_))
 315                         return eval_not(arg1);
 316                 if (type == ID($_AND_))
 317                         return const_and(arg1, arg2, false, false, 1);
 318                 if (type == ID($_NAND_))
 319                         return eval_not(const_and(arg1, arg2, false, false, 1));
 320                 if (type == ID($_OR_))
 321                         return const_or(arg1, arg2, false, false, 1);
 322                 if (type == ID($_NOR_))
 323                         return eval_not(const_or(arg1, arg2, false, false, 1));
 324                 if (type == ID($_XOR_))
 325                         return const_xor(arg1, arg2, false, false, 1);
 326                 if (type == ID($_XNOR_))
 327                         return const_xnor(arg1, arg2, false, false, 1);
 328                 if (type == ID($_ANDNOT_))
 329                         return const_and(arg1, eval_not(arg2), false, false, 1);
 330                 if (type == ID($_ORNOT_))
 331                         return const_or(arg1, eval_not(arg2), false, false, 1);
 332
 333                 if (errp != nullptr) {
 334                         *errp = true;
 335                         return State::Sm;
 336                 }
 337
 338                 log_abort();
 339         }
 340
 341         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool *errp = nullptr)
 342         {
 343                 if (cell->type == ID($slice)) {
 344                         RTLIL::Const ret;
 345                         int width = cell->parameters.at(ID::Y_WIDTH).as_int();
 346                         int offset = cell->parameters.at(ID::OFFSET).as_int();
 347                         ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
 348                         return ret;
 349                 }
 350
 351                 if (cell->type == ID($concat)) {
 352                         RTLIL::Const ret = arg1;
 353                         ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
 354                         return ret;
 355                 }
 356
 357                 if (cell->type == ID($lut))
 358                 {
 359                         int width = cell->parameters.at(ID::WIDTH).as_int();
 360
 361                         std::vector<RTLIL::State> t = cell->parameters.at(ID::LUT).bits;
 362                         while (GetSize(t) < (1 << width))
 363                                 t.push_back(State::S0);
 364                         t.resize(1 << width);
 365
 366                         for (int i = width-1; i >= 0; i--) {
 367                                 RTLIL::State sel = arg1.bits.at(i);
 368                                 std::vector<RTLIL::State> new_t;
 369                                 if (sel == State::S0)
 370                                         new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
 371                                 else if (sel == State::S1)
 372                                         new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
 373                                 else
 374                                         for (int j = 0; j < GetSize(t)/2; j++)
 375                                                 new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
 376                                 t.swap(new_t);
 377                         }
 378
 379                         log_assert(GetSize(t) == 1);
 380                         return t;
 381                 }
 382
 383                 if (cell->type == ID($sop))
 384                 {
 385                         int width = cell->parameters.at(ID::WIDTH).as_int();
 386                         int depth = cell->parameters.at(ID::DEPTH).as_int();
 387                         std::vector<RTLIL::State> t = cell->parameters.at(ID::TABLE).bits;
 388
 389                         while (GetSize(t) < width*depth*2)
 390                                 t.push_back(State::S0);
 391
 392                         RTLIL::State default_ret = State::S0;
 393
 394                         for (int i = 0; i < depth; i++)
 395                         {
 396                                 bool match = true;
 397                                 bool match_x = true;
 398
 399                                 for (int j = 0; j < width; j++) {
 400                                         RTLIL::State a = arg1.bits.at(j);
 401                                         if (t.at(2*width*i + 2*j + 0) == State::S1) {
 402                                                 if (a == State::S1) match_x = false;
 403                                                 if (a != State::S0) match = false;
 404                                         }
 405                                         if (t.at(2*width*i + 2*j + 1) == State::S1) {
 406                                                 if (a == State::S0) match_x = false;
 407                                                 if (a != State::S1) match = false;
 408                                         }
 409                                 }
 410
 411                                 if (match)
 412                                         return State::S1;
 413
 414                                 if (match_x)
 415                                         default_ret = State::Sx;
 416                         }
 417
 418                         return default_ret;
 419                 }
 420
 421                 bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
 422                 bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
 423                 int result_len = cell->parameters.count(ID::Y_WIDTH) > 0 ? cell->parameters[ID::Y_WIDTH].as_int() : -1;
 424                 return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len, errp);
 425         }
 426
 427         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, bool *errp = nullptr)
 428         {
 429                 if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
 430                         RTLIL::Const ret = arg1;
 431                         for (size_t i = 0; i < arg3.bits.size(); i++)
 432                                 if (arg3.bits[i] == RTLIL::State::S1) {
 433                                         std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
 434                                         ret = RTLIL::Const(bits);
 435                                 }
 436                         return ret;
 437                 }
 438
 439                 if (cell->type == ID($_AOI3_))
 440                         return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
 441                 if (cell->type == ID($_OAI3_))
 442                         return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 443
 444                 log_assert(arg3.bits.size() == 0);
 445                 return eval(cell, arg1, arg2, errp);
 446         }
 447
 448         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4, bool *errp = nullptr)
 449         {
 450                 if (cell->type == ID($_AOI4_))
 451                         return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 452                 if (cell->type == ID($_OAI4_))
 453                         return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
 454
 455                 log_assert(arg4.bits.size() == 0);
 456                 return eval(cell, arg1, arg2, arg3, errp);
 457         }
 458 };
 459
 460 // initialized by yosys_setup()
 461 extern CellTypes yosys_celltypes;
 462
 463 YOSYS_NAMESPACE_END
 464
 465 #endif