kernel/celltypes.h

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #ifndef CELLTYPES_H
  21 #define CELLTYPES_H
  22
  23 #include <kernel/yosys.h>
  24
  25 YOSYS_NAMESPACE_BEGIN
  26
  27 struct CellType
  28 {
  29         RTLIL::IdString type;
  30         pool<RTLIL::IdString> inputs, outputs;
  31         bool is_evaluable;
  32 };
  33
  34 struct CellTypes
  35 {
  36         dict<RTLIL::IdString, CellType> cell_types;
  37
  38         CellTypes()
  39         {
  40         }
  41
  42         CellTypes(RTLIL::Design *design)
  43         {
  44                 setup(design);
  45         }
  46
  47         void setup(RTLIL::Design *design = NULL)
  48         {
  49                 if (design)
  50                         setup_design(design);
  51
  52                 setup_internals();
  53                 setup_internals_mem();
  54                 setup_stdcells();
  55                 setup_stdcells_mem();
  56         }
  57
  58         void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false)
  59         {
  60                 CellType ct = {type, inputs, outputs, is_evaluable};
  61                 cell_types[ct.type] = ct;
  62         }
  63
  64         void setup_module(RTLIL::Module *module)
  65         {
  66                 pool<RTLIL::IdString> inputs, outputs;
  67                 for (RTLIL::IdString wire_name : module->ports) {
  68                         RTLIL::Wire *wire = module->wire(wire_name);
  69                         if (wire->port_input)
  70                                 inputs.insert(wire->name);
  71                         if (wire->port_output)
  72                                 outputs.insert(wire->name);
  73                 }
  74                 setup_type(module->name, inputs, outputs);
  75         }
  76
  77         void setup_design(RTLIL::Design *design)
  78         {
  79                 for (auto module : design->modules())
  80                         setup_module(module);
  81         }
  82
  83         void setup_internals()
  84         {
  85                 std::vector<RTLIL::IdString> unary_ops = {
  86                         "$not", "$pos", "$neg",
  87                         "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
  88                         "$logic_not", "$slice", "$lut", "$sop"
  89                 };
  90
  91                 std::vector<RTLIL::IdString> binary_ops = {
  92                         "$and", "$or", "$xor", "$xnor",
  93                         "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
  94                         "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
  95                         "$add", "$sub", "$mul", "$div", "$mod", "$pow",
  96                         "$logic_and", "$logic_or", "$concat", "$macc"
  97                 };
  98                 IdString A = "\\A", B = "\\B", S = "\\S", Y = "\\Y";
  99                 IdString P = "\\P", G = "\\G", C = "\\C", X = "\\X";
 100                 IdString BI = "\\BI", CI = "\\CI", CO = "\\CO", EN = "\\EN";
 101
 102                 for (auto type : unary_ops)
 103                         setup_type(type, {A}, {Y}, true);
 104
 105                 for (auto type : binary_ops)
 106                         setup_type(type, {A, B}, {Y}, true);
 107
 108                 for (auto type : std::vector<RTLIL::IdString>({"$mux", "$pmux"}))
 109                         setup_type(type, {A, B, S}, {Y}, true);
 110
 111                 setup_type("$lcu", {P, G, CI}, {CO}, true);
 112                 setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
 113                 setup_type("$fa", {A, B, C}, {X, Y}, true);
 114
 115                 setup_type("$tribuf", {A, EN}, {Y}, true);
 116
 117                 setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
 118                 setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
 119                 setup_type("$predict", {A, EN}, pool<RTLIL::IdString>(), true);
 120                 setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
 121                 setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
 122                 setup_type("$aconst", pool<RTLIL::IdString>(), {Y}, true);
 123                 setup_type("$equiv", {A, B}, {Y}, true);
 124         }
 125
 126         void setup_internals_mem()
 127         {
 128                 IdString SET = "\\SET", CLR = "\\CLR", CLK = "\\CLK", ARST = "\\ARST", EN = "\\EN";
 129                 IdString Q = "\\Q", D = "\\D", ADDR = "\\ADDR", DATA = "\\DATA", RD_EN = "\\RD_EN";
 130                 IdString RD_CLK = "\\RD_CLK", RD_ADDR = "\\RD_ADDR", WR_CLK = "\\WR_CLK", WR_EN = "\\WR_EN";
 131                 IdString WR_ADDR = "\\WR_ADDR", WR_DATA = "\\WR_DATA", RD_DATA = "\\RD_DATA";
 132                 IdString CTRL_IN = "\\CTRL_IN", CTRL_OUT = "\\CTRL_OUT";
 133
 134                 setup_type("$sr", {SET, CLR}, {Q});
 135                 setup_type("$dff", {CLK, D}, {Q});
 136                 setup_type("$dffe", {CLK, EN, D}, {Q});
 137                 setup_type("$dffsr", {CLK, SET, CLR, D}, {Q});
 138                 setup_type("$adff", {CLK, ARST, D}, {Q});
 139                 setup_type("$dlatch", {EN, D}, {Q});
 140                 setup_type("$dlatchsr", {EN, SET, CLR, D}, {Q});
 141
 142                 setup_type("$memrd", {CLK, EN, ADDR}, {DATA});
 143                 setup_type("$memwr", {CLK, EN, ADDR, DATA}, pool<RTLIL::IdString>());
 144                 setup_type("$meminit", {ADDR, DATA}, pool<RTLIL::IdString>());
 145                 setup_type("$mem", {RD_CLK, RD_EN, RD_ADDR, WR_CLK, WR_EN, WR_ADDR, WR_DATA}, {RD_DATA});
 146
 147                 setup_type("$fsm", {CLK, ARST, CTRL_IN}, {CTRL_OUT});
 148         }
 149
 150         void setup_stdcells()
 151         {
 152                 IdString A = "\\A", B = "\\B", C = "\\C", D = "\\D";
 153                 IdString E = "\\E", F = "\\F", G = "\\G", H = "\\H";
 154                 IdString I = "\\I", J = "\\J", K = "\\K", L = "\\L";
 155                 IdString M = "\\I", N = "\\N", O = "\\O", P = "\\P";
 156                 IdString S = "\\S", T = "\\T", U = "\\U", V = "\\V";
 157                 IdString Y = "\\Y";
 158
 159                 setup_type("$_BUF_", {A}, {Y}, true);
 160                 setup_type("$_NOT_", {A}, {Y}, true);
 161                 setup_type("$_AND_", {A, B}, {Y}, true);
 162                 setup_type("$_NAND_", {A, B}, {Y}, true);
 163                 setup_type("$_OR_",  {A, B}, {Y}, true);
 164                 setup_type("$_NOR_",  {A, B}, {Y}, true);
 165                 setup_type("$_XOR_", {A, B}, {Y}, true);
 166                 setup_type("$_XNOR_", {A, B}, {Y}, true);
 167                 setup_type("$_MUX_", {A, B, S}, {Y}, true);
 168                 setup_type("$_MUX4_", {A, B, C, D, S, T}, {Y}, true);
 169                 setup_type("$_MUX8_", {A, B, C, D, E, F, G, H, S, T, U}, {Y}, true);
 170                 setup_type("$_MUX16_", {A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, S, T, U, V}, {Y}, true);
 171                 setup_type("$_AOI3_", {A, B, C}, {Y}, true);
 172                 setup_type("$_OAI3_", {A, B, C}, {Y}, true);
 173                 setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
 174                 setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
 175                 setup_type("$_TBUF_", {A, E}, {Y}, true);
 176         }
 177
 178         void setup_stdcells_mem()
 179         {
 180                 IdString S = "\\S", R = "\\R", C = "\\C";
 181                 IdString D = "\\D", Q = "\\Q", E = "\\E";
 182
 183                 std::vector<char> list_np = {'N', 'P'}, list_01 = {'0', '1'};
 184
 185                 for (auto c1 : list_np)
 186                 for (auto c2 : list_np)
 187                         setup_type(stringf("$_SR_%c%c_", c1, c2), {S, R}, {Q});
 188
 189                 for (auto c1 : list_np)
 190                         setup_type(stringf("$_DFF_%c_", c1), {C, D}, {Q});
 191
 192                 for (auto c1 : list_np)
 193                 for (auto c2 : list_np)
 194                         setup_type(stringf("$_DFFE_%c%c_", c1, c2), {C, D, E}, {Q});
 195
 196                 for (auto c1 : list_np)
 197                 for (auto c2 : list_np)
 198                 for (auto c3 : list_01)
 199                         setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {C, R, D}, {Q});
 200
 201                 for (auto c1 : list_np)
 202                 for (auto c2 : list_np)
 203                 for (auto c3 : list_np)
 204                         setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {C, S, R, D}, {Q});
 205
 206                 for (auto c1 : list_np)
 207                         setup_type(stringf("$_DLATCH_%c_", c1), {E, D}, {Q});
 208
 209                 for (auto c1 : list_np)
 210                 for (auto c2 : list_np)
 211                 for (auto c3 : list_np)
 212                         setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {E, S, R, D}, {Q});
 213         }
 214
 215         void clear()
 216         {
 217                 cell_types.clear();
 218         }
 219
 220         bool cell_known(RTLIL::IdString type)
 221         {
 222                 return cell_types.count(type) != 0;
 223         }
 224
 225         bool cell_output(RTLIL::IdString type, RTLIL::IdString port)
 226         {
 227                 auto it = cell_types.find(type);
 228                 return it != cell_types.end() && it->second.outputs.count(port) != 0;
 229         }
 230
 231         bool cell_input(RTLIL::IdString type, RTLIL::IdString port)
 232         {
 233                 auto it = cell_types.find(type);
 234                 return it != cell_types.end() && it->second.inputs.count(port) != 0;
 235         }
 236
 237         bool cell_evaluable(RTLIL::IdString type)
 238         {
 239                 auto it = cell_types.find(type);
 240                 return it != cell_types.end() && it->second.is_evaluable;
 241         }
 242
 243         static RTLIL::Const eval_not(RTLIL::Const v)
 244         {
 245                 for (auto &bit : v.bits)
 246                         if (bit == RTLIL::S0) bit = RTLIL::S1;
 247                         else if (bit == RTLIL::S1) bit = RTLIL::S0;
 248                 return v;
 249         }
 250
 251         static RTLIL::Const eval(RTLIL::IdString type, const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool signed2, int result_len)
 252         {
 253                 if (type == "$sshr" && !signed1)
 254                         type = "$shr";
 255                 if (type == "$sshl" && !signed1)
 256                         type = "$shl";
 257
 258                 if (type != "$sshr" && type != "$sshl" && type != "$shr" && type != "$shl" && type != "$shift" && type != "$shiftx" &&
 259                                 type != "$pos" && type != "$neg" && type != "$not") {
 260                         if (!signed1 || !signed2)
 261                                 signed1 = false, signed2 = false;
 262                 }
 263
 264 #define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
 265                 HANDLE_CELL_TYPE(not)
 266                 HANDLE_CELL_TYPE(and)
 267                 HANDLE_CELL_TYPE(or)
 268                 HANDLE_CELL_TYPE(xor)
 269                 HANDLE_CELL_TYPE(xnor)
 270                 HANDLE_CELL_TYPE(reduce_and)
 271                 HANDLE_CELL_TYPE(reduce_or)
 272                 HANDLE_CELL_TYPE(reduce_xor)
 273                 HANDLE_CELL_TYPE(reduce_xnor)
 274                 HANDLE_CELL_TYPE(reduce_bool)
 275                 HANDLE_CELL_TYPE(logic_not)
 276                 HANDLE_CELL_TYPE(logic_and)
 277                 HANDLE_CELL_TYPE(logic_or)
 278                 HANDLE_CELL_TYPE(shl)
 279                 HANDLE_CELL_TYPE(shr)
 280                 HANDLE_CELL_TYPE(sshl)
 281                 HANDLE_CELL_TYPE(sshr)
 282                 HANDLE_CELL_TYPE(shift)
 283                 HANDLE_CELL_TYPE(shiftx)
 284                 HANDLE_CELL_TYPE(lt)
 285                 HANDLE_CELL_TYPE(le)
 286                 HANDLE_CELL_TYPE(eq)
 287                 HANDLE_CELL_TYPE(ne)
 288                 HANDLE_CELL_TYPE(eqx)
 289                 HANDLE_CELL_TYPE(nex)
 290                 HANDLE_CELL_TYPE(ge)
 291                 HANDLE_CELL_TYPE(gt)
 292                 HANDLE_CELL_TYPE(add)
 293                 HANDLE_CELL_TYPE(sub)
 294                 HANDLE_CELL_TYPE(mul)
 295                 HANDLE_CELL_TYPE(div)
 296                 HANDLE_CELL_TYPE(mod)
 297                 HANDLE_CELL_TYPE(pow)
 298                 HANDLE_CELL_TYPE(pos)
 299                 HANDLE_CELL_TYPE(neg)
 300 #undef HANDLE_CELL_TYPE
 301
 302                 if (type == "$_BUF_")
 303                         return arg1;
 304                 if (type == "$_NOT_")
 305                         return eval_not(arg1);
 306                 if (type == "$_AND_")
 307                         return const_and(arg1, arg2, false, false, 1);
 308                 if (type == "$_NAND_")
 309                         return eval_not(const_and(arg1, arg2, false, false, 1));
 310                 if (type == "$_OR_")
 311                         return const_or(arg1, arg2, false, false, 1);
 312                 if (type == "$_NOR_")
 313                         return eval_not(const_and(arg1, arg2, false, false, 1));
 314                 if (type == "$_XOR_")
 315                         return const_xor(arg1, arg2, false, false, 1);
 316                 if (type == "$_XNOR_")
 317                         return const_xnor(arg1, arg2, false, false, 1);
 318
 319                 log_abort();
 320         }
 321
 322         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
 323         {
 324                 if (cell->type == "$slice") {
 325                         RTLIL::Const ret;
 326                         int width = cell->parameters.at("\\Y_WIDTH").as_int();
 327                         int offset = cell->parameters.at("\\OFFSET").as_int();
 328                         ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
 329                         return ret;
 330                 }
 331
 332                 if (cell->type == "$concat") {
 333                         RTLIL::Const ret = arg1;
 334                         ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
 335                         return ret;
 336                 }
 337
 338                 if (cell->type == "$lut")
 339                 {
 340                         int width = cell->parameters.at("\\WIDTH").as_int();
 341
 342                         std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
 343                         while (GetSize(t) < (1 << width))
 344                                 t.push_back(RTLIL::S0);
 345                         t.resize(1 << width);
 346
 347                         for (int i = width-1; i >= 0; i--) {
 348                                 RTLIL::State sel = arg1.bits.at(i);
 349                                 std::vector<RTLIL::State> new_t;
 350                                 if (sel == RTLIL::S0)
 351                                         new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
 352                                 else if (sel == RTLIL::S1)
 353                                         new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
 354                                 else
 355                                         for (int j = 0; j < GetSize(t)/2; j++)
 356                                                 new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
 357                                 t.swap(new_t);
 358                         }
 359
 360                         log_assert(GetSize(t) == 1);
 361                         return t;
 362                 }
 363
 364                 if (cell->type == "$sop")
 365                 {
 366                         int width = cell->parameters.at("\\WIDTH").as_int();
 367                         int depth = cell->parameters.at("\\DEPTH").as_int();
 368                         std::vector<RTLIL::State> t = cell->parameters.at("\\TABLE").bits;
 369
 370                         while (GetSize(t) < width*depth*2)
 371                                 t.push_back(RTLIL::S0);
 372
 373                         RTLIL::State default_ret = State::S0;
 374
 375                         for (int i = 0; i < depth; i++)
 376                         {
 377                                 bool match = true;
 378                                 bool match_x = true;
 379
 380                                 for (int j = 0; j < width; j++) {
 381                                         RTLIL::State a = arg1.bits.at(j);
 382                                         if (t.at(2*width*i + 2*j + 0) == State::S1) {
 383                                                 if (a == State::S1) match_x = false;
 384                                                 if (a != State::S0) match = false;
 385                                         }
 386                                         if (t.at(2*width*i + 2*j + 1) == State::S1) {
 387                                                 if (a == State::S0) match_x = false;
 388                                                 if (a != State::S1) match = false;
 389                                         }
 390                                 }
 391
 392                                 if (match)
 393                                         return State::S1;
 394
 395                                 if (match_x)
 396                                         default_ret = State::Sx;
 397                         }
 398
 399                         return default_ret;
 400                 }
 401
 402                 bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
 403                 bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
 404                 int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
 405                 return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
 406         }
 407
 408         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3)
 409         {
 410                 if (cell->type.in("$mux", "$pmux", "$_MUX_")) {
 411                         RTLIL::Const ret = arg1;
 412                         for (size_t i = 0; i < arg3.bits.size(); i++)
 413                                 if (arg3.bits[i] == RTLIL::State::S1) {
 414                                         std::vector<RTLIL::State> bits(arg2.bits.begin() + i*arg1.bits.size(), arg2.bits.begin() + (i+1)*arg1.bits.size());
 415                                         ret = RTLIL::Const(bits);
 416                                 }
 417                         return ret;
 418                 }
 419
 420                 if (cell->type == "$_AOI3_")
 421                         return eval_not(const_or(const_and(arg1, arg2, false, false, 1), arg3, false, false, 1));
 422                 if (cell->type == "$_OAI3_")
 423                         return eval_not(const_and(const_or(arg1, arg2, false, false, 1), arg3, false, false, 1));
 424
 425                 log_assert(arg3.bits.size() == 0);
 426                 return eval(cell, arg1, arg2);
 427         }
 428
 429         static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2, const RTLIL::Const &arg3, const RTLIL::Const &arg4)
 430         {
 431                 if (cell->type == "$_AOI4_")
 432                         return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 433                 if (cell->type == "$_OAI4_")
 434                         return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
 435
 436                 log_assert(arg4.bits.size() == 0);
 437                 return eval(cell, arg1, arg2, arg3);
 438         }
 439 };
 440
 441 // initialized by yosys_setup()
 442 extern CellTypes yosys_celltypes;
 443
 444 YOSYS_NAMESPACE_END
 445
 446 #endif
 447