2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <kernel/yosys.h>
30 pool
<RTLIL::IdString
> inputs
, outputs
;
36 dict
<RTLIL::IdString
, CellType
> cell_types
;
42 CellTypes(RTLIL::Design
*design
)
47 void setup(RTLIL::Design
*design
= NULL
)
53 setup_internals_mem();
58 void setup_type(RTLIL::IdString type
, const pool
<RTLIL::IdString
> &inputs
, const pool
<RTLIL::IdString
> &outputs
, bool is_evaluable
= false)
60 CellType ct
= {type
, inputs
, outputs
, is_evaluable
};
61 cell_types
[ct
.type
] = ct
;
64 void setup_module(RTLIL::Module
*module
)
66 pool
<RTLIL::IdString
> inputs
, outputs
;
67 for (RTLIL::IdString wire_name
: module
->ports
) {
68 RTLIL::Wire
*wire
= module
->wire(wire_name
);
70 inputs
.insert(wire
->name
);
71 if (wire
->port_output
)
72 outputs
.insert(wire
->name
);
74 setup_type(module
->name
, inputs
, outputs
);
77 void setup_design(RTLIL::Design
*design
)
79 for (auto module
: design
->modules())
83 void setup_internals()
85 std::vector
<RTLIL::IdString
> unary_ops
= {
86 "$not", "$pos", "$neg",
87 "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool",
88 "$logic_not", "$slice", "$lut", "$sop"
91 std::vector
<RTLIL::IdString
> binary_ops
= {
92 "$and", "$or", "$xor", "$xnor",
93 "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
94 "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
95 "$add", "$sub", "$mul", "$div", "$mod", "$pow",
96 "$logic_and", "$logic_or", "$concat", "$macc"
98 IdString A
= "\\A", B
= "\\B", S
= "\\S", Y
= "\\Y";
99 IdString P
= "\\P", G
= "\\G", C
= "\\C", X
= "\\X";
100 IdString BI
= "\\BI", CI
= "\\CI", CO
= "\\CO", EN
= "\\EN";
102 for (auto type
: unary_ops
)
103 setup_type(type
, {A
}, {Y
}, true);
105 for (auto type
: binary_ops
)
106 setup_type(type
, {A
, B
}, {Y
}, true);
108 for (auto type
: std::vector
<RTLIL::IdString
>({"$mux", "$pmux"}))
109 setup_type(type
, {A
, B
, S
}, {Y
}, true);
111 setup_type("$lcu", {P
, G
, CI
}, {CO
}, true);
112 setup_type("$alu", {A
, B
, CI
, BI
}, {X
, Y
, CO
}, true);
113 setup_type("$fa", {A
, B
, C
}, {X
, Y
}, true);
115 setup_type("$tribuf", {A
, EN
}, {Y
}, true);
117 setup_type("$assert", {A
, EN
}, pool
<RTLIL::IdString
>(), true);
118 setup_type("$assume", {A
, EN
}, pool
<RTLIL::IdString
>(), true);
119 setup_type("$live", {A
, EN
}, pool
<RTLIL::IdString
>(), true);
120 setup_type("$fair", {A
, EN
}, pool
<RTLIL::IdString
>(), true);
121 setup_type("$cover", {A
, EN
}, pool
<RTLIL::IdString
>(), true);
122 setup_type("$initstate", pool
<RTLIL::IdString
>(), {Y
}, true);
123 setup_type("$anyconst", pool
<RTLIL::IdString
>(), {Y
}, true);
124 setup_type("$anyseq", pool
<RTLIL::IdString
>(), {Y
}, true);
125 setup_type("$equiv", {A
, B
}, {Y
}, true);
128 void setup_internals_mem()
130 IdString SET
= "\\SET", CLR
= "\\CLR", CLK
= "\\CLK", ARST
= "\\ARST", EN
= "\\EN";
131 IdString Q
= "\\Q", D
= "\\D", ADDR
= "\\ADDR", DATA
= "\\DATA", RD_EN
= "\\RD_EN";
132 IdString RD_CLK
= "\\RD_CLK", RD_ADDR
= "\\RD_ADDR", WR_CLK
= "\\WR_CLK", WR_EN
= "\\WR_EN";
133 IdString WR_ADDR
= "\\WR_ADDR", WR_DATA
= "\\WR_DATA", RD_DATA
= "\\RD_DATA";
134 IdString CTRL_IN
= "\\CTRL_IN", CTRL_OUT
= "\\CTRL_OUT";
136 setup_type("$sr", {SET
, CLR
}, {Q
});
137 setup_type("$ff", {D
}, {Q
});
138 setup_type("$dff", {CLK
, D
}, {Q
});
139 setup_type("$dffe", {CLK
, EN
, D
}, {Q
});
140 setup_type("$dffsr", {CLK
, SET
, CLR
, D
}, {Q
});
141 setup_type("$adff", {CLK
, ARST
, D
}, {Q
});
142 setup_type("$dlatch", {EN
, D
}, {Q
});
143 setup_type("$dlatchsr", {EN
, SET
, CLR
, D
}, {Q
});
145 setup_type("$memrd", {CLK
, EN
, ADDR
}, {DATA
});
146 setup_type("$memwr", {CLK
, EN
, ADDR
, DATA
}, pool
<RTLIL::IdString
>());
147 setup_type("$meminit", {ADDR
, DATA
}, pool
<RTLIL::IdString
>());
148 setup_type("$mem", {RD_CLK
, RD_EN
, RD_ADDR
, WR_CLK
, WR_EN
, WR_ADDR
, WR_DATA
}, {RD_DATA
});
150 setup_type("$fsm", {CLK
, ARST
, CTRL_IN
}, {CTRL_OUT
});
153 void setup_stdcells()
155 IdString A
= "\\A", B
= "\\B", C
= "\\C", D
= "\\D";
156 IdString E
= "\\E", F
= "\\F", G
= "\\G", H
= "\\H";
157 IdString I
= "\\I", J
= "\\J", K
= "\\K", L
= "\\L";
158 IdString M
= "\\I", N
= "\\N", O
= "\\O", P
= "\\P";
159 IdString S
= "\\S", T
= "\\T", U
= "\\U", V
= "\\V";
162 setup_type("$_BUF_", {A
}, {Y
}, true);
163 setup_type("$_NOT_", {A
}, {Y
}, true);
164 setup_type("$_AND_", {A
, B
}, {Y
}, true);
165 setup_type("$_NAND_", {A
, B
}, {Y
}, true);
166 setup_type("$_OR_", {A
, B
}, {Y
}, true);
167 setup_type("$_NOR_", {A
, B
}, {Y
}, true);
168 setup_type("$_XOR_", {A
, B
}, {Y
}, true);
169 setup_type("$_XNOR_", {A
, B
}, {Y
}, true);
170 setup_type("$_MUX_", {A
, B
, S
}, {Y
}, true);
171 setup_type("$_MUX4_", {A
, B
, C
, D
, S
, T
}, {Y
}, true);
172 setup_type("$_MUX8_", {A
, B
, C
, D
, E
, F
, G
, H
, S
, T
, U
}, {Y
}, true);
173 setup_type("$_MUX16_", {A
, B
, C
, D
, E
, F
, G
, H
, I
, J
, K
, L
, M
, N
, O
, P
, S
, T
, U
, V
}, {Y
}, true);
174 setup_type("$_AOI3_", {A
, B
, C
}, {Y
}, true);
175 setup_type("$_OAI3_", {A
, B
, C
}, {Y
}, true);
176 setup_type("$_AOI4_", {A
, B
, C
, D
}, {Y
}, true);
177 setup_type("$_OAI4_", {A
, B
, C
, D
}, {Y
}, true);
178 setup_type("$_TBUF_", {A
, E
}, {Y
}, true);
181 void setup_stdcells_mem()
183 IdString S
= "\\S", R
= "\\R", C
= "\\C";
184 IdString D
= "\\D", Q
= "\\Q", E
= "\\E";
186 std::vector
<char> list_np
= {'N', 'P'}, list_01
= {'0', '1'};
188 for (auto c1
: list_np
)
189 for (auto c2
: list_np
)
190 setup_type(stringf("$_SR_%c%c_", c1
, c2
), {S
, R
}, {Q
});
192 setup_type("$_FF_", {D
}, {Q
});
194 for (auto c1
: list_np
)
195 setup_type(stringf("$_DFF_%c_", c1
), {C
, D
}, {Q
});
197 for (auto c1
: list_np
)
198 for (auto c2
: list_np
)
199 setup_type(stringf("$_DFFE_%c%c_", c1
, c2
), {C
, D
, E
}, {Q
});
201 for (auto c1
: list_np
)
202 for (auto c2
: list_np
)
203 for (auto c3
: list_01
)
204 setup_type(stringf("$_DFF_%c%c%c_", c1
, c2
, c3
), {C
, R
, D
}, {Q
});
206 for (auto c1
: list_np
)
207 for (auto c2
: list_np
)
208 for (auto c3
: list_np
)
209 setup_type(stringf("$_DFFSR_%c%c%c_", c1
, c2
, c3
), {C
, S
, R
, D
}, {Q
});
211 for (auto c1
: list_np
)
212 setup_type(stringf("$_DLATCH_%c_", c1
), {E
, D
}, {Q
});
214 for (auto c1
: list_np
)
215 for (auto c2
: list_np
)
216 for (auto c3
: list_np
)
217 setup_type(stringf("$_DLATCHSR_%c%c%c_", c1
, c2
, c3
), {E
, S
, R
, D
}, {Q
});
225 bool cell_known(RTLIL::IdString type
)
227 return cell_types
.count(type
) != 0;
230 bool cell_output(RTLIL::IdString type
, RTLIL::IdString port
)
232 auto it
= cell_types
.find(type
);
233 return it
!= cell_types
.end() && it
->second
.outputs
.count(port
) != 0;
236 bool cell_input(RTLIL::IdString type
, RTLIL::IdString port
)
238 auto it
= cell_types
.find(type
);
239 return it
!= cell_types
.end() && it
->second
.inputs
.count(port
) != 0;
242 bool cell_evaluable(RTLIL::IdString type
)
244 auto it
= cell_types
.find(type
);
245 return it
!= cell_types
.end() && it
->second
.is_evaluable
;
248 static RTLIL::Const
eval_not(RTLIL::Const v
)
250 for (auto &bit
: v
.bits
)
251 if (bit
== RTLIL::S0
) bit
= RTLIL::S1
;
252 else if (bit
== RTLIL::S1
) bit
= RTLIL::S0
;
256 static RTLIL::Const
eval(RTLIL::IdString type
, const RTLIL::Const
&arg1
, const RTLIL::Const
&arg2
, bool signed1
, bool signed2
, int result_len
)
258 if (type
== "$sshr" && !signed1
)
260 if (type
== "$sshl" && !signed1
)
263 if (type
!= "$sshr" && type
!= "$sshl" && type
!= "$shr" && type
!= "$shl" && type
!= "$shift" && type
!= "$shiftx" &&
264 type
!= "$pos" && type
!= "$neg" && type
!= "$not") {
265 if (!signed1
|| !signed2
)
266 signed1
= false, signed2
= false;
269 #define HANDLE_CELL_TYPE(_t) if (type == "$" #_t) return const_ ## _t(arg1, arg2, signed1, signed2, result_len);
270 HANDLE_CELL_TYPE(not)
271 HANDLE_CELL_TYPE(and)
273 HANDLE_CELL_TYPE(xor)
274 HANDLE_CELL_TYPE(xnor
)
275 HANDLE_CELL_TYPE(reduce_and
)
276 HANDLE_CELL_TYPE(reduce_or
)
277 HANDLE_CELL_TYPE(reduce_xor
)
278 HANDLE_CELL_TYPE(reduce_xnor
)
279 HANDLE_CELL_TYPE(reduce_bool
)
280 HANDLE_CELL_TYPE(logic_not
)
281 HANDLE_CELL_TYPE(logic_and
)
282 HANDLE_CELL_TYPE(logic_or
)
283 HANDLE_CELL_TYPE(shl
)
284 HANDLE_CELL_TYPE(shr
)
285 HANDLE_CELL_TYPE(sshl
)
286 HANDLE_CELL_TYPE(sshr
)
287 HANDLE_CELL_TYPE(shift
)
288 HANDLE_CELL_TYPE(shiftx
)
293 HANDLE_CELL_TYPE(eqx
)
294 HANDLE_CELL_TYPE(nex
)
297 HANDLE_CELL_TYPE(add
)
298 HANDLE_CELL_TYPE(sub
)
299 HANDLE_CELL_TYPE(mul
)
300 HANDLE_CELL_TYPE(div
)
301 HANDLE_CELL_TYPE(mod
)
302 HANDLE_CELL_TYPE(pow
)
303 HANDLE_CELL_TYPE(pos
)
304 HANDLE_CELL_TYPE(neg
)
305 #undef HANDLE_CELL_TYPE
307 if (type
== "$_BUF_")
309 if (type
== "$_NOT_")
310 return eval_not(arg1
);
311 if (type
== "$_AND_")
312 return const_and(arg1
, arg2
, false, false, 1);
313 if (type
== "$_NAND_")
314 return eval_not(const_and(arg1
, arg2
, false, false, 1));
316 return const_or(arg1
, arg2
, false, false, 1);
317 if (type
== "$_NOR_")
318 return eval_not(const_or(arg1
, arg2
, false, false, 1));
319 if (type
== "$_XOR_")
320 return const_xor(arg1
, arg2
, false, false, 1);
321 if (type
== "$_XNOR_")
322 return const_xnor(arg1
, arg2
, false, false, 1);
327 static RTLIL::Const
eval(RTLIL::Cell
*cell
, const RTLIL::Const
&arg1
, const RTLIL::Const
&arg2
)
329 if (cell
->type
== "$slice") {
331 int width
= cell
->parameters
.at("\\Y_WIDTH").as_int();
332 int offset
= cell
->parameters
.at("\\OFFSET").as_int();
333 ret
.bits
.insert(ret
.bits
.end(), arg1
.bits
.begin()+offset
, arg1
.bits
.begin()+offset
+width
);
337 if (cell
->type
== "$concat") {
338 RTLIL::Const ret
= arg1
;
339 ret
.bits
.insert(ret
.bits
.end(), arg2
.bits
.begin(), arg2
.bits
.end());
343 if (cell
->type
== "$lut")
345 int width
= cell
->parameters
.at("\\WIDTH").as_int();
347 std::vector
<RTLIL::State
> t
= cell
->parameters
.at("\\LUT").bits
;
348 while (GetSize(t
) < (1 << width
))
349 t
.push_back(RTLIL::S0
);
350 t
.resize(1 << width
);
352 for (int i
= width
-1; i
>= 0; i
--) {
353 RTLIL::State sel
= arg1
.bits
.at(i
);
354 std::vector
<RTLIL::State
> new_t
;
355 if (sel
== RTLIL::S0
)
356 new_t
= std::vector
<RTLIL::State
>(t
.begin(), t
.begin() + GetSize(t
)/2);
357 else if (sel
== RTLIL::S1
)
358 new_t
= std::vector
<RTLIL::State
>(t
.begin() + GetSize(t
)/2, t
.end());
360 for (int j
= 0; j
< GetSize(t
)/2; j
++)
361 new_t
.push_back(t
[j
] == t
[j
+ GetSize(t
)/2] ? t
[j
] : RTLIL::Sx
);
365 log_assert(GetSize(t
) == 1);
369 if (cell
->type
== "$sop")
371 int width
= cell
->parameters
.at("\\WIDTH").as_int();
372 int depth
= cell
->parameters
.at("\\DEPTH").as_int();
373 std::vector
<RTLIL::State
> t
= cell
->parameters
.at("\\TABLE").bits
;
375 while (GetSize(t
) < width
*depth
*2)
376 t
.push_back(RTLIL::S0
);
378 RTLIL::State default_ret
= State::S0
;
380 for (int i
= 0; i
< depth
; i
++)
385 for (int j
= 0; j
< width
; j
++) {
386 RTLIL::State a
= arg1
.bits
.at(j
);
387 if (t
.at(2*width
*i
+ 2*j
+ 0) == State::S1
) {
388 if (a
== State::S1
) match_x
= false;
389 if (a
!= State::S0
) match
= false;
391 if (t
.at(2*width
*i
+ 2*j
+ 1) == State::S1
) {
392 if (a
== State::S0
) match_x
= false;
393 if (a
!= State::S1
) match
= false;
401 default_ret
= State::Sx
;
407 bool signed_a
= cell
->parameters
.count("\\A_SIGNED") > 0 && cell
->parameters
["\\A_SIGNED"].as_bool();
408 bool signed_b
= cell
->parameters
.count("\\B_SIGNED") > 0 && cell
->parameters
["\\B_SIGNED"].as_bool();
409 int result_len
= cell
->parameters
.count("\\Y_WIDTH") > 0 ? cell
->parameters
["\\Y_WIDTH"].as_int() : -1;
410 return eval(cell
->type
, arg1
, arg2
, signed_a
, signed_b
, result_len
);
413 static RTLIL::Const
eval(RTLIL::Cell
*cell
, const RTLIL::Const
&arg1
, const RTLIL::Const
&arg2
, const RTLIL::Const
&arg3
)
415 if (cell
->type
.in("$mux", "$pmux", "$_MUX_")) {
416 RTLIL::Const ret
= arg1
;
417 for (size_t i
= 0; i
< arg3
.bits
.size(); i
++)
418 if (arg3
.bits
[i
] == RTLIL::State::S1
) {
419 std::vector
<RTLIL::State
> bits(arg2
.bits
.begin() + i
*arg1
.bits
.size(), arg2
.bits
.begin() + (i
+1)*arg1
.bits
.size());
420 ret
= RTLIL::Const(bits
);
425 if (cell
->type
== "$_AOI3_")
426 return eval_not(const_or(const_and(arg1
, arg2
, false, false, 1), arg3
, false, false, 1));
427 if (cell
->type
== "$_OAI3_")
428 return eval_not(const_and(const_or(arg1
, arg2
, false, false, 1), arg3
, false, false, 1));
430 log_assert(arg3
.bits
.size() == 0);
431 return eval(cell
, arg1
, arg2
);
434 static RTLIL::Const
eval(RTLIL::Cell
*cell
, const RTLIL::Const
&arg1
, const RTLIL::Const
&arg2
, const RTLIL::Const
&arg3
, const RTLIL::Const
&arg4
)
436 if (cell
->type
== "$_AOI4_")
437 return eval_not(const_or(const_and(arg1
, arg2
, false, false, 1), const_and(arg3
, arg4
, false, false, 1), false, false, 1));
438 if (cell
->type
== "$_OAI4_")
439 return eval_not(const_and(const_or(arg1
, arg2
, false, false, 1), const_and(arg3
, arg4
, false, false, 1), false, false, 1));
441 log_assert(arg4
.bits
.size() == 0);
442 return eval(cell
, arg1
, arg2
, arg3
);
446 // initialized by yosys_setup()
447 extern CellTypes yosys_celltypes
;